Changeset 7915 in vbox for trunk/src/VBox
- Timestamp:
- Apr 11, 2008 1:12:23 PM (17 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/HostDrivers/Support/SUPDRVShared.c
r7902 r7915 39 39 #include <iprt/process.h> 40 40 #include <iprt/mp.h> 41 #include <iprt/cpuset.h> 41 42 #include <iprt/log.h> 42 43 … … 4138 4139 } 4139 4140 4140 /** 4141 * Determine if the time stamp counters of the CPU cores are asynchronous. 4142 */ 4143 static uint64_t g_aTsc[8][8]; 4144 4141 4142 /** 4143 * Callback used by supdrvDetermineAsyncTSC to read the TSC on a CPU. 4144 * 4145 * @param idCpu Ignored. 4146 * @param pvUser1 Where to put the TSC. 4147 * @param pvUser2 Ignored. 4148 */ 4145 4149 static DECLCALLBACK(void) supdrvDetermineAsyncTscWorker(RTCPUID idCpu, void *pvUser1, void *pvUser2) 4146 4150 { 4147 int iSlot = *(int*)pvUser1; 4148 int iCpu = *(int*)pvUser2; 4149 g_aTsc[iSlot][iCpu] = ASMReadTSC(); 4150 } 4151 4152 /** 4151 *(uint64_t *)pvUser1 = ASMReadTSC(); 4152 } 4153 4154 4155 /** 4156 * Determine if Async GIP mode is required because of TSC drift. 4157 * 4153 4158 * When using the default/normal timer code it is essential that the time stamp counter 4154 4159 * (TSC) runs never backwards, that is, a read operation to the counter should return … … 4157 4162 * case we have to choose the asynchronous timer mode. 4158 4163 * 4159 * @param pu64Diffpointer to the determined difference between different cores.4160 * @return false if the time stamp counters appear to be synchron, true otherwise.4164 * @param pu64Diff pointer to the determined difference between different cores. 4165 * @return false if the time stamp counters appear to be synchron, true otherwise. 4161 4166 */ 4162 4167 bool VBOXCALL supdrvDetermineAsyncTsc(uint64_t *pu64DiffCores) 4163 4168 { 4169 static uint64_t s_aTsc[8][8]; 4164 4170 uint64_t u64Diff, u64DiffMin, u64DiffMax, u64TscLast; 4165 int iSlot, iCpu; 4166 bool fBackwards = false; 4167 int cCpu = RTMpGetOnlineCount(); 4168 4169 if (cCpu < 2) 4171 int iSlot, iCpu, cCpus; 4172 bool fBackwards; 4173 RTCPUSET OnlineCpus; 4174 int rc; 4175 4176 *pu64DiffCores = 1; 4177 4178 RTMpGetOnlineSet(&OnlineCpus); 4179 cCpus = RTCpuSetCount(&OnlineCpus); 4180 if (cCpus < 2) 4170 4181 return false; 4171 4182 4172 if (cCpu > RT_ELEMENTS(g_aTsc)) 4173 cCpu = RT_ELEMENTS(g_aTsc); 4174 4175 for (iSlot = 0; iSlot < RT_ELEMENTS(g_aTsc); iSlot++) 4176 { 4177 for (iCpu = 0; iCpu < cCpu; iCpu++) 4178 RTMpOnSpecific(iCpu, supdrvDetermineAsyncTscWorker, &iSlot, &iCpu); 4179 } 4180 4183 /* 4184 * Collect data from the first 8 online CPUs. 4185 */ 4186 if (cCpus > RT_ELEMENTS(s_aTsc)) 4187 cCpus = RT_ELEMENTS(s_aTsc); 4188 for (iSlot = 0; iSlot < RT_ELEMENTS(s_aTsc); iSlot++) 4189 { 4190 RTCPUID iCpuSet = 0; 4191 for (iCpu = 0; iCpu < cCpus; iCpu++) 4192 { 4193 while (!RTCpuSetIsMember(&OnlineCpus, iCpuSet)) 4194 iCpuSet++; /* skip offline CPU */ 4195 rc = RTMpOnSpecific(RTMpCpuIdFromSetIndex(iCpuSet), supdrvDetermineAsyncTscWorker, &s_aTsc[iSlot][iCpu], NULL); 4196 if (rc == VERR_NOT_SUPPORTED) 4197 return false; 4198 iCpuSet++; 4199 } 4200 } 4201 4202 /* 4203 * Check that the TSC reads are strictly ascending. 4204 */ 4205 fBackwards = false; 4181 4206 u64DiffMin = (uint64_t)~0; 4182 4207 u64TscLast = 0; 4183 for (iSlot = 0; iSlot < RT_ELEMENTS( g_aTsc); iSlot++)4184 { 4185 uint64_t u64Tsc0 = g_aTsc[iSlot][0];4208 for (iSlot = 0; iSlot < RT_ELEMENTS(s_aTsc); iSlot++) 4209 { 4210 uint64_t u64Tsc0 = s_aTsc[iSlot][0]; 4186 4211 u64DiffMax = 0; 4187 4212 if (u64Tsc0 <= u64TscLast) 4188 4213 fBackwards = true; 4189 4214 u64TscLast = u64Tsc0; 4190 for (iCpu = 1; iCpu < cCpu ; iCpu++)4191 { 4192 uint64_t u64TscN = g_aTsc[iSlot][iCpu];4215 for (iCpu = 1; iCpu < cCpus; iCpu++) 4216 { 4217 uint64_t u64TscN = s_aTsc[iSlot][iCpu]; 4193 4218 if (u64TscN <= u64TscLast) 4194 4219 fBackwards = true; 4195 4220 u64TscLast = u64TscN; 4221 4196 4222 u64Diff = u64TscN > u64Tsc0 ? u64TscN - u64Tsc0 : u64Tsc0 - u64TscN; 4197 4223 if (u64DiffMax < u64Diff) … … 4203 4229 /* informational */ 4204 4230 *pu64DiffCores = u64DiffMin; 4205 4231 4206 4232 return fBackwards; 4207 4233 }
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