Changeset 80016 in vbox for trunk/src/VBox/VMM/VMMR3
- Timestamp:
- Jul 26, 2019 5:06:38 PM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 132451
- Location:
- trunk/src/VBox/VMM/VMMR3
- Files:
-
- 1 deleted
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/EM.cpp
r80007 r80016 102 102 AssertCompileMemberAlignment(VM, em.s, 32); 103 103 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding)); 104 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump)); 104 AssertCompile(RT_SIZEOFMEMB(VMCPU, em.s.u.FatalLongJump) <= RT_SIZEOFMEMB(VMCPU, em.s.u.achPaddingFatalLongJump)); 105 AssertCompile(RT_SIZEOFMEMB(VMCPU, em.s) <= RT_SIZEOFMEMB(VMCPU, em.padding)); 105 106 106 107 /* 107 108 * Init the structure. 108 109 */ 109 pVM->em.s.offVM = RT_UOFFSETOF(VM, em.s);110 110 PCFGMNODE pCfgRoot = CFGMR3GetRoot(pVM); 111 111 PCFGMNODE pCfgEM = CFGMR3GetChild(pCfgRoot, "EM"); … … 234 234 pVCpu->em.s.enmState = i == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI; 235 235 pVCpu->em.s.enmPrevState = EMSTATE_NONE; 236 pVCpu->em.s.fForceRAW = false;237 236 pVCpu->em.s.u64TimeSliceStart = 0; /* paranoia */ 238 237 pVCpu->em.s.idxContinueExitRec = UINT16_MAX; 239 240 #ifdef VBOX_WITH_RAW_MODE241 if (VM_IS_RAW_MODE_ENABLED(pVM))242 {243 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);244 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));245 }246 #endif247 238 248 239 # define EM_REG_COUNTER(a, b, c) \ … … 273 264 pVCpu->em.s.pStatsR3 = pStats; 274 265 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats); 275 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);276 266 277 267 # if 1 /* rawmode only? */ … … 402 392 { 403 393 LogFlow(("EMR3Relocate\n")); 404 for (VMCPUID i = 0; i < pVM->cCpus; i++) 405 { 406 PVMCPU pVCpu = &pVM->aCpus[i]; 407 if (pVCpu->em.s.pStatsR3) 408 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3); 409 } 394 RT_NOREF(pVM); 410 395 } 411 396 … … 421 406 { 422 407 /* Reset scheduling state. */ 423 pVCpu->em.s.fForceRAW = false;424 408 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_UNHALT); 425 409 … … 459 443 VMMR3_INT_DECL(int) EMR3Term(PVM pVM) 460 444 { 461 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));462 463 445 #ifdef VBOX_WITH_REM 464 446 PDMR3CritSectDelete(&pVM->em.s.CritSectREM); … … 483 465 PVMCPU pVCpu = &pVM->aCpus[i]; 484 466 485 SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);467 SSMR3PutBool(pSSM, false /*fForceRAW*/); 486 468 487 469 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED); … … 531 513 PVMCPU pVCpu = &pVM->aCpus[i]; 532 514 533 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW); 534 if (RT_FAILURE(rc)) 535 pVCpu->em.s.fForceRAW = false; 515 bool fForceRAWIgnored; 516 int rc = SSMR3GetBool(pSSM, &fForceRAWIgnored); 536 517 AssertRCReturn(rc, rc); 537 518 … … 872 853 case VINF_EM_DBG_STEP: 873 854 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW 874 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER 875 || pVCpu->em.s.fForceRAW /* paranoia */) 876 #ifdef VBOX_WITH_RAW_MODE 877 rc = emR3RawStep(pVM, pVCpu); 878 #else 855 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER) 879 856 AssertLogRelMsgFailedStmt(("Bad EM state."), VERR_EM_INTERNAL_ERROR); 880 #endif881 857 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM) 882 858 rc = EMR3HmSingleInstruction(pVM, pVCpu, 0 /*fFlags*/); … … 979 955 case VINF_EM_HALT: 980 956 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER) 981 {982 #ifdef VBOX_WITH_RAW_MODE983 rc = emR3RawResumeHyper(pVM, pVCpu);984 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))985 continue;986 #else987 957 AssertLogRelMsgFailedReturn(("Not implemented\n"), VERR_EM_INTERNAL_ERROR); 988 #endif989 }990 958 if (rc == VINF_SUCCESS) 991 959 rc = VINF_EM_RESCHEDULE; … … 1422 1390 { 1423 1391 /* 1424 * When forcing raw-mode execution, things are simple.1425 */1426 if (pVCpu->em.s.fForceRAW)1427 return EMSTATE_RAW;1428 1429 /*1430 1392 * We stay in the wait for SIPI state unless explicitly told otherwise. 1431 1393 */ … … 1558 1520 } 1559 1521 1560 # ifdef VBOX_WITH_RAW_MODE1561 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip))1562 {1563 Log2(("raw r0 mode forced: patch code\n"));1564 # ifdef VBOX_WITH_SAFE_STR1565 Assert(pVCpu->cpum.GstCtx.tr.Sel);1566 # endif1567 return EMSTATE_RAW;1568 }1569 # endif /* VBOX_WITH_RAW_MODE */1570 1571 1522 # if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS) 1572 1523 if (!(EFlags.u32 & X86_EFL_IF)) … … 1693 1644 pVCpu->em.s.idxContinueExitRec = UINT16_MAX; 1694 1645 } 1695 1696 #ifdef VBOX_WITH_RAW_MODE1697 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))1698 CSAMR3DoPendingAction(pVM, pVCpu);1699 #endif1700 1646 1701 1647 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) … … 1910 1856 UPDATE_RC(); 1911 1857 } 1912 1913 #ifdef VBOX_WITH_RAW_MODE1914 /*1915 * CSAM page scanning.1916 */1917 if ( !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)1918 && VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))1919 {1920 /** @todo check for 16 or 32 bits code! (D bit in the code selector) */1921 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));1922 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);1923 CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);1924 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);1925 }1926 #endif1927 1858 1928 1859 /* … … 2176 2107 2177 2108 bool fGif = CPUMGetGuestGif(&pVCpu->cpum.GstCtx); 2178 #ifdef VBOX_WITH_RAW_MODE2179 fGif &= !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip);2180 #endif2181 2109 if (fGif) 2182 2110 { … … 2507 2435 VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu) 2508 2436 { 2509 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",2437 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s)\n", 2510 2438 pVM, 2511 2439 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState), 2512 2440 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState), 2513 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState), 2514 pVCpu->em.s.fForceRAW)); 2441 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState) )); 2515 2442 VM_ASSERT_EMT(pVM); 2516 2443 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE … … 2566 2493 rc = emR3ForcedActions(pVM, pVCpu, rc); 2567 2494 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc); 2568 if ( ( rc == VINF_EM_RESCHEDULE_REM 2569 || rc == VINF_EM_RESCHEDULE_HM) 2570 && pVCpu->em.s.fForceRAW) 2495 if ( rc == VINF_EM_RESCHEDULE_REM 2496 || rc == VINF_EM_RESCHEDULE_HM) 2571 2497 rc = VINF_EM_RESCHEDULE_RAW; 2572 2498 } … … 2610 2536 case VINF_EM_RESCHEDULE_HM: 2611 2537 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM); 2612 Assert(!pVCpu->em.s.fForceRAW);2613 2538 if (VM_IS_HM_ENABLED(pVM)) 2614 2539 { … … 2906 2831 */ 2907 2832 case EMSTATE_RAW: 2908 #ifdef VBOX_WITH_RAW_MODE2909 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);2910 #else2911 2833 AssertLogRelMsgFailed(("%Rrc\n", rc)); 2912 2834 rc = VERR_EM_INTERNAL_ERROR; 2913 #endif2914 2835 break; 2915 2836 -
trunk/src/VBox/VMM/VMMR3/EMHM.cpp
r80007 r80016 309 309 return rc; 310 310 311 #ifdef VBOX_WITH_RAW_MODE312 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));313 #endif314 315 311 /* Prefetch pages for EIP and ESP. */ 316 312 /** @todo This is rather expensive. Should investigate if it really helps at all. */ … … 332 328 } 333 329 /** @todo maybe prefetch the supervisor stack page as well */ 334 #ifdef VBOX_WITH_RAW_MODE335 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));336 #endif337 330 } 338 331 … … 401 394 * Process high priority pre-execution raw-mode FFs. 402 395 */ 403 #ifdef VBOX_WITH_RAW_MODE404 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));405 #endif406 396 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 407 397 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) -
trunk/src/VBox/VMM/VMMR3/EMR3Nem.cpp
r80007 r80016 300 300 static int emR3NemForcedActions(PVM pVM, PVMCPU pVCpu) 301 301 { 302 #ifdef VBOX_WITH_RAW_MODE303 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));304 #endif305 306 302 /* 307 303 * Sync page directory should not happen in NEM mode.
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