- Timestamp:
- Jul 29, 2019 9:05:53 PM (5 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r80034 r80054 2184 2184 2185 2185 uint8_t *pbXStates; 2186 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3* pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,2186 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 2 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX, 2187 2187 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates); 2188 2188 AssertLogRelRCReturn(rc, rc); … … 2200 2200 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates); 2201 2201 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates); 2202 pbXStates += cbMaxXState;2203 2204 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;2205 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);2206 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);2207 2202 pbXStates += cbMaxXState; 2208 2203 … … 2313 2308 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3); 2314 2309 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3); 2315 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */2316 2310 2317 2311 /* Recheck the guest DRx values in raw-mode. */ … … 2747 2741 * XSAVE it was moved down till after we've got the count. 2748 2742 */ 2743 CPUMCTX HyperCtxIgnored; 2749 2744 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE) 2750 2745 { 2751 2746 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++) 2752 2747 { 2753 PVMCPU pVCpu = &pVM->aCpus[iCpu]; 2754 X86FXSTATE Ign; 2748 X86FXSTATE Ign; 2755 2749 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL); 2756 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3; 2757 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */ 2758 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 2750 SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 2759 2751 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL); 2760 pVCpu->cpum.s.Hyper.cr3 = uCR3;2761 pVCpu->cpum.s.Hyper.rsp = uRSP;2762 2752 } 2763 2753 } … … 2798 2788 * The XSAVE saved state layout moved the hyper state down here. 2799 2789 */ 2800 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3; 2801 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */ 2802 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL); 2803 pVCpu->cpum.s.Hyper.cr3 = uCR3; 2804 pVCpu->cpum.s.Hyper.rsp = uRSP; 2790 rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL); 2805 2791 AssertRCReturn(rc, rc); 2806 2792 … … 4176 4162 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment); 4177 4163 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment); 4178 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, "."); 4164 4165 pHlp->pfnPrintf(pHlp, 4166 ".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n" 4167 ".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n", 4168 pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], 4169 pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]); 4179 4170 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask); 4180 4171 } -
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
r79830 r80054 2441 2441 pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx; 2442 2442 } 2443 memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));2444 2443 2445 2444 /* Copy the CPU #0 data to the other CPUs. */ 2446 2445 for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++) 2447 {2448 2446 memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 2449 2447 sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState)); 2450 memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],2451 sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));2452 }2453 2448 2454 2449 return VINF_SUCCESS; -
trunk/src/VBox/VMM/include/CPUMInternal.h
r78220 r80054 382 382 383 383 /** 384 * The hypervisor context CPU state (just DRx left now). 385 */ 386 typedef struct CPUMHYPERCTX 387 { 388 /** Debug registers. 389 * @remarks DR4 and DR5 should not be used since they are aliases for 390 * DR6 and DR7 respectively on both AMD and Intel CPUs. 391 * @remarks DR8-15 are currently not supported by AMD or Intel, so 392 * neither do we. 393 */ 394 uint64_t dr[8]; 395 /** @todo eliminiate the rest. */ 396 uint64_t cr3; 397 uint64_t au64Padding[7]; 398 } CPUMHYPERCTX; 399 #ifndef VBOX_FOR_DTRACE_LIB 400 AssertCompileSizeAlignment(CPUMHYPERCTX, 64); 401 #endif 402 /** Pointer to the hypervisor context CPU state. */ 403 typedef CPUMHYPERCTX *PCPUMHYPERCTX; 404 405 406 /** 384 407 * CPUM Data (part of VM) 385 408 */ … … 517 540 * Must be aligned on a 64-byte boundary. */ 518 541 CPUMHOSTCTX Host; 519 /** Hypervisor context. Must be aligned on a 64-byte boundary. */ 520 CPUMCTX Hyper; 542 /** Old hypervisor context, only used for combined DRx values now. 543 * Must be aligned on a 64-byte boundary. */ 544 CPUMHYPERCTX Hyper; 521 545 522 546 #ifdef VBOX_WITH_CRASHDUMP_MAGIC -
trunk/src/VBox/VMM/include/CPUMInternal.mac
r79713 r80054 408 408 409 409 ; 410 ; Hypervisor Context (same as .Guest above).410 ; Hypervisor Context. 411 411 ; 412 412 alignb 64 413 413 .Hyper resq 0 414 .Hyper.eax resq 1 415 .Hyper.ecx resq 1 416 .Hyper.edx resq 1 417 .Hyper.ebx resq 1 418 .Hyper.esp resq 1 419 .Hyper.ebp resq 1 420 .Hyper.esi resq 1 421 .Hyper.edi resq 1 422 .Hyper.r8 resq 1 423 .Hyper.r9 resq 1 424 .Hyper.r10 resq 1 425 .Hyper.r11 resq 1 426 .Hyper.r12 resq 1 427 .Hyper.r13 resq 1 428 .Hyper.r14 resq 1 429 .Hyper.r15 resq 1 430 .Hyper.es.Sel resw 1 431 .Hyper.es.PaddingSel resw 1 432 .Hyper.es.ValidSel resw 1 433 .Hyper.es.fFlags resw 1 434 .Hyper.es.u64Base resq 1 435 .Hyper.es.u32Limit resd 1 436 .Hyper.es.Attr resd 1 437 .Hyper.cs.Sel resw 1 438 .Hyper.cs.PaddingSel resw 1 439 .Hyper.cs.ValidSel resw 1 440 .Hyper.cs.fFlags resw 1 441 .Hyper.cs.u64Base resq 1 442 .Hyper.cs.u32Limit resd 1 443 .Hyper.cs.Attr resd 1 444 .Hyper.ss.Sel resw 1 445 .Hyper.ss.PaddingSel resw 1 446 .Hyper.ss.ValidSel resw 1 447 .Hyper.ss.fFlags resw 1 448 .Hyper.ss.u64Base resq 1 449 .Hyper.ss.u32Limit resd 1 450 .Hyper.ss.Attr resd 1 451 .Hyper.ds.Sel resw 1 452 .Hyper.ds.PaddingSel resw 1 453 .Hyper.ds.ValidSel resw 1 454 .Hyper.ds.fFlags resw 1 455 .Hyper.ds.u64Base resq 1 456 .Hyper.ds.u32Limit resd 1 457 .Hyper.ds.Attr resd 1 458 .Hyper.fs.Sel resw 1 459 .Hyper.fs.PaddingSel resw 1 460 .Hyper.fs.ValidSel resw 1 461 .Hyper.fs.fFlags resw 1 462 .Hyper.fs.u64Base resq 1 463 .Hyper.fs.u32Limit resd 1 464 .Hyper.fs.Attr resd 1 465 .Hyper.gs.Sel resw 1 466 .Hyper.gs.PaddingSel resw 1 467 .Hyper.gs.ValidSel resw 1 468 .Hyper.gs.fFlags resw 1 469 .Hyper.gs.u64Base resq 1 470 .Hyper.gs.u32Limit resd 1 471 .Hyper.gs.Attr resd 1 472 .Hyper.eip resq 1 473 .Hyper.eflags resq 1 474 .Hyper.cr0 resq 1 475 .Hyper.cr2 resq 1 414 .Hyper.dr resq 8 476 415 .Hyper.cr3 resq 1 477 .Hyper.cr4 resq 1478 .Hyper.dr resq 8479 .Hyper.gdtrPadding resw 3480 .Hyper.gdtr resw 0481 .Hyper.gdtr.cbGdt resw 1482 .Hyper.gdtr.pGdt resq 1483 .Hyper.idtrPadding resw 3484 .Hyper.idtr resw 0485 .Hyper.idtr.cbIdt resw 1486 .Hyper.idtr.pIdt resq 1487 .Hyper.ldtr.Sel resw 1488 .Hyper.ldtr.PaddingSel resw 1489 .Hyper.ldtr.ValidSel resw 1490 .Hyper.ldtr.fFlags resw 1491 .Hyper.ldtr.u64Base resq 1492 .Hyper.ldtr.u32Limit resd 1493 .Hyper.ldtr.Attr resd 1494 .Hyper.tr.Sel resw 1495 .Hyper.tr.PaddingSel resw 1496 .Hyper.tr.ValidSel resw 1497 .Hyper.tr.fFlags resw 1498 .Hyper.tr.u64Base resq 1499 .Hyper.tr.u32Limit resd 1500 .Hyper.tr.Attr resd 1501 .Hyper.SysEnter.cs resb 8502 .Hyper.SysEnter.eip resb 8503 .Hyper.SysEnter.esp resb 8504 .Hyper.msrEFER resb 8505 .Hyper.msrSTAR resb 8506 .Hyper.msrPAT resb 8507 .Hyper.msrLSTAR resb 8508 .Hyper.msrCSTAR resb 8509 .Hyper.msrSFMASK resb 8510 .Hyper.msrKERNELGSBASE resb 8511 .Hyper.uMsrPadding0 resb 8512 alignb 8513 .Hyper.aXcr resq 2514 .Hyper.fXStateMask resq 1515 .Hyper.pXStateR0 RTR0PTR_RES 1516 alignb 8517 .Hyper.pXStateR3 RTR3PTR_RES 1518 alignb 8519 .Hyper.pXStateRC RTRCPTR_RES 1520 .Hyper.aoffXState resw 64521 .Hyper.fWorldSwitcher resd 1522 .Hyper.fExtrn resq 1523 alignb 8524 .Hyper.hwvirt.svm.uMsrHSavePa resq 1525 .Hyper.hwvirt.svm.GCPhysVmcb resq 1526 .Hyper.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1527 alignb 8528 .Hyper.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1529 alignb 8530 .Hyper.hwvirt.svm.HostState resb 184531 .Hyper.hwvirt.svm.uPrevPauseTick resq 1532 .Hyper.hwvirt.svm.cPauseFilter resw 1533 .Hyper.hwvirt.svm.cPauseFilterThreshold resw 1534 .Hyper.hwvirt.svm.fInterceptEvents resb 1535 alignb 8536 .Hyper.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1537 alignb 8538 .Hyper.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1539 alignb 8540 .Hyper.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1541 alignb 8542 .Hyper.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1543 alignb 8544 .Hyper.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1545 .Hyper.hwvirt.svm.abPadding0 resb 272546 .Hyper.hwvirt.enmHwvirt resd 1547 .Hyper.hwvirt.fGif resb 1548 alignb 8549 .Hyper.hwvirt.fLocalForcedActions resd 1550 416 alignb 64 551 417
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