Index: trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 80062)
+++ trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 80064)
@@ -27,11 +27,6 @@
 #include <VBox/vmm/mm.h>
 #include <VBox/vmm/em.h>
-#ifndef IN_RC
-# include <VBox/vmm/nem.h>
-# include <VBox/vmm/hm.h>
-#endif
-#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
-# include <VBox/vmm/selm.h>
-#endif
+#include <VBox/vmm/nem.h>
+#include <VBox/vmm/hm.h>
 #include "CPUMInternal.h"
 #include <VBox/vmm/vm.h>
@@ -1030,29 +1025,4 @@
     bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
     pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
-
-#ifdef VBOX_WITH_RAW_MODE_NOT_R0
-    /*
-     * Patch manager saved state legacy pain.
-     */
-    PVM pVM = pVCpu->CTX_SUFF(pVM);
-    PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
-    if (pLeaf)
-    {
-        if (fVisible || (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
-            pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx;
-        else
-            pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx & ~X86_CPUID_FEATURE_EDX_APIC;
-    }
-
-    pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
-    if (pLeaf)
-    {
-        if (fVisible || (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
-            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx;
-        else
-            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx & ~X86_CPUID_AMD_FEATURE_EDX_APIC;
-    }
-#endif
-
     return fOld;
 }
@@ -1312,10 +1282,7 @@
          * In ring-0 we might end up here when just single stepping.
          */
-#if defined(IN_RC) || defined(IN_RING0)
+#ifdef IN_RING0
         if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
         {
-# ifdef IN_RC
-            ASMSetDR7(X86_DR7_INIT_VAL);
-# endif
             if (pVCpu->cpum.s.Hyper.dr[0])
                 ASMSetDR0(0);
@@ -1382,5 +1349,5 @@
         if (fNewComponents)
         {
-#if defined(IN_RING0) || defined(IN_RC)
+#ifdef IN_RING0
             if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
             {
@@ -1618,18 +1585,4 @@
 }
 
-#ifdef IN_RC
-
-/**
- * Lazily sync in the FPU/XMM state.
- *
- * @returns VBox status code.
- * @param   pVCpu       The cross context virtual CPU structure.
- */
-VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
-{
-    return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
-}
-
-#endif /* !IN_RC */
 
 /**
@@ -1784,20 +1737,5 @@
                 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
             else
-            {
                 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
-#ifdef VBOX_WITH_RAW_MODE_NOT_R0
-# ifdef VBOX_WITH_RAW_RING1
-                if (pVCpu->cpum.s.fRawEntered)
-                {
-                    if (uCpl == 1)
-                        uCpl = 0;
-                }
-                Assert(uCpl != 2);  /* ring 2 support not allowed anymore. */
-# else
-                if (uCpl == 1)
-                    uCpl = 0;
-# endif
-#endif
-            }
         }
         else
@@ -2037,5 +1975,4 @@
 VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu)
 {
-#ifndef IN_RC
     /*
      * Return the state of guest-NMI blocking in any of the following cases:
@@ -2059,7 +1996,4 @@
      */
     return CPUMIsGuestVmxVirtNmiBlocking(pVCpu, pCtx);
-#else
-    return VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
-#endif
 }
 
@@ -2073,5 +2007,4 @@
 VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock)
 {
-#ifndef IN_RC
     /*
      * Set the state of guest-NMI blocking in any of the following cases:
@@ -2107,10 +2040,4 @@
      */
     return CPUMSetGuestVmxVirtNmiBlocking(pVCpu, pCtx, fBlock);
-#else
-    if (fBlock)
-        VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
-    else
-        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
-#endif
 }
 
@@ -2129,8 +2056,4 @@
     /** @todo Optimization: Avoid this function call and use a pointer to the
      *        relevant eflags instead (setup during VMRUN instruction emulation). */
-#ifdef IN_RC
-    RT_NOREF2(pVCpu, pCtx);
-    AssertReleaseFailedReturn(false);
-#else
     Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
 
@@ -2142,5 +2065,4 @@
 
     return fEFlags.Bits.u1IF;
-#endif
 }
 
@@ -2158,8 +2080,4 @@
 VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
 {
-#ifdef IN_RC
-    RT_NOREF2(pVCpu, pCtx);
-    AssertReleaseFailedReturn(false);
-#else
     RT_NOREF(pVCpu);
     Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
@@ -2173,5 +2091,4 @@
 
     return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
-#endif
 }
 
@@ -2185,11 +2102,6 @@
 VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
 {
-#ifdef IN_RC
-    RT_NOREF(pCtx);
-    AssertReleaseFailedReturn(0);
-#else
     PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
     return pVmcbCtrl->IntCtrl.n.u8VIntrVector;
-#endif
 }
 
@@ -2266,11 +2178,10 @@
  * @returns The TSC offset after applying any nested-guest TSC offset.
  * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
- * @param   uTicks      The guest TSC.
+ * @param   uTscValue   The guest TSC.
  *
  * @sa      CPUMRemoveNestedGuestTscOffset.
  */
-VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTicks)
-{
-#ifndef IN_RC
+VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
+{
     PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
     if (CPUMIsGuestInVmxNonRootMode(pCtx))
@@ -2279,23 +2190,20 @@
         Assert(pVmcs);
         if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
-            return uTicks + pVmcs->u64TscOffset.u;
-        return uTicks;
+            return uTscValue + pVmcs->u64TscOffset.u;
+        return uTscValue;
     }
 
     if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
     {
-        uint64_t u64TscOffset;
-        if (!HMGetGuestSvmTscOffset(pVCpu, &u64TscOffset))
+        uint64_t offTsc;
+        if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
         {
             PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
             Assert(pVmcb);
-            u64TscOffset = pVmcb->ctrl.u64TSCOffset;
+            offTsc = pVmcb->ctrl.u64TSCOffset;
         }
-        return uTicks + u64TscOffset;
-    }
-#else
-    RT_NOREF(pVCpu);
-#endif
-    return uTicks;
+        return uTscValue + offTsc;
+    }
+    return uTscValue;
 }
 
@@ -2307,11 +2215,10 @@
  * @returns The TSC offset after removing any nested-guest TSC offset.
  * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
- * @param   uTicks      The nested-guest TSC.
+ * @param   uTscValue   The nested-guest TSC.
  *
  * @sa      CPUMApplyNestedGuestTscOffset.
  */
-VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTicks)
-{
-#ifndef IN_RC
+VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
+{
     PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
     if (CPUMIsGuestInVmxNonRootMode(pCtx))
@@ -2321,24 +2228,21 @@
             PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
             Assert(pVmcs);
-            return uTicks - pVmcs->u64TscOffset.u;
+            return uTscValue - pVmcs->u64TscOffset.u;
         }
-        return uTicks;
+        return uTscValue;
     }
 
     if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
     {
-        uint64_t u64TscOffset;
-        if (!HMGetGuestSvmTscOffset(pVCpu, &u64TscOffset))
+        uint64_t offTsc;
+        if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
         {
             PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
             Assert(pVmcb);
-            u64TscOffset = pVmcb->ctrl.u64TSCOffset;
+            offTsc = pVmcb->ctrl.u64TSCOffset;
         }
-        return uTicks - u64TscOffset;
-    }
-#else
-    RT_NOREF(pVCpu);
-#endif
-    return uTicks;
+        return uTscValue - offTsc;
+    }
+    return uTscValue;
 }
 
@@ -2359,5 +2263,4 @@
     if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
     {
-#ifndef IN_RC
         switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
         {
@@ -2383,7 +2286,4 @@
                 AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
         }
-#else
-        AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
-#endif
     }
     return VINF_SUCCESS;
@@ -2538,5 +2438,4 @@
 VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVM pVM, uint64_t u64VmcsField)
 {
-#ifndef IN_RC
     uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
     uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
@@ -2792,8 +2691,4 @@
 
     return false;
-#else
-    RT_NOREF2(pVM, u64VmcsField);
-    return false;
-#endif
 }
 
@@ -2809,5 +2704,4 @@
 VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
 {
-#ifndef IN_RC
     PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
     if (CPUMIsGuestVmxProcCtlsSet(pVCpu, pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
@@ -2824,8 +2718,4 @@
 
     return false;
-#else
-    RT_NOREF3(pVCpu, u16Port, cbAccess);
-    return false;
-#endif
 }
 
@@ -2840,5 +2730,4 @@
 VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
 {
-#ifndef IN_RC
     /*
      * If the CR3-load exiting control is set and the new CR3 value does not
@@ -2867,8 +2756,4 @@
     }
     return false;
-#else
-    RT_NOREF2(pVCpu, uNewCr3);
-    return false;
-#endif
 }
 
@@ -2886,5 +2771,4 @@
 VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
 {
-#ifndef IN_RC
     Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
     Assert(   uExitReason == VMX_EXIT_VMREAD
@@ -2915,8 +2799,4 @@
     Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
     return ASMBitTest(pbBitmap + (u32VmcsField >> 3), u32VmcsField & 7);
-#else
-    RT_NOREF3(pVCpu, uExitReason, u64VmcsField);
-    return false;
-#endif
 }
 
