Changeset 80071 in vbox for trunk/src

Timestamp:

Jul 31, 2019 11:43:16 AM (5 years ago)

Author:

vboxsync

Message:

VMM: Kicking out raw-mode and 32-bit hosts - CPUM. [disasm fixes] bugref:9517 bugref:9511

File:

• trunk/src/VBox/Disassembler/DisasmReg.cpp (modified) (10 diffs)

trunk/src/VBox/Disassembler/DisasmReg.cpp

@@ -25 +25 @@
 #include <iprt/errcore.h>
 #include <VBox/log.h>
-#include <VBox/vmm/cpum.h>
+#ifdef RT_ARCH_AMD64
+# include <VBox/vmm/cpum.h>
+#endif
 #include <iprt/assert.h>
 #include <iprt/string.h>
@@ -35 +37 @@
 *   Global Variables                                                                                                             *
 *********************************************************************************************************************************/
+#ifdef RT_ARCH_AMD64
 
 /**
@@ -63 +66 @@
  * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
  */
-#define DIS_READ_REG64(p, idx)       (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
-#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
-#define DIS_PTR_REG64(p, idx)        ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
+# define DIS_READ_REG64(p, idx)       (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
+# define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
+# define DIS_PTR_REG64(p, idx)        ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
 
 /**
@@ -94 +97 @@
  * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
  */
-#define DIS_READ_REG32(p, idx)       (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
+# define DIS_READ_REG32(p, idx)       (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
 /* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
  * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
@@ -100 +103 @@
  *   there is no need for an instruction movzlq.''
  */
-#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
-#define DIS_PTR_REG32(p, idx)        ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
+# define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
+# define DIS_PTR_REG32(p, idx)        ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
 
 /**
@@ -130 +133 @@
  * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
  */
-#define DIS_READ_REG16(p, idx)          (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
-#define DIS_WRITE_REG16(p, idx, val)    (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
-#define DIS_PTR_REG16(p, idx)           ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
+# define DIS_READ_REG16(p, idx)          (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
+# define DIS_WRITE_REG16(p, idx, val)    (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
+# define DIS_PTR_REG16(p, idx)           ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
 
 /**
@@ -165 +168 @@
  * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
  */
-#define DIS_READ_REG8(p, idx)           (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
-#define DIS_WRITE_REG8(p, idx, val)     (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
-#define DIS_PTR_REG8(p, idx)            ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
+# define DIS_READ_REG8(p, idx)           (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
+# define DIS_WRITE_REG8(p, idx, val)     (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
+# define DIS_PTR_REG8(p, idx)            ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
 
 /**
@@ -196 +199 @@
  * Macro for accessing segment registers in CPUMCTXCORE structure.
  */
-#define DIS_READ_REGSEG(p, idx)         (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
-#define DIS_WRITE_REGSEG(p, idx, val)   (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
+# define DIS_READ_REGSEG(p, idx)         (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
+# define DIS_WRITE_REGSEG(p, idx, val)   (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
+
+#endif /* RT_ARCH_AMD64 */
+
 
 //*****************************************************************************
@@ -334 +340 @@
 
 
+#ifdef RT_ARCH_AMD64
+
 /**
  * Returns the value of the specified 8 bits general purpose register
@@ -835 +843 @@
 }
 
+#endif /* RT_ARCH_AMD64 */
+