Changeset 80094 in vbox
- Timestamp:
- Aug 1, 2019 4:25:23 AM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 132534
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 2 edited
-
HMR0.cpp (modified) (3 diffs)
-
HMVMXR0.cpp (modified) (13 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r80052 r80094 1607 1607 * 1608 1608 * @param pDesc Descriptor to dump. 1609 * @param Sel Selector number.1610 * @param psz Msg Message to prepend the log entry with.1611 */ 1612 VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *psz Msg)1609 * @param Sel The selector. 1610 * @param pszSel The name of the selector. 1611 */ 1612 VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel) 1613 1613 { 1614 1614 /* … … 1693 1693 ADD_STR(psz, "64-bit "); 1694 1694 else 1695 ADD_STR(psz, "Comp 1695 ADD_STR(psz, "Comp "); 1696 1696 # else 1697 1697 if (pDesc->Gen.u1Granularity) … … 1712 1712 1713 1713 # if HC_ARCH_BITS == 64 1714 uint64_t u32Base = X86DESC64_BASE(pDesc);1715 Log((" %s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,1716 Sel, pDesc->au64[0], pDesc->au64[1], u 32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));1714 uint64_t const u64Base = X86DESC64_BASE(pDesc); 1715 Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel, 1716 Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg)); 1717 1717 # else 1718 uint32_t 1719 Log((" %s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,1718 uint32_t const u32Base = X86DESC_BASE(pDesc); 1719 Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel, 1720 1720 Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg)); 1721 1721 # endif 1722 1722 #else 1723 NOREF(Sel); NOREF(psz Msg);1723 NOREF(Sel); NOREF(pszSel); 1724 1724 #endif 1725 1725 } -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r80080 r80094 3036 3036 3037 3037 /* Update VMCS with the VPID. */ 3038 int rc = VMXWriteVmcs 32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);3038 int rc = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid); 3039 3039 AssertRC(rc); 3040 3040 … … 3187 3187 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid)); 3188 3188 3189 int rc = VMXWriteVmcs 32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);3189 int rc = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid); 3190 3190 AssertRC(rc); 3191 3191 } … … 4483 4483 4484 4484 /* Write these host selector fields into the host-state area in the VMCS. */ 4485 int rc = VMXWriteVmcs 32(VMX_VMCS16_HOST_CS_SEL, uSelCS);4486 rc |= VMXWriteVmcs 32(VMX_VMCS16_HOST_SS_SEL, uSelSS);4485 int rc = VMXWriteVmcs16(VMX_VMCS16_HOST_CS_SEL, uSelCS); 4486 rc |= VMXWriteVmcs16(VMX_VMCS16_HOST_SS_SEL, uSelSS); 4487 4487 #if HC_ARCH_BITS == 64 4488 rc |= VMXWriteVmcs 32(VMX_VMCS16_HOST_DS_SEL, uSelDS);4489 rc |= VMXWriteVmcs 32(VMX_VMCS16_HOST_ES_SEL, uSelES);4490 rc |= VMXWriteVmcs 32(VMX_VMCS16_HOST_FS_SEL, uSelFS);4491 rc |= VMXWriteVmcs 32(VMX_VMCS16_HOST_GS_SEL, uSelGS);4488 rc |= VMXWriteVmcs16(VMX_VMCS16_HOST_DS_SEL, uSelDS); 4489 rc |= VMXWriteVmcs16(VMX_VMCS16_HOST_ES_SEL, uSelES); 4490 rc |= VMXWriteVmcs16(VMX_VMCS16_HOST_FS_SEL, uSelFS); 4491 rc |= VMXWriteVmcs16(VMX_VMCS16_HOST_GS_SEL, uSelGS); 4492 4492 #else 4493 4493 NOREF(uSelDS); … … 4496 4496 NOREF(uSelGS); 4497 4497 #endif 4498 rc |= VMXWriteVmcs 32(VMX_VMCS16_HOST_TR_SEL, uSelTR);4498 rc |= VMXWriteVmcs16(VMX_VMCS16_HOST_TR_SEL, uSelTR); 4499 4499 AssertRCReturn(rc, rc); 4500 4500 … … 6436 6436 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */ 6437 6437 6438 rc = VMXWriteVmcs 32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);6438 rc = VMXWriteVmcs16(VMX_VMCS16_GUEST_TR_SEL, u16Sel); 6439 6439 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit); 6440 6440 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights); … … 6479 6479 u32Access = pCtx->ldtr.Attr.u; 6480 6480 6481 rc = VMXWriteVmcs 32(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel);6481 rc = VMXWriteVmcs16(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel); 6482 6482 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit); 6483 6483 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access); … … 6784 6784 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu)); 6785 6785 6786 /* VMX control bits. */ 6787 uint32_t u32Val; 6788 uint64_t u64Val; 6789 RTHCUINTREG uHCReg; 6790 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc); 6791 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val)); 6792 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc); 6793 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val)); 6794 if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS) 6786 static struct 6795 6787 { 6796 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc); 6797 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val)); 6788 /** Name of the field to log. */ 6789 const char *pszName; 6790 /** The VMCS field. */ 6791 uint32_t uVmcsField; 6792 /** Whether host support of this field needs to be checked. */ 6793 bool fCheckSupport; 6794 } const s_aVmcsFields[] = 6795 { 6796 { "VMX_VMCS32_CTRL_PIN_EXEC", VMX_VMCS32_CTRL_PIN_EXEC, false, }, 6797 { "VMX_VMCS32_CTRL_PROC_EXEC", VMX_VMCS32_CTRL_PROC_EXEC, false, }, 6798 { "VMX_VMCS32_CTRL_PROC_EXEC2", VMX_VMCS32_CTRL_PROC_EXEC2, true, }, 6799 { "VMX_VMCS32_CTRL_ENTRY", VMX_VMCS32_CTRL_ENTRY, false, }, 6800 { "VMX_VMCS32_CTRL_EXIT", VMX_VMCS32_CTRL_EXIT, false, }, 6801 { "VMX_VMCS32_CTRL_CR3_TARGET_COUNT", VMX_VMCS32_CTRL_CR3_TARGET_COUNT, false, }, 6802 { "VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO", VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, false, }, 6803 { "VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE", VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, false, }, 6804 { "VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH", VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, false, }, 6805 { "VMX_VMCS32_CTRL_TPR_THRESHOLD", VMX_VMCS32_CTRL_TPR_THRESHOLD, false, }, 6806 { "VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT", VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, false, }, 6807 { "VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT", VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, false, }, 6808 { "VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT", VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, false, }, 6809 { "VMX_VMCS32_CTRL_EXCEPTION_BITMAP", VMX_VMCS32_CTRL_EXCEPTION_BITMAP, false, }, 6810 { "VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK", VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, false, }, 6811 { "VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH", VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, false, }, 6812 { "VMX_VMCS_CTRL_CR0_MASK", VMX_VMCS_CTRL_CR0_MASK, false, }, 6813 { "VMX_VMCS_CTRL_CR0_READ_SHADOW", VMX_VMCS_CTRL_CR0_READ_SHADOW, false, }, 6814 { "VMX_VMCS_CTRL_CR4_MASK", VMX_VMCS_CTRL_CR4_MASK, false, }, 6815 { "VMX_VMCS_CTRL_CR4_READ_SHADOW", VMX_VMCS_CTRL_CR4_READ_SHADOW, false, }, 6816 { "VMX_VMCS64_CTRL_EPTP_FULL", VMX_VMCS64_CTRL_EPTP_FULL, true, }, 6817 { "VMX_VMCS_GUEST_RIP", VMX_VMCS_GUEST_RIP, false, }, 6818 { "VMX_VMCS_GUEST_RSP", VMX_VMCS_GUEST_RSP, false, }, 6819 { "VMX_VMCS_GUEST_RFLAGS", VMX_VMCS_GUEST_RFLAGS, false, }, 6820 { "VMX_VMCS16_VPID", VMX_VMCS16_VPID, true, }, 6821 { "VMX_VMCS_HOST_CR0", VMX_VMCS_HOST_CR0, false, }, 6822 { "VMX_VMCS_HOST_CR3", VMX_VMCS_HOST_CR3, false, }, 6823 { "VMX_VMCS_HOST_CR4", VMX_VMCS_HOST_CR4, false, }, 6824 /* The order of selector fields below are fixed! */ 6825 { "VMX_VMCS16_HOST_ES_SEL", VMX_VMCS16_HOST_ES_SEL, false, }, 6826 { "VMX_VMCS16_HOST_CS_SEL", VMX_VMCS16_HOST_CS_SEL, false, }, 6827 { "VMX_VMCS16_HOST_SS_SEL", VMX_VMCS16_HOST_SS_SEL, false, }, 6828 { "VMX_VMCS16_HOST_DS_SEL", VMX_VMCS16_HOST_DS_SEL, false, }, 6829 { "VMX_VMCS16_HOST_FS_SEL", VMX_VMCS16_HOST_FS_SEL, false, }, 6830 { "VMX_VMCS16_HOST_GS_SEL", VMX_VMCS16_HOST_GS_SEL, false, }, 6831 { "VMX_VMCS16_HOST_TR_SEL", VMX_VMCS16_HOST_TR_SEL, false, }, 6832 /* End of ordered selector fields. */ 6833 { "VMX_VMCS_HOST_TR_BASE", VMX_VMCS_HOST_TR_BASE, false, }, 6834 { "VMX_VMCS_HOST_GDTR_BASE", VMX_VMCS_HOST_GDTR_BASE, false, }, 6835 { "VMX_VMCS_HOST_IDTR_BASE", VMX_VMCS_HOST_IDTR_BASE, false, }, 6836 { "VMX_VMCS32_HOST_SYSENTER_CS", VMX_VMCS32_HOST_SYSENTER_CS, false, }, 6837 { "VMX_VMCS_HOST_SYSENTER_EIP", VMX_VMCS_HOST_SYSENTER_EIP, false, }, 6838 { "VMX_VMCS_HOST_SYSENTER_ESP", VMX_VMCS_HOST_SYSENTER_ESP, false, }, 6839 { "VMX_VMCS_HOST_RSP", VMX_VMCS_HOST_RSP, false, }, 6840 { "VMX_VMCS_HOST_RIP", VMX_VMCS_HOST_RIP, false, } 6841 }; 6842 6843 RTGDTR HostGdtr; 6844 ASMGetGDTR(&HostGdtr); 6845 6846 uint32_t const cVmcsFields = RT_ELEMENTS(s_aVmcsFields); 6847 for (uint32_t i = 0; i < cVmcsFields; i++) 6848 { 6849 uint32_t const uVmcsField = s_aVmcsFields[i].uVmcsField; 6850 6851 bool fSupported; 6852 if (!s_aVmcsFields[i].fCheckSupport) 6853 fSupported = true; 6854 else 6855 { 6856 PVM pVM = pVCpu->CTX_SUFF(pVM); 6857 switch (uVmcsField) 6858 { 6859 case VMX_VMCS64_CTRL_EPTP_FULL: fSupported = pVM->hm.s.fNestedPaging; break; 6860 case VMX_VMCS16_VPID: fSupported = pVM->hm.s.vmx.fVpid; break; 6861 case VMX_VMCS32_CTRL_PROC_EXEC2: 6862 fSupported = RT_BOOL(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS); 6863 break; 6864 default: 6865 AssertMsgFailedReturnVoid(("Failed to provide VMCS field support for %#RX32\n", uVmcsField)); 6866 } 6867 } 6868 6869 if (fSupported) 6870 { 6871 const char *pszName = s_aVmcsFields[i].pszName; 6872 uint8_t const uWidth = RT_BF_GET(uVmcsField, VMX_BF_VMCSFIELD_WIDTH); 6873 switch (uWidth) 6874 { 6875 case VMX_VMCSFIELD_WIDTH_16BIT: 6876 { 6877 uint16_t u16Val; 6878 rc = VMXReadVmcs16(uVmcsField, &u16Val); 6879 AssertRC(rc); 6880 Log4(("%-40s = %#RX16\n", pszName, u16Val)); 6881 6882 if ( uVmcsField >= VMX_VMCS16_HOST_ES_SEL 6883 && uVmcsField <= VMX_VMCS16_HOST_TR_SEL) 6884 { 6885 if (u16Val < HostGdtr.cbGdt) 6886 { 6887 /* Order of selectors in s_apszSel is fixed and matches the order in s_aVmcsFields. */ 6888 static const char * const s_apszSel[] = { "Host ES", "Host CS", "Host SS", "Host DS", 6889 "Host FS", "Host GS", "Host TR" }; 6890 uint8_t const idxSel = RT_BF_GET(uVmcsField, VMX_BF_VMCSFIELD_INDEX); 6891 Assert(idxSel < RT_ELEMENTS(s_apszSel)); 6892 PCX86DESCHC pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u16Val & X86_SEL_MASK)); 6893 hmR0DumpDescriptor(pDesc, u16Val, s_apszSel[idxSel]); 6894 } 6895 else 6896 Log4((" Selector value exceeds GDT limit!\n")); 6897 } 6898 break; 6899 } 6900 6901 case VMX_VMCSFIELD_WIDTH_32BIT: 6902 { 6903 uint32_t u32Val; 6904 rc = VMXReadVmcs32(uVmcsField, &u32Val); 6905 AssertRC(rc); 6906 Log4(("%-40s = %#RX32\n", pszName, u32Val)); 6907 break; 6908 } 6909 6910 case VMX_VMCSFIELD_WIDTH_64BIT: 6911 case VMX_VMCSFIELD_WIDTH_NATURAL: 6912 { 6913 uint64_t u64Val; 6914 rc = VMXReadVmcs64(uVmcsField, &u64Val); 6915 AssertRC(rc); 6916 Log4(("%-40s = %#RX64\n", pszName, u64Val)); 6917 break; 6918 } 6919 } 6920 } 6798 6921 } 6799 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc); 6800 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val)); 6801 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc); 6802 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val)); 6803 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc); 6804 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val)); 6805 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc); 6806 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val)); 6807 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc); 6808 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val)); 6809 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc); 6810 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val)); 6811 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc); 6812 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val)); 6813 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc); 6814 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val)); 6815 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc); 6816 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val)); 6817 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc); 6818 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val)); 6819 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc); 6820 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val)); 6821 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc); 6822 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val)); 6823 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc); 6824 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val)); 6825 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc); 6826 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg)); 6827 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc); 6828 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg)); 6829 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc); 6830 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg)); 6831 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc); 6832 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg)); 6833 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging) 6834 { 6835 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc); 6836 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val)); 6837 } 6838 6839 /* Guest bits. */ 6840 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc); 6841 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rip, u64Val)); 6842 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc); 6843 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rsp, u64Val)); 6844 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc); 6845 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pVCpu->cpum.GstCtx.eflags.u32, u32Val)); 6846 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid) 6847 { 6848 rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc); 6849 Log4(("VMX_VMCS16_VPID %u\n", u32Val)); 6850 } 6851 6852 /* Host bits. */ 6853 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc); 6854 Log4(("Host CR0 %#RHr\n", uHCReg)); 6855 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc); 6856 Log4(("Host CR3 %#RHr\n", uHCReg)); 6857 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc); 6858 Log4(("Host CR4 %#RHr\n", uHCReg)); 6859 6860 RTGDTR HostGdtr; 6861 PCX86DESCHC pDesc; 6862 ASMGetGDTR(&HostGdtr); 6863 rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc); 6864 Log4(("Host CS %#08x\n", u32Val)); 6865 if (u32Val < HostGdtr.cbGdt) 6866 { 6867 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6868 hmR0DumpDescriptor(pDesc, u32Val, "CS: "); 6869 } 6870 6871 rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc); 6872 Log4(("Host DS %#08x\n", u32Val)); 6873 if (u32Val < HostGdtr.cbGdt) 6874 { 6875 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6876 hmR0DumpDescriptor(pDesc, u32Val, "DS: "); 6877 } 6878 6879 rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc); 6880 Log4(("Host ES %#08x\n", u32Val)); 6881 if (u32Val < HostGdtr.cbGdt) 6882 { 6883 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6884 hmR0DumpDescriptor(pDesc, u32Val, "ES: "); 6885 } 6886 6887 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc); 6888 Log4(("Host FS %#08x\n", u32Val)); 6889 if (u32Val < HostGdtr.cbGdt) 6890 { 6891 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6892 hmR0DumpDescriptor(pDesc, u32Val, "FS: "); 6893 } 6894 6895 rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc); 6896 Log4(("Host GS %#08x\n", u32Val)); 6897 if (u32Val < HostGdtr.cbGdt) 6898 { 6899 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6900 hmR0DumpDescriptor(pDesc, u32Val, "GS: "); 6901 } 6902 6903 rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc); 6904 Log4(("Host SS %#08x\n", u32Val)); 6905 if (u32Val < HostGdtr.cbGdt) 6906 { 6907 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6908 hmR0DumpDescriptor(pDesc, u32Val, "SS: "); 6909 } 6910 6911 rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc); 6912 Log4(("Host TR %#08x\n", u32Val)); 6913 if (u32Val < HostGdtr.cbGdt) 6914 { 6915 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK)); 6916 hmR0DumpDescriptor(pDesc, u32Val, "TR: "); 6917 } 6918 6919 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc); 6920 Log4(("Host TR Base %#RHv\n", uHCReg)); 6921 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc); 6922 Log4(("Host GDTR Base %#RHv\n", uHCReg)); 6923 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc); 6924 Log4(("Host IDTR Base %#RHv\n", uHCReg)); 6925 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc); 6926 Log4(("Host SYSENTER CS %#08x\n", u32Val)); 6927 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc); 6928 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg)); 6929 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc); 6930 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg)); 6931 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc); 6932 Log4(("Host RSP %#RHv\n", uHCReg)); 6933 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc); 6934 Log4(("Host RIP %#RHv\n", uHCReg)); 6922 6935 6923 # if HC_ARCH_BITS == 64 6936 6924 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER))); … … 7284 7272 uint32_t const idxBase = g_aVmcsSegBase[iSegReg]; 7285 7273 7274 uint16_t u16Sel; 7286 7275 uint64_t u64Base; 7287 uint32_t u32 Sel, u32Limit, u32Attr;7288 int rc = VMXReadVmcs 32(idxSel, &u32Sel);7276 uint32_t u32Limit, u32Attr; 7277 int rc = VMXReadVmcs16(idxSel, &u16Sel); 7289 7278 rc |= VMXReadVmcs32(idxLimit, &u32Limit); 7290 7279 rc |= VMXReadVmcs32(idxAttr, &u32Attr); … … 7293 7282 { 7294 7283 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg]; 7295 pSelReg->Sel = u 32Sel;7296 pSelReg->ValidSel = u 32Sel;7284 pSelReg->Sel = u16Sel; 7285 pSelReg->ValidSel = u16Sel; 7297 7286 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID; 7298 7287 pSelReg->u32Limit = u32Limit; … … 7317 7306 static int hmR0VmxImportGuestLdtr(PVMCPU pVCpu) 7318 7307 { 7308 uint16_t u16Sel; 7319 7309 uint64_t u64Base; 7320 uint32_t u32 Sel, u32Limit, u32Attr;7321 int rc = VMXReadVmcs 32(VMX_VMCS16_GUEST_LDTR_SEL, &u32Sel);7310 uint32_t u32Limit, u32Attr; 7311 int rc = VMXReadVmcs16(VMX_VMCS16_GUEST_LDTR_SEL, &u16Sel); 7322 7312 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, &u32Limit); 7323 7313 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, &u32Attr); … … 7325 7315 if (RT_SUCCESS(rc)) 7326 7316 { 7327 pVCpu->cpum.GstCtx.ldtr.Sel = u 32Sel;7328 pVCpu->cpum.GstCtx.ldtr.ValidSel = u 32Sel;7317 pVCpu->cpum.GstCtx.ldtr.Sel = u16Sel; 7318 pVCpu->cpum.GstCtx.ldtr.ValidSel = u16Sel; 7329 7319 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID; 7330 7320 pVCpu->cpum.GstCtx.ldtr.u32Limit = u32Limit; … … 7349 7339 static int hmR0VmxImportGuestTr(PVMCPU pVCpu) 7350 7340 { 7351 uint 32_t u32Sel, u32Limit, u32Attr;7341 uint16_t u16Sel; 7352 7342 uint64_t u64Base; 7353 int rc = VMXReadVmcs32(VMX_VMCS16_GUEST_TR_SEL, &u32Sel); 7343 uint32_t u32Limit, u32Attr; 7344 int rc = VMXReadVmcs16(VMX_VMCS16_GUEST_TR_SEL, &u16Sel); 7354 7345 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, &u32Limit); 7355 7346 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, &u32Attr); … … 7357 7348 AssertRCReturn(rc, rc); 7358 7349 7359 pVCpu->cpum.GstCtx.tr.Sel = u 32Sel;7360 pVCpu->cpum.GstCtx.tr.ValidSel = u 32Sel;7350 pVCpu->cpum.GstCtx.tr.Sel = u16Sel; 7351 pVCpu->cpum.GstCtx.tr.ValidSel = u16Sel; 7361 7352 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID; 7362 7353 pVCpu->cpum.GstCtx.tr.u32Limit = u32Limit;
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