Changeset 80346 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Aug 19, 2019 7:36:29 PM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 132811
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h
r80334 r80346 36 36 # define NEMWIN_NEED_GET_REGISTER 37 37 # if defined(IN_RING0) || defined(NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS) 38 # define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_ pGVCpu, a_enmReg, a_Expr, a_Msg) \38 # define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) \ 39 39 do { \ 40 40 HV_REGISTER_VALUE TmpVal; \ 41 nemHCWinGetRegister(a_pVCpu, a_ pGVCpu, a_enmReg, &TmpVal); \41 nemHCWinGetRegister(a_pVCpu, a_enmReg, &TmpVal); \ 42 42 AssertMsg(a_Expr, a_Msg); \ 43 43 } while (0) 44 44 # else 45 # define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_ pGVCpu, a_enmReg, a_Expr, a_Msg) \45 # define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) \ 46 46 do { \ 47 47 WHV_REGISTER_VALUE TmpVal; \ … … 51 51 # endif 52 52 #else 53 # define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_ pGVCpu, a_enmReg, a_Expr, a_Msg) do { } while (0)53 # define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) do { } while (0) 54 54 #endif 55 55 … … 57 57 * Asserts the correctness of a 64-bit register value in a message/context. 58 58 */ 59 #define NEMWIN_ASSERT_MSG_REG_VAL64(a_pVCpu, a_ pGVCpu, a_enmReg, a_u64Val) \60 NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_ pGVCpu, a_enmReg, (a_u64Val) == TmpVal.Reg64, \59 #define NEMWIN_ASSERT_MSG_REG_VAL64(a_pVCpu, a_enmReg, a_u64Val) \ 60 NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, (a_u64Val) == TmpVal.Reg64, \ 61 61 (#a_u64Val "=%#RX64, expected %#RX64\n", (a_u64Val), TmpVal.Reg64)) 62 62 /** @def NEMWIN_ASSERT_MSG_REG_VAL 63 63 * Asserts the correctness of a segment register value in a message/context. 64 64 */ 65 #define NEMWIN_ASSERT_MSG_REG_SEG(a_pVCpu, a_ pGVCpu, a_enmReg, a_SReg) \66 NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_ pGVCpu, a_enmReg, \65 #define NEMWIN_ASSERT_MSG_REG_SEG(a_pVCpu, a_enmReg, a_SReg) \ 66 NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, \ 67 67 (a_SReg).Base == TmpVal.Segment.Base \ 68 68 && (a_SReg).Limit == TmpVal.Segment.Limit \ … … 109 109 #ifdef IN_RING0 110 110 /** @todo optimize further, caller generally has the physical address. */ 111 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM); 112 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE); 113 return nemR0WinMapPages(pGVM, pVM, &pGVM->aCpus[pVCpu->idCpu], 111 return nemR0WinMapPages(pVM, pVCpu, 114 112 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, 115 113 GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, … … 136 134 { 137 135 # ifdef IN_RING0 138 PGVM pGVM = GVMMR0FastGetGVMByVM(pVM); 139 AssertReturn(pGVM, VERR_INVALID_VM_HANDLE); 140 return nemR0WinUnmapPages(pGVM, &pGVM->aCpus[pVCpu->idCpu], GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, 1); 136 return nemR0WinUnmapPages(pVM, pVCpu, GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, 1); 141 137 # else 142 138 pVCpu->nem.s.Hypercall.UnmapPages.GCPhys = GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK; … … 398 394 ADD_REG64(WHvX64RegisterTscAux, pCtxMsrs->msr.TscAux); 399 395 #if 0 /** @todo these registers aren't available? Might explain something.. .*/ 400 const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(p GVM->pVM);396 const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM); 401 397 if (enmCpuVendor != CPUMCPUVENDOR_AMD) 402 398 { … … 665 661 666 662 //#ifdef LOG_ENABLED 667 // const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(p GVM->pVM);663 // const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM); 668 664 //#endif 669 665 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS) … … 1291 1287 AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API); 1292 1288 1293 pInput->PartitionId = p GVCpu->pGVM->nemr0.s.idHvPartition;1294 pInput->VpIndex = p GVCpu->idCpu;1289 pInput->PartitionId = pVCpu->pGVM->nemr0.s.idHvPartition; 1290 pInput->VpIndex = pVCpu->idCpu; 1295 1291 pInput->fFlags = 0; 1296 1292 pInput->Names[0] = (HV_REGISTER_NAME)enmReg; … … 1823 1819 * @param pGVM The global (ring-0) VM structure. 1824 1820 * @param pGVCpu The global (ring-0) per CPU structure. 1821 * @param fWhat What to import. 1822 * @param pszCaller Who is doing the importing. 1823 */ 1824 DECLINLINE(VBOXSTRICTRC) nemR0WinImportStateStrict(PGVM pGVM, PGVMCPU pGVCpu, uint64_t fWhat, const char *pszCaller) 1825 { 1826 int rc = nemR0WinImportState(pGVM, pGVCpu, &pGVCpu->cpum.GstCtx, fWhat, true /*fCanUpdateCr3*/); 1827 if (RT_SUCCESS(rc)) 1828 { 1829 Assert(rc == VINF_SUCCESS); 1830 return VINF_SUCCESS; 1831 } 1832 1833 if (rc == VERR_NEM_FLUSH_TLB) 1834 { 1835 Log4(("%s/%u: nemR0WinImportState -> %Rrc\n", pszCaller, pGVCpu->idCpu, -rc)); 1836 return -rc; 1837 } 1838 RT_NOREF(pszCaller); 1839 AssertMsgFailedReturn(("%s/%u: nemR0WinImportState failed: %Rrc\n", pszCaller, pGVCpu->idCpu, rc), rc); 1840 } 1841 #endif /* IN_RING0 && NEM_WIN_TEMPLATE_MODE_OWN_RUN_API*/ 1842 1843 #if defined(NEM_WIN_TEMPLATE_MODE_OWN_RUN_API) || defined(IN_RING3) 1844 /** 1845 * Wrapper around nemR0WinImportStateStrict and nemHCWinCopyStateFromHyperV. 1846 * 1847 * Unlike the wrapped APIs, this checks whether it's necessary. 1848 * 1849 * @returns VBox strict status code. 1825 1850 * @param pVCpu The cross context per CPU structure. 1826 1851 * @param fWhat What to import. 1827 1852 * @param pszCaller Who is doing the importing. 1828 1853 */ 1829 DECLINLINE(VBOXSTRICTRC) nemR0WinImportStateStrict(PGVM pGVM, PGVMCPU pGVCpu, PVMCPUCC pVCpu, uint64_t fWhat, const char *pszCaller) 1830 { 1831 int rc = nemR0WinImportState(pGVM, pGVCpu, &pVCpu->cpum.GstCtx, fWhat, true /*fCanUpdateCr3*/); 1832 if (RT_SUCCESS(rc)) 1833 { 1834 Assert(rc == VINF_SUCCESS); 1835 return VINF_SUCCESS; 1836 } 1837 1838 if (rc == VERR_NEM_FLUSH_TLB) 1839 { 1840 Log4(("%s/%u: nemR0WinImportState -> %Rrc\n", pszCaller, pGVCpu->idCpu, -rc)); 1841 return -rc; 1842 } 1843 RT_NOREF(pszCaller); 1844 AssertMsgFailedReturn(("%s/%u: nemR0WinImportState failed: %Rrc\n", pszCaller, pGVCpu->idCpu, rc), rc); 1845 } 1846 #endif /* IN_RING0 && NEM_WIN_TEMPLATE_MODE_OWN_RUN_API*/ 1847 1848 #if defined(NEM_WIN_TEMPLATE_MODE_OWN_RUN_API) || defined(IN_RING3) 1849 /** 1850 * Wrapper around nemR0WinImportStateStrict and nemHCWinCopyStateFromHyperV. 1851 * 1852 * Unlike the wrapped APIs, this checks whether it's necessary. 1853 * 1854 * @returns VBox strict status code. 1855 * @param pGVM The global (ring-0) VM structure. 1856 * @param pGVCpu The global (ring-0) per CPU structure. 1857 * @param fWhat What to import. 1858 * @param pszCaller Who is doing the importing. 1859 */ 1860 DECLINLINE(VBOXSTRICTRC) nemHCWinImportStateIfNeededStrict(PVMCPUCC pVCpu, PGVMCPU pGVCpu, uint64_t fWhat, const char *pszCaller) 1854 DECLINLINE(VBOXSTRICTRC) nemHCWinImportStateIfNeededStrict(PVMCPUCC pVCpu, uint64_t fWhat, const char *pszCaller) 1861 1855 { 1862 1856 if (pVCpu->cpum.GstCtx.fExtrn & fWhat) 1863 1857 { 1864 1858 # ifdef IN_RING0 1865 return nemR0WinImportStateStrict(p GVCpu->pGVM, pGVCpu, pVCpu, fWhat, pszCaller);1859 return nemR0WinImportStateStrict(pVCpu->pGVM, pVCpu, fWhat, pszCaller); 1866 1860 # else 1867 RT_NOREF(p GVCpu, pszCaller);1861 RT_NOREF(pszCaller); 1868 1862 int rc = nemHCWinCopyStateFromHyperV(pVCpu->pVMR3, pVCpu, fWhat); 1869 1863 AssertRCReturn(rc, rc); … … 1947 1941 * @param pVCpu The cross context per CPU structure. 1948 1942 * @param pMsg The message. 1949 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).1950 1943 * @sa nemR3WinHandleExitMemory 1951 1944 */ 1952 1945 NEM_TMPL_STATIC VBOXSTRICTRC 1953 nemHCWinHandleMessageMemory(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_MEMORY_INTERCEPT_MESSAGE const *pMsg , PGVMCPU pGVCpu)1946 nemHCWinHandleMessageMemory(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_MEMORY_INTERCEPT_MESSAGE const *pMsg) 1954 1947 { 1955 1948 uint64_t const uHostTsc = ASMReadTSC(); … … 2030 2023 VBOXSTRICTRC rcStrict; 2031 2024 # ifdef IN_RING0 2032 rcStrict = nemR0WinImportStateStrict(p GVCpu->pGVM, pGVCpu, pVCpu,2025 rcStrict = nemR0WinImportStateStrict(pVM, pVCpu, 2033 2026 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES, "MemExit"); 2034 2027 if (rcStrict != VINF_SUCCESS) … … 2037 2030 rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES); 2038 2031 AssertRCReturn(rc, rc); 2039 NOREF(pGVCpu);2040 2032 # endif 2041 2033 … … 2172 2164 * @param pVCpu The cross context per CPU structure. 2173 2165 * @param pMsg The message. 2174 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).2175 2166 */ 2176 2167 NEM_TMPL_STATIC VBOXSTRICTRC 2177 nemHCWinHandleMessageIoPort(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_IO_PORT_INTERCEPT_MESSAGE const *pMsg , PGVMCPU pGVCpu)2168 nemHCWinHandleMessageIoPort(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_IO_PORT_INTERCEPT_MESSAGE const *pMsg) 2178 2169 { 2179 2170 /* … … 2185 2176 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ 2186 2177 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE); 2187 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterCs, pMsg->Header.CsSegment);2188 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRip, pMsg->Header.Rip);2189 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRflags, pMsg->Header.Rflags);2190 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);2191 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRax, pMsg->Rax);2178 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterCs, pMsg->Header.CsSegment); 2179 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRip, pMsg->Header.Rip); 2180 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRflags, pMsg->Header.Rflags); 2181 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8); 2182 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRax, pMsg->Rax); 2192 2183 if (pMsg->AccessInfo.StringOp) 2193 2184 { 2194 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterDs, pMsg->DsSegment);2195 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterEs, pMsg->EsSegment);2196 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRcx, pMsg->Rcx);2197 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRsi, pMsg->Rsi);2198 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRdi, pMsg->Rdi);2185 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterDs, pMsg->DsSegment); 2186 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterEs, pMsg->EsSegment); 2187 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRcx, pMsg->Rcx); 2188 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRsi, pMsg->Rsi); 2189 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRdi, pMsg->Rdi); 2199 2190 } 2200 2191 … … 2308 2299 pVCpu->cpum.GstCtx.rsi = pMsg->Rsi; 2309 2300 # ifdef IN_RING0 2310 rcStrict = nemR0WinImportStateStrict(p GVCpu->pGVM, pGVCpu, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IOExit");2301 rcStrict = nemR0WinImportStateStrict(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IOExit"); 2311 2302 if (rcStrict != VINF_SUCCESS) 2312 2303 return rcStrict; … … 2314 2305 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM); 2315 2306 AssertRCReturn(rc, rc); 2316 RT_NOREF(pGVCpu);2317 2307 # endif 2318 2308 … … 2359 2349 2360 2350 # ifdef IN_RING0 2361 rcStrict = nemR0WinImportStateStrict(p GVCpu->pGVM, pGVCpu, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IOExit");2351 rcStrict = nemR0WinImportStateStrict(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "IOExit"); 2362 2352 if (rcStrict != VINF_SUCCESS) 2363 2353 return rcStrict; … … 2365 2355 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM); 2366 2356 AssertRCReturn(rc, rc); 2367 RT_NOREF(pGVCpu);2368 2357 # endif 2369 2358 … … 2554 2543 * @param pVCpu The cross context per CPU structure. 2555 2544 * @param pMsg The message. 2556 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).2557 2545 * @sa nemR3WinHandleExitInterruptWindow 2558 2546 */ 2559 2547 NEM_TMPL_STATIC VBOXSTRICTRC 2560 nemHCWinHandleMessageInterruptWindow(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_INTERRUPT_WINDOW_MESSAGE const *pMsg , PGVMCPU pGVCpu)2548 nemHCWinHandleMessageInterruptWindow(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_INTERRUPT_WINDOW_MESSAGE const *pMsg) 2561 2549 { 2562 2550 /* … … 2580 2568 2581 2569 /** @todo call nemHCWinHandleInterruptFF */ 2582 RT_NOREF(pVM , pGVCpu);2570 RT_NOREF(pVM); 2583 2571 return VINF_SUCCESS; 2584 2572 } … … 2629 2617 * @param pVCpu The cross context per CPU structure. 2630 2618 * @param pMsg The message. 2631 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).2632 2619 * @sa nemR3WinHandleExitCpuId 2633 2620 */ 2634 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageCpuId(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_CPUID_INTERCEPT_MESSAGE const *pMsg, 2635 PGVMCPU pGVCpu) 2621 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageCpuId(PVMCC pVM, PVMCPUCC pVCpu, HV_X64_CPUID_INTERCEPT_MESSAGE const *pMsg) 2636 2622 { 2637 2623 /* Check message register value sanity. */ 2638 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterCs, pMsg->Header.CsSegment);2639 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRip, pMsg->Header.Rip);2640 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRflags, pMsg->Header.Rflags);2641 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);2642 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRax, pMsg->Rax);2643 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRcx, pMsg->Rcx);2644 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRdx, pMsg->Rdx);2645 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRbx, pMsg->Rbx);2624 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterCs, pMsg->Header.CsSegment); 2625 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRip, pMsg->Header.Rip); 2626 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRflags, pMsg->Header.Rflags); 2627 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8); 2628 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRax, pMsg->Rax); 2629 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRcx, pMsg->Rcx); 2630 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRdx, pMsg->Rdx); 2631 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRbx, pMsg->Rbx); 2646 2632 2647 2633 /* Do exit history. */ … … 2698 2684 pMsg->DefaultResultRax, pMsg->DefaultResultRcx, pMsg->DefaultResultRdx, pMsg->DefaultResultRbx)); 2699 2685 # ifdef IN_RING0 2700 VBOXSTRICTRC rcStrict = nemR0WinImportStateStrict(p GVCpu->pGVM, pGVCpu, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "CpuIdExit");2686 VBOXSTRICTRC rcStrict = nemR0WinImportStateStrict(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM, "CpuIdExit"); 2701 2687 if (rcStrict != VINF_SUCCESS) 2702 2688 return rcStrict; … … 2705 2691 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM); 2706 2692 AssertRCReturn(rc, rc); 2707 RT_NOREF(pGVCpu);2708 2693 # endif 2709 2694 VBOXSTRICTRC rcStrictExec = EMHistoryExec(pVCpu, pExitRec, 0); … … 2796 2781 * @param pVCpu The cross context per CPU structure. 2797 2782 * @param pMsg The message. 2798 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).2799 2783 * @sa nemR3WinHandleExitMsr 2800 2784 */ 2801 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageMsr(PVMCPUCC pVCpu, HV_X64_MSR_INTERCEPT_MESSAGE const *pMsg , PGVMCPU pGVCpu)2785 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleMessageMsr(PVMCPUCC pVCpu, HV_X64_MSR_INTERCEPT_MESSAGE const *pMsg) 2802 2786 { 2803 2787 /* … … 2806 2790 Assert( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ 2807 2791 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE); 2808 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterCs, pMsg->Header.CsSegment);2809 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRip, pMsg->Header.Rip);2810 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRflags, pMsg->Header.Rflags);2811 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);2812 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRax, pMsg->Rax);2813 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRdx, pMsg->Rdx);2792 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterCs, pMsg->Header.CsSegment); 2793 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRip, pMsg->Header.Rip); 2794 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRflags, pMsg->Header.Rflags); 2795 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8); 2796 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRax, pMsg->Rax); 2797 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRdx, pMsg->Rdx); 2814 2798 2815 2799 /* … … 2830 2814 2831 2815 nemHCWinCopyStateFromX64Header(pVCpu, &pMsg->Header); 2832 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu,2816 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, 2833 2817 (!pExitRec ? 0 : IEM_CPUMCTX_EXTRN_MUST_MASK) 2834 2818 | CPUMCTX_EXTRN_ALL_MSRS | CPUMCTX_EXTRN_CR0 … … 2930 2914 * If we get down here, we're supposed to #GP(0). 2931 2915 */ 2932 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu,NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL_MSRS, "MSR");2916 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL_MSRS, "MSR"); 2933 2917 if (rcStrict == VINF_SUCCESS) 2934 2918 { … … 2969 2953 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); 2970 2954 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext); 2971 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NULL,2955 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, 2972 2956 (!pExitRec ? 0 : IEM_CPUMCTX_EXTRN_MUST_MASK) 2973 2957 | CPUMCTX_EXTRN_ALL_MSRS | CPUMCTX_EXTRN_CR0 … … 3056 3040 * If we get down here, we're supposed to #GP(0). 3057 3041 */ 3058 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NULL, 3059 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL_MSRS, "MSR"); 3042 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL_MSRS, "MSR"); 3060 3043 if (rcStrict == VINF_SUCCESS) 3061 3044 { … … 3195 3178 * @param pVCpu The cross context per CPU structure. 3196 3179 * @param pMsg The message. 3197 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).3198 3180 * @sa nemR3WinHandleExitMsr 3199 3181 */ 3200 3182 NEM_TMPL_STATIC VBOXSTRICTRC 3201 nemHCWinHandleMessageException(PVMCPUCC pVCpu, HV_X64_EXCEPTION_INTERCEPT_MESSAGE const *pMsg , PGVMCPU pGVCpu)3183 nemHCWinHandleMessageException(PVMCPUCC pVCpu, HV_X64_EXCEPTION_INTERCEPT_MESSAGE const *pMsg) 3202 3184 { 3203 3185 /* … … 3207 3189 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE 3208 3190 || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE); 3209 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterCs, pMsg->Header.CsSegment);3210 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRip, pMsg->Header.Rip);3211 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRflags, pMsg->Header.Rflags);3212 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);3213 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterDs, pMsg->DsSegment);3214 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterSs, pMsg->SsSegment);3215 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRax, pMsg->Rax);3216 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRcx, pMsg->Rcx);3217 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRdx, pMsg->Rdx);3218 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRbx, pMsg->Rbx);3219 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRsp, pMsg->Rsp);3220 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRbp, pMsg->Rbp);3221 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRsi, pMsg->Rsi);3222 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRdi, pMsg->Rdi);3223 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR8, pMsg->R8);3224 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR9, pMsg->R9);3225 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR10, pMsg->R10);3226 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR11, pMsg->R11);3227 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR12, pMsg->R12);3228 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR13, pMsg->R13);3229 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR14, pMsg->R14);3230 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterR15, pMsg->R15);3191 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterCs, pMsg->Header.CsSegment); 3192 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRip, pMsg->Header.Rip); 3193 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRflags, pMsg->Header.Rflags); 3194 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8); 3195 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterDs, pMsg->DsSegment); 3196 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterSs, pMsg->SsSegment); 3197 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRax, pMsg->Rax); 3198 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRcx, pMsg->Rcx); 3199 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRdx, pMsg->Rdx); 3200 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRbx, pMsg->Rbx); 3201 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRsp, pMsg->Rsp); 3202 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRbp, pMsg->Rbp); 3203 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRsi, pMsg->Rsi); 3204 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRdi, pMsg->Rdi); 3205 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR8, pMsg->R8); 3206 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR9, pMsg->R9); 3207 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR10, pMsg->R10); 3208 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR11, pMsg->R11); 3209 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR12, pMsg->R12); 3210 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR13, pMsg->R13); 3211 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR14, pMsg->R14); 3212 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterR15, pMsg->R15); 3231 3213 3232 3214 /* … … 3243 3225 if (pMsg->ExceptionVector == X86_XCPT_DB) 3244 3226 fWhat |= CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6; 3245 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu,fWhat, "Xcpt");3227 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, fWhat, "Xcpt"); 3246 3228 if (rcStrict != VINF_SUCCESS) 3247 3229 return rcStrict; … … 3341 3323 if (pExit->VpException.ExceptionType == X86_XCPT_DB) 3342 3324 fWhat |= CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6; 3343 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NULL,fWhat, "Xcpt");3325 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, fWhat, "Xcpt"); 3344 3326 if (rcStrict != VINF_SUCCESS) 3345 3327 return rcStrict; … … 3431 3413 * @param pVCpu The cross context per CPU structure. 3432 3414 * @param pMsgHdr The message header. 3433 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).3434 3415 * @sa nemR3WinHandleExitUnrecoverableException 3435 3416 */ 3436 3417 NEM_TMPL_STATIC VBOXSTRICTRC 3437 nemHCWinHandleMessageUnrecoverableException(PVMCPUCC pVCpu, HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr , PGVMCPU pGVCpu)3418 nemHCWinHandleMessageUnrecoverableException(PVMCPUCC pVCpu, HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr) 3438 3419 { 3439 3420 /* Check message register value sanity. */ 3440 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, pGVCpu,HvX64RegisterCs, pMsgHdr->CsSegment);3441 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRip, pMsgHdr->Rip);3442 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterRflags, pMsgHdr->Rflags);3443 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu,HvX64RegisterCr8, (uint64_t)pMsgHdr->Cr8);3421 NEMWIN_ASSERT_MSG_REG_SEG( pVCpu, HvX64RegisterCs, pMsgHdr->CsSegment); 3422 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRip, pMsgHdr->Rip); 3423 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterRflags, pMsgHdr->Rflags); 3424 NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, HvX64RegisterCr8, (uint64_t)pMsgHdr->Cr8); 3444 3425 3445 3426 # if 0 … … 3458 3439 pMsgHdr->Rip + pMsgHdr->CsSegment.Base, ASMReadTSC()); 3459 3440 nemHCWinCopyStateFromX64Header(pVCpu, pMsgHdr); 3460 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, 3461 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL, "TripleExit"); 3441 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL, "TripleExit"); 3462 3442 if (rcStrict == VINF_SUCCESS) 3463 3443 { … … 3511 3491 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); 3512 3492 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext); 3513 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NULL, 3514 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL, "TripleExit"); 3493 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL, "TripleExit"); 3515 3494 if (rcStrict == VINF_SUCCESS) 3516 3495 { … … 3549 3528 * @param pVCpu The cross context per CPU structure. 3550 3529 * @param pMappingHeader The message slot mapping. 3551 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).3552 3530 * @sa nemR3WinHandleExit 3553 3531 */ 3554 3532 NEM_TMPL_STATIC VBOXSTRICTRC 3555 nemHCWinHandleMessage(PVMCC pVM, PVMCPUCC pVCpu, VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader , PGVMCPU pGVCpu)3533 nemHCWinHandleMessage(PVMCC pVM, PVMCPUCC pVCpu, VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader) 3556 3534 { 3557 3535 if (pMappingHeader->enmVidMsgType == VidMessageHypervisorMessage) … … 3564 3542 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment)); 3565 3543 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemUnmapped); 3566 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept , pGVCpu);3544 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept); 3567 3545 3568 3546 case HvMessageTypeGpaIntercept: 3569 3547 Assert(pMsg->Header.PayloadSize == RT_UOFFSETOF(HV_X64_MEMORY_INTERCEPT_MESSAGE, DsSegment)); 3570 3548 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemIntercept); 3571 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept , pGVCpu);3549 return nemHCWinHandleMessageMemory(pVM, pVCpu, &pMsg->X64MemoryIntercept); 3572 3550 3573 3551 case HvMessageTypeX64IoPortIntercept: 3574 3552 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64IoPortIntercept)); 3575 3553 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitPortIo); 3576 return nemHCWinHandleMessageIoPort(pVM, pVCpu, &pMsg->X64IoPortIntercept , pGVCpu);3554 return nemHCWinHandleMessageIoPort(pVM, pVCpu, &pMsg->X64IoPortIntercept); 3577 3555 3578 3556 case HvMessageTypeX64Halt: … … 3586 3564 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64InterruptWindow)); 3587 3565 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInterruptWindow); 3588 return nemHCWinHandleMessageInterruptWindow(pVM, pVCpu, &pMsg->X64InterruptWindow , pGVCpu);3566 return nemHCWinHandleMessageInterruptWindow(pVM, pVCpu, &pMsg->X64InterruptWindow); 3589 3567 3590 3568 case HvMessageTypeX64CpuidIntercept: 3591 3569 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64CpuIdIntercept)); 3592 3570 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitCpuId); 3593 return nemHCWinHandleMessageCpuId(pVM, pVCpu, &pMsg->X64CpuIdIntercept , pGVCpu);3571 return nemHCWinHandleMessageCpuId(pVM, pVCpu, &pMsg->X64CpuIdIntercept); 3594 3572 3595 3573 case HvMessageTypeX64MsrIntercept: 3596 3574 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64MsrIntercept)); 3597 3575 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMsr); 3598 return nemHCWinHandleMessageMsr(pVCpu, &pMsg->X64MsrIntercept , pGVCpu);3576 return nemHCWinHandleMessageMsr(pVCpu, &pMsg->X64MsrIntercept); 3599 3577 3600 3578 case HvMessageTypeX64ExceptionIntercept: 3601 3579 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64ExceptionIntercept)); 3602 3580 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitException); 3603 return nemHCWinHandleMessageException(pVCpu, &pMsg->X64ExceptionIntercept , pGVCpu);3581 return nemHCWinHandleMessageException(pVCpu, &pMsg->X64ExceptionIntercept); 3604 3582 3605 3583 case HvMessageTypeUnrecoverableException: 3606 3584 Assert(pMsg->Header.PayloadSize == sizeof(pMsg->X64InterceptHeader)); 3607 3585 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitUnrecoverable); 3608 return nemHCWinHandleMessageUnrecoverableException(pVCpu, &pMsg->X64InterceptHeader , pGVCpu);3586 return nemHCWinHandleMessageUnrecoverableException(pVCpu, &pMsg->X64InterceptHeader); 3609 3587 3610 3588 case HvMessageTypeInvalidVpRegisterValue: … … 3712 3690 * @returns NT status code. 3713 3691 * @param pGVM The ring-0 VM structure. 3714 * @param pGVCpu The ring-0 CPU structure. 3715 * @param pVCpu The calling cross context CPU structure. 3692 * @param pGVCpu The global (ring-0) per CPU structure. 3716 3693 * @param fFlags The wait flags. 3717 3694 * @param cMillies The timeout in milliseconds 3718 3695 */ 3719 static NTSTATUS nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(PGVM pGVM, PGVMCPU pGVCpu, PVMCPUCC pVCpu, 3720 uint32_t fFlags, uint32_t cMillies) 3721 { 3722 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu; 3723 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = fFlags; 3724 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMillies; 3725 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pVCpu, pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.uFunction, 3726 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext, 3696 static NTSTATUS nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(PGVM pGVM, PGVMCPU pGVCpu, uint32_t fFlags, uint32_t cMillies) 3697 { 3698 pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu; 3699 pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = fFlags; 3700 pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMillies; 3701 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVCpu, pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.uFunction, 3702 &pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext, 3727 3703 pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.cbInput, 3728 3704 NULL, 0); … … 3740 3716 || rcNt == STATUS_USER_APC /* just in case */) 3741 3717 { 3742 DBGFTRACE_CUSTOM(p VCpu->CTX_SUFF(pVM), "IoCtlMessageSlotHandleAndGetNextRestart/1 %#x (f=%#x)", rcNt, fFlags);3743 STAM_REL_COUNTER_INC(&p VCpu->nem.s.StatStopCpuPendingAlerts);3718 DBGFTRACE_CUSTOM(pGVCpu->CTX_SUFF(pVM), "IoCtlMessageSlotHandleAndGetNextRestart/1 %#x (f=%#x)", rcNt, fFlags); 3719 STAM_REL_COUNTER_INC(&pGVCpu->nem.s.StatStopCpuPendingAlerts); 3744 3720 Assert(fFlags & VID_MSHAGN_F_GET_NEXT_MESSAGE); 3745 3721 3746 p VCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pVCpu->idCpu;3747 p VCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = fFlags & ~VID_MSHAGN_F_HANDLE_MESSAGE;3748 p VCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMillies;3749 rcNt = nemR0NtPerformIoControl(pGVM, p VCpu, pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.uFunction,3750 &p VCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext,3722 pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pGVCpu->idCpu; 3723 pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = fFlags & ~VID_MSHAGN_F_HANDLE_MESSAGE; 3724 pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMillies; 3725 rcNt = nemR0NtPerformIoControl(pGVM, pGVCpu, pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.uFunction, 3726 &pGVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext, 3751 3727 pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.cbInput, 3752 3728 NULL, 0); 3753 DBGFTRACE_CUSTOM(p VCpu->CTX_SUFF(pVM), "IoCtlMessageSlotHandleAndGetNextRestart/2 %#x", rcNt);3729 DBGFTRACE_CUSTOM(pGVM, "IoCtlMessageSlotHandleAndGetNextRestart/2 %#x", rcNt); 3754 3730 } 3755 3731 return rcNt; 3756 3732 } 3757 3758 3733 #endif /* IN_RING0 */ 3759 3734 … … 3774 3749 * exit. 3775 3750 * @param pMappingHeader The message slot mapping. 3776 * @param pGVM The global (ring-0) VM structure (NULL in r3).3777 * @param pGVCpu The global (ring-0) per CPU structure (NULL in r3).3778 3751 */ 3779 3752 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinStopCpu(PVMCC pVM, PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict, 3780 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader, 3781 PGVM pGVM, PGVMCPU pGVCpu) 3753 VID_MESSAGE_MAPPING_HEADER volatile *pMappingHeader) 3782 3754 { 3783 3755 # ifdef DBGFTRACE_ENABLED … … 3791 3763 DBGFTRACE_CUSTOM(pVM, "nemStop#0"); 3792 3764 # ifdef IN_RING0 3793 pVCpu->nem.s.uIoCtlBuf.idCpu = p GVCpu->idCpu;3794 NTSTATUS rcNt = nemR0NtPerformIoControl(p GVM, pVCpu, pGVM->nemr0.s.IoCtlStopVirtualProcessor.uFunction,3765 pVCpu->nem.s.uIoCtlBuf.idCpu = pVCpu->idCpu; 3766 NTSTATUS rcNt = nemR0NtPerformIoControl(pVM, pVCpu, pVM->nemr0.s.IoCtlStopVirtualProcessor.uFunction, 3795 3767 &pVCpu->nem.s.uIoCtlBuf.idCpu, sizeof(pVCpu->nem.s.uIoCtlBuf.idCpu), 3796 3768 NULL, 0); … … 3811 3783 return rcStrict; 3812 3784 } 3813 RT_NOREF(pGVM, pGVCpu);3814 3785 # endif 3815 3786 … … 3835 3806 */ 3836 3807 # ifdef IN_RING0 3837 rcNt = nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(p GVM, pGVCpu, pVCpu, VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/);3808 rcNt = nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(pVM, pVCpu, VID_MSHAGN_F_GET_NEXT_MESSAGE, 30000 /*ms*/); 3838 3809 DBGFTRACE_CUSTOM(pVM, "nemStop#1: %#x / %#x %#x %#x", rcNt, pMappingHeader->enmVidMsgType, pMappingHeader->cbMessage, 3839 3810 pMsgForTrace->Header.MessageType); … … 3853 3824 if (enmVidMsgType != VidMessageStopRequestComplete) 3854 3825 { 3855 VBOXSTRICTRC rcStrict2 = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader , pGVCpu);3826 VBOXSTRICTRC rcStrict2 = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader); 3856 3827 if (rcStrict2 != VINF_SUCCESS && RT_SUCCESS(rcStrict)) 3857 3828 rcStrict = rcStrict2; … … 3863 3834 */ 3864 3835 # ifdef IN_RING0 3865 rcNt = nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(p GVM, pGVCpu, pVCpu,3836 rcNt = nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(pVM, pVCpu, 3866 3837 VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE, 3867 3838 30000 /*ms*/); … … 3891 3862 */ 3892 3863 # ifdef IN_RING0 3893 rcNt = nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(p GVM, pGVCpu, pVCpu, VID_MSHAGN_F_HANDLE_MESSAGE, 30000 /*ms*/);3864 rcNt = nemR0NtPerformIoCtlMessageSlotHandleAndGetNext(pVM, pVCpu, VID_MSHAGN_F_HANDLE_MESSAGE, 30000 /*ms*/); 3894 3865 DBGFTRACE_CUSTOM(pVM, "nemStop#3: %#x / %#x %#x %#x", rcNt, pMappingHeader->enmVidMsgType, 3895 3866 pMsgForTrace->Header.MessageType, pMappingHeader->cbMessage, pMsgForTrace->Header.MessageType); … … 3927 3898 * @param pVM The cross context VM structure. 3928 3899 * @param pVCpu The cross context per CPU structure. 3929 * @param pGVCpu The global (ring-0) per CPU structure.3930 3900 * @param pfInterruptWindows Where to return interrupt window flags. 3931 3901 */ 3932 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleInterruptFF(PVMCC pVM, PVMCPUCC pVCpu, PGVMCPU pGVCpu,uint8_t *pfInterruptWindows)3902 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleInterruptFF(PVMCC pVM, PVMCPUCC pVCpu, uint8_t *pfInterruptWindows) 3933 3903 { 3934 3904 Assert(!TRPMHasTrap(pVCpu)); … … 3961 3931 if (pVCpu->cpum.GstCtx.fExtrn & fNeedExtrn) 3962 3932 { 3963 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, 3964 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "IntFF"); 3933 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "IntFF"); 3965 3934 if (rcStrict != VINF_SUCCESS) 3966 3935 return rcStrict; … … 3977 3946 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)) 3978 3947 { 3979 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, 3980 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI"); 3948 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI"); 3981 3949 if (rcStrict == VINF_SUCCESS) 3982 3950 { … … 4000 3968 { 4001 3969 AssertCompile(NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT & CPUMCTX_EXTRN_APIC_TPR); 4002 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, pGVCpu, 4003 NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI"); 3970 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI"); 4004 3971 if (rcStrict == VINF_SUCCESS) 4005 3972 { … … 4035 4002 * @param pVM The cross context VM structure. 4036 4003 * @param pVCpu The cross context per CPU structure. 4037 * @param pGVM The ring-0 VM structure (NULL in ring-3).4038 * @param pGVCpu The ring-0 per CPU structure (NULL in ring-3).4039 4004 */ 4040 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVMCC pVM, PVMCPUCC pVCpu , PGVM pGVM, PGVMCPU pGVCpu)4005 NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVMCC pVM, PVMCPUCC pVCpu) 4041 4006 { 4042 4007 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags)); … … 4044 4009 if (LogIs3Enabled()) 4045 4010 nemHCWinLogState(pVM, pVCpu); 4046 # endif4047 # ifdef IN_RING04048 Assert(pVCpu->idCpu == pGVCpu->idCpu);4049 4011 # endif 4050 4012 … … 4102 4064 { 4103 4065 pVCpu->nem.s.fHandleAndGetFlags = 0; 4104 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader , pGVM, pGVCpu);4066 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader); 4105 4067 if (rcStrict == VINF_SUCCESS) 4106 4068 { /* likely */ } … … 4115 4077 4116 4078 /* Try inject interrupt. */ 4117 rcStrict = nemHCWinHandleInterruptFF(pVM, pVCpu, pGVCpu,&pVCpu->nem.s.fDesiredInterruptWindows);4079 rcStrict = nemHCWinHandleInterruptFF(pVM, pVCpu, &pVCpu->nem.s.fDesiredInterruptWindows); 4118 4080 if (rcStrict == VINF_SUCCESS) 4119 4081 { /* likely */ } … … 4148 4110 # endif 4149 4111 # ifdef IN_RING0 4150 int rc2 = nemR0WinExportState(p GVM, pGVCpu, &pVCpu->cpum.GstCtx);4112 int rc2 = nemR0WinExportState(pVM, pVCpu, &pVCpu->cpum.GstCtx); 4151 4113 # else 4152 4114 int rc2 = nemHCWinCopyStateToHyperV(pVM, pVCpu); 4153 RT_NOREF(pGVM, pGVCpu);4154 4115 # endif 4155 4116 AssertRCReturn(rc2, rc2); … … 4176 4137 { 4177 4138 # ifdef IN_RING0 4178 pVCpu->nem.s.uIoCtlBuf.idCpu = p GVCpu->idCpu;4179 NTSTATUS rcNt = nemR0NtPerformIoControl(p GVM, pVCpu, pGVM->nemr0.s.IoCtlStartVirtualProcessor.uFunction,4139 pVCpu->nem.s.uIoCtlBuf.idCpu = pVCpu->idCpu; 4140 NTSTATUS rcNt = nemR0NtPerformIoControl(pVM, pVCpu, pVM->nemr0.s.IoCtlStartVirtualProcessor.uFunction, 4180 4141 &pVCpu->nem.s.uIoCtlBuf.idCpu, sizeof(pVCpu->nem.s.uIoCtlBuf.idCpu), 4181 4142 NULL, 0); 4182 4143 LogFlow(("NEM/%u: IoCtlStartVirtualProcessor -> %#x\n", pVCpu->idCpu, rcNt)); 4183 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("VidStartVirtualProcessor failed for CPU #%u: %#x\n", p GVCpu->idCpu, rcNt),4144 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("VidStartVirtualProcessor failed for CPU #%u: %#x\n", pVCpu->idCpu, rcNt), 4184 4145 VERR_NEM_IPE_5); 4185 4146 # else … … 4211 4172 cMsWait = RT_MS_1SEC; 4212 4173 # ifdef IN_RING0 4213 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = p GVCpu->idCpu;4174 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.iCpu = pVCpu->idCpu; 4214 4175 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.fFlags = pVCpu->nem.s.fHandleAndGetFlags; 4215 4176 pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext.cMillies = cMsWait; 4216 NTSTATUS rcNt = nemR0NtPerformIoControl(p GVM, pVCpu, pGVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.uFunction,4177 NTSTATUS rcNt = nemR0NtPerformIoControl(pVM, pVCpu, pVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.uFunction, 4217 4178 &pVCpu->nem.s.uIoCtlBuf.MsgSlotHandleAndGetNext, 4218 p GVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.cbInput,4179 pVM->nemr0.s.IoCtlMessageSlotHandleAndGetNext.cbInput, 4219 4180 NULL, 0); 4220 4181 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT); … … 4238 4199 */ 4239 4200 # ifdef NEM_WIN_TEMPLATE_MODE_OWN_RUN_API 4240 rcStrict = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader , pGVCpu);4201 rcStrict = nemHCWinHandleMessage(pVM, pVCpu, pMappingHeader); 4241 4202 pVCpu->nem.s.fHandleAndGetFlags |= VID_MSHAGN_F_HANDLE_MESSAGE; 4242 4203 # else … … 4315 4276 { 4316 4277 pVCpu->nem.s.fHandleAndGetFlags = 0; 4317 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader , pGVM, pGVCpu);4278 rcStrict = nemHCWinStopCpu(pVM, pVCpu, rcStrict, pMappingHeader); 4318 4279 } 4319 4280 # endif … … 4343 4304 { 4344 4305 # ifdef IN_RING0 4345 int rc2 = nemR0WinImportState(p GVM, pGVCpu, &pVCpu->cpum.GstCtx, fImport | CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT,4306 int rc2 = nemR0WinImportState(pVM, pVCpu, &pVCpu->cpum.GstCtx, fImport | CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT, 4346 4307 true /*fCanUpdateCr3*/); 4347 4308 if (RT_SUCCESS(rc2))
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