Changeset 80598 in vbox
- Timestamp:
- Sep 5, 2019 7:56:07 AM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 133119
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r80595 r80598 4576 4576 Assert(hmR0VmxGetFixedCr0Mask(pVCpu) & X86_CR0_PG); 4577 4577 if ( (pCtx->cr4 & X86_CR4_PAE) 4578 && (pCtx->cr0 & X86_CR0_PG) 4579 && (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE)) 4580 { 4581 /* Assert that host is NX capable. */ 4582 Assert(pVCpu->CTX_SUFF(pVM)->cpum.ro.HostFeatures.fNoExecute); 4583 return true; 4578 && (pCtx->cr0 & X86_CR0_PG)) 4579 { 4580 /* 4581 * If nested paging is not used, verify that the guest paging mode matches the 4582 * shadow paging mode which is/will be placed in the VMCS (which is what will 4583 * actually be used while executing the guest and not the CR4 shadow value). 4584 */ 4585 AssertMsg(pVM->hm.s.fNestedPaging || ( pVCpu->hm.s.enmShadowMode == PGMMODE_PAE 4586 || pVCpu->hm.s.enmShadowMode == PGMMODE_PAE_NX 4587 || pVCpu->hm.s.enmShadowMode == PGMMODE_AMD64 4588 || pVCpu->hm.s.enmShadowMode == PGMMODE_AMD64_NX), 4589 ("enmShadowMode=%u\n", pVCpu->hm.s.enmShadowMode)); 4590 if ((u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE)) 4591 { 4592 /* Verify that the host is NX capable. */ 4593 Assert(pVCpu->CTX_SUFF(pVM)->cpum.ro.HostFeatures.fNoExecute); 4594 return true; 4595 } 4584 4596 } 4585 4597 … … 5650 5662 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */ 5651 5663 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */ 5664 { 5652 5665 #ifdef VBOX_WITH_64_BITS_GUESTS 5666 /* For our assumption in hmR0VmxShouldSwapEferMsr. */ 5667 Assert(u64GuestCr4 & X86_CR4_PAE); 5653 5668 break; 5654 5669 #endif 5670 } 5655 5671 default: 5656 5672 AssertFailed();
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