Changeset 80721 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Library/SmmCpuFeaturesLib
- Timestamp:
- Sep 11, 2019 8:46:37 AM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 133262
- Location:
- trunk/src/VBox/Devices/EFI/FirmwareNew
- Files:
-
- 3 edited
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. (modified) (1 prop)
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OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c (modified) (32 diffs)
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OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/EFI/FirmwareNew
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Property svn:mergeinfo
changed from (toggle deleted branches)
to (toggle deleted branches)/vendor/edk2/current 103735-103757,103769-103776,129194-129237 /vendor/edk2/current 103735-103757,103769-103776,129194-133213
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Property svn:mergeinfo
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trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
r77662 r80721 1 1 /** @file 2 The CPU specific programming for PiSmmCpuDxeSmm module. 3 4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #include <PiSmm.h> 16 #include <Library/SmmCpuFeaturesLib.h> 2 The CPU specific programming for PiSmmCpuDxeSmm module. 3 4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 **/ 8 17 9 #include <Library/BaseLib.h> 18 10 #include <Library/BaseMemoryLib.h> 19 #include <Library/PcdLib.h> 20 #include <Library/MemoryAllocationLib.h> 11 #include <Library/DebugLib.h> 12 #include <Library/MemEncryptSevLib.h> 13 #include <Library/SmmCpuFeaturesLib.h> 21 14 #include <Library/SmmServicesTableLib.h> 22 #include <Library/DebugLib.h> 15 #include <Library/UefiBootServicesTableLib.h> 16 #include <PiSmm.h> 23 17 #include <Register/QemuSmramSaveStateMap.h> 24 18 … … 88 82 // Configure SMBASE. 89 83 // 90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); 84 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( 85 SMM_DEFAULT_SMBASE + 86 SMRAM_SAVE_STATE_MAP_OFFSET 87 ); 91 88 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) { 92 89 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; … … 118 115 @param[in] CpuIndex The index of the CPU to hook. The value 119 116 must be between 0 and the NumberOfCpus 120 field in the System Management System Table121 (SMST).117 field in the System Management System 118 Table (SMST). 122 119 @param[in] CpuState Pointer to SMRAM Save State Map for the 123 120 currently executing CPU. … … 141 138 { 142 139 UINT64 OriginalInstructionPointer; 143 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState; 144 140 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; 141 142 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState; 145 143 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { 146 144 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP; … … 184 182 ) 185 183 { 184 EFI_STATUS Status; 185 UINTN MapPagesBase; 186 UINTN MapPagesCount; 187 188 if (!MemEncryptSevIsEnabled ()) { 189 return; 190 } 191 192 // 193 // Now that SMBASE relocation is complete, re-encrypt the original SMRAM save 194 // state map's container pages, and release the pages to DXE. (The pages were 195 // allocated in PlatformPei.) 196 // 197 Status = MemEncryptSevLocateInitialSmramSaveStateMapPages ( 198 &MapPagesBase, 199 &MapPagesCount 200 ); 201 ASSERT_EFI_ERROR (Status); 202 203 Status = MemEncryptSevSetPageEncMask ( 204 0, // Cr3BaseAddress -- use current CR3 205 MapPagesBase, // BaseAddress 206 MapPagesCount, // NumPages 207 TRUE // Flush 208 ); 209 if (EFI_ERROR (Status)) { 210 DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n", 211 __FUNCTION__, Status)); 212 ASSERT (FALSE); 213 CpuDeadLoop (); 214 } 215 216 ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount)); 217 218 Status = gBS->FreePages (MapPagesBase, MapPagesCount); 219 ASSERT_EFI_ERROR (Status); 186 220 } 187 221 … … 192 226 193 227 @retval 0 Use the default SMI handler. 194 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler() 195 The caller is required to allocate enough SMRAM for each CPU to 196 support the size of the custom SMI handler. 228 @retval > 0 Use the SMI handler installed by 229 SmmCpuFeaturesInstallSmiHandler(). The caller is required to 230 allocate enough SMRAM for each CPU to support the size of the 231 custom SMI handler. 197 232 **/ 198 233 UINTN … … 206 241 207 242 /** 208 Install a custom SMI handler for the CPU specified by CpuIndex. This function209 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater210 than zero and is called by the CPU that was elected as monarch during System211 Management Mode initialization.243 Install a custom SMI handler for the CPU specified by CpuIndex. This 244 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size 245 is greater than zero and is called by the CPU that was elected as monarch 246 during System Management Mode initialization. 212 247 213 248 @param[in] CpuIndex The index of the CPU to install the custom SMI handler. … … 264 299 265 300 /** 266 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()267 returns TRUE.301 Disable SMRR register if SMRR is supported and 302 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE. 268 303 **/ 269 304 VOID … … 279 314 280 315 /** 281 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()282 returns TRUE.316 Enable SMRR register if SMRR is supported and 317 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE. 283 318 **/ 284 319 VOID … … 314 349 Processor specific hook point each time a CPU exits System Management Mode. 315 350 316 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must317 be between 0 and the NumberOfCpus field in the System318 Management System Table (SMST).351 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value 352 must be between 0 and the NumberOfCpus field in the 353 System Management System Table (SMST). 319 354 **/ 320 355 VOID … … 400 435 401 436 /// 402 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY 437 /// Macro used to simplify the lookup table entries of type 438 /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY 403 439 /// 404 440 #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field) 405 441 406 442 /// 407 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE 443 /// Macro used to simplify the lookup table entries of type 444 /// CPU_SMM_SAVE_STATE_REGISTER_RANGE 408 445 /// 409 446 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } … … 438 475 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY 439 476 /// 440 static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = { 441 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO), 442 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP), 443 SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4), 477 STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = { 478 SMM_REGISTER_RANGE ( 479 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, 480 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO 481 ), 482 SMM_REGISTER_RANGE ( 483 EFI_SMM_SAVE_STATE_REGISTER_ES, 484 EFI_SMM_SAVE_STATE_REGISTER_RIP 485 ), 486 SMM_REGISTER_RANGE ( 487 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, 488 EFI_SMM_SAVE_STATE_REGISTER_CR4 489 ), 444 490 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 } 445 491 }; … … 449 495 /// supported EFI_SMM_SAVE_STATE_REGISTER value 450 496 /// 451 static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = { 452 {0, 0, 0, 0, 0, FALSE}, // Reserved 497 STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = { 498 { 499 0, // Width32 500 0, // Width64 501 0, // Offset32 502 0, // Offset64Lo 503 0, // Offset64Hi 504 FALSE // Writeable 505 }, // Reserved 453 506 454 507 // 455 508 // CPU Save State registers defined in PI SMM CPU Protocol. 456 509 // 457 {0, 8, 0 , SMM_CPU_OFFSET (x64._GDTRBase) , SMM_CPU_OFFSET (x64._GDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4 458 {0, 8, 0 , SMM_CPU_OFFSET (x64._IDTRBase) , SMM_CPU_OFFSET (x64._IDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5 459 {0, 8, 0 , SMM_CPU_OFFSET (x64._LDTRBase) , SMM_CPU_OFFSET (x64._LDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6 460 {0, 0, 0 , SMM_CPU_OFFSET (x64._GDTRLimit), SMM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7 461 {0, 0, 0 , SMM_CPU_OFFSET (x64._IDTRLimit), SMM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8 462 {0, 0, 0 , SMM_CPU_OFFSET (x64._LDTRLimit), SMM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9 463 {0, 0, 0 , 0 , 0 + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10 464 465 {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20 466 {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21 467 {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22 468 {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23 469 {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24 470 {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25 471 {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26 472 {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27 473 {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28 474 {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29 475 {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30 476 {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31 477 {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32 478 {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33 479 {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34 480 {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35 481 {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36 482 {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37 483 {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38 484 {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 485 {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40 486 {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41 487 {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42 488 {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43 489 {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44 490 {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45 491 {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46 492 493 {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51 494 {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52 495 {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53 496 {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54 510 { 511 0, // Width32 512 8, // Width64 513 0, // Offset32 514 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo 515 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi 516 FALSE // Writeable 517 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4 518 519 { 520 0, // Width32 521 8, // Width64 522 0, // Offset32 523 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo 524 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi 525 FALSE // Writeable 526 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5 527 528 { 529 0, // Width32 530 8, // Width64 531 0, // Offset32 532 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo 533 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi 534 FALSE // Writeable 535 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6 536 537 { 538 0, // Width32 539 0, // Width64 540 0, // Offset32 541 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo 542 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi 543 FALSE // Writeable 544 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7 545 546 { 547 0, // Width32 548 0, // Width64 549 0, // Offset32 550 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo 551 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi 552 FALSE // Writeable 553 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8 554 555 { 556 0, // Width32 557 0, // Width64 558 0, // Offset32 559 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo 560 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi 561 FALSE // Writeable 562 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9 563 564 { 565 0, // Width32 566 0, // Width64 567 0, // Offset32 568 0, // Offset64Lo 569 0 + 4, // Offset64Hi 570 FALSE // Writeable 571 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10 572 573 { 574 4, // Width32 575 4, // Width64 576 SMM_CPU_OFFSET (x86._ES), // Offset32 577 SMM_CPU_OFFSET (x64._ES), // Offset64Lo 578 0, // Offset64Hi 579 FALSE // Writeable 580 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20 581 582 { 583 4, // Width32 584 4, // Width64 585 SMM_CPU_OFFSET (x86._CS), // Offset32 586 SMM_CPU_OFFSET (x64._CS), // Offset64Lo 587 0, // Offset64Hi 588 FALSE // Writeable 589 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21 590 591 { 592 4, // Width32 593 4, // Width64 594 SMM_CPU_OFFSET (x86._SS), // Offset32 595 SMM_CPU_OFFSET (x64._SS), // Offset64Lo 596 0, // Offset64Hi 597 FALSE // Writeable 598 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22 599 600 { 601 4, // Width32 602 4, // Width64 603 SMM_CPU_OFFSET (x86._DS), // Offset32 604 SMM_CPU_OFFSET (x64._DS), // Offset64Lo 605 0, // Offset64Hi 606 FALSE // Writeable 607 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23 608 609 { 610 4, // Width32 611 4, // Width64 612 SMM_CPU_OFFSET (x86._FS), // Offset32 613 SMM_CPU_OFFSET (x64._FS), // Offset64Lo 614 0, // Offset64Hi 615 FALSE // Writeable 616 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24 617 618 { 619 4, // Width32 620 4, // Width64 621 SMM_CPU_OFFSET (x86._GS), // Offset32 622 SMM_CPU_OFFSET (x64._GS), // Offset64Lo 623 0, // Offset64Hi 624 FALSE // Writeable 625 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25 626 627 { 628 0, // Width32 629 4, // Width64 630 0, // Offset32 631 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo 632 0, // Offset64Hi 633 FALSE // Writeable 634 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26 635 636 { 637 4, // Width32 638 4, // Width64 639 SMM_CPU_OFFSET (x86._TR), // Offset32 640 SMM_CPU_OFFSET (x64._TR), // Offset64Lo 641 0, // Offset64Hi 642 FALSE // Writeable 643 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27 644 645 { 646 4, // Width32 647 8, // Width64 648 SMM_CPU_OFFSET (x86._DR7), // Offset32 649 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo 650 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi 651 FALSE // Writeable 652 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28 653 654 { 655 4, // Width32 656 8, // Width64 657 SMM_CPU_OFFSET (x86._DR6), // Offset32 658 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo 659 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi 660 FALSE // Writeable 661 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29 662 663 { 664 0, // Width32 665 8, // Width64 666 0, // Offset32 667 SMM_CPU_OFFSET (x64._R8), // Offset64Lo 668 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi 669 TRUE // Writeable 670 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30 671 672 { 673 0, // Width32 674 8, // Width64 675 0, // Offset32 676 SMM_CPU_OFFSET (x64._R9), // Offset64Lo 677 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi 678 TRUE // Writeable 679 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31 680 681 { 682 0, // Width32 683 8, // Width64 684 0, // Offset32 685 SMM_CPU_OFFSET (x64._R10), // Offset64Lo 686 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi 687 TRUE // Writeable 688 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32 689 690 { 691 0, // Width32 692 8, // Width64 693 0, // Offset32 694 SMM_CPU_OFFSET (x64._R11), // Offset64Lo 695 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi 696 TRUE // Writeable 697 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33 698 699 { 700 0, // Width32 701 8, // Width64 702 0, // Offset32 703 SMM_CPU_OFFSET (x64._R12), // Offset64Lo 704 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi 705 TRUE // Writeable 706 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34 707 708 { 709 0, // Width32 710 8, // Width64 711 0, // Offset32 712 SMM_CPU_OFFSET (x64._R13), // Offset64Lo 713 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi 714 TRUE // Writeable 715 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35 716 717 { 718 0, // Width32 719 8, // Width64 720 0, // Offset32 721 SMM_CPU_OFFSET (x64._R14), // Offset64Lo 722 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi 723 TRUE // Writeable 724 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36 725 726 { 727 0, // Width32 728 8, // Width64 729 0, // Offset32 730 SMM_CPU_OFFSET (x64._R15), // Offset64Lo 731 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi 732 TRUE // Writeable 733 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37 734 735 { 736 4, // Width32 737 8, // Width64 738 SMM_CPU_OFFSET (x86._EAX), // Offset32 739 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo 740 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi 741 TRUE // Writeable 742 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38 743 744 { 745 4, // Width32 746 8, // Width64 747 SMM_CPU_OFFSET (x86._EBX), // Offset32 748 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo 749 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi 750 TRUE // Writeable 751 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 752 753 { 754 4, // Width32 755 8, // Width64 756 SMM_CPU_OFFSET (x86._ECX), // Offset32 757 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo 758 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi 759 TRUE // Writeable 760 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40 761 762 { 763 4, // Width32 764 8, // Width64 765 SMM_CPU_OFFSET (x86._EDX), // Offset32 766 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo 767 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi 768 TRUE // Writeable 769 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41 770 771 { 772 4, // Width32 773 8, // Width64 774 SMM_CPU_OFFSET (x86._ESP), // Offset32 775 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo 776 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi 777 TRUE // Writeable 778 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42 779 780 { 781 4, // Width32 782 8, // Width64 783 SMM_CPU_OFFSET (x86._EBP), // Offset32 784 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo 785 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi 786 TRUE // Writeable 787 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43 788 789 { 790 4, // Width32 791 8, // Width64 792 SMM_CPU_OFFSET (x86._ESI), // Offset32 793 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo 794 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi 795 TRUE // Writeable 796 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44 797 798 { 799 4, // Width32 800 8, // Width64 801 SMM_CPU_OFFSET (x86._EDI), // Offset32 802 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo 803 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi 804 TRUE // Writeable 805 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45 806 807 { 808 4, // Width32 809 8, // Width64 810 SMM_CPU_OFFSET (x86._EIP), // Offset32 811 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo 812 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi 813 TRUE // Writeable 814 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46 815 816 { 817 4, // Width32 818 8, // Width64 819 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32 820 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo 821 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi 822 TRUE // Writeable 823 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51 824 825 { 826 4, // Width32 827 8, // Width64 828 SMM_CPU_OFFSET (x86._CR0), // Offset32 829 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo 830 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi 831 FALSE // Writeable 832 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52 833 834 { 835 4, // Width32 836 8, // Width64 837 SMM_CPU_OFFSET (x86._CR3), // Offset32 838 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo 839 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi 840 FALSE // Writeable 841 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53 842 843 { 844 0, // Width32 845 4, // Width64 846 0, // Offset32 847 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo 848 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi 849 FALSE // Writeable 850 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54 497 851 }; 498 852 … … 510 864 511 865 **/ 512 static UINTN 866 STATIC 867 UINTN 513 868 GetRegisterIndex ( 514 869 IN EFI_SMM_SAVE_STATE_REGISTER Register … … 518 873 UINTN Offset; 519 874 520 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) { 521 if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) { 875 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; 876 mSmmCpuRegisterRanges[Index].Length != 0; 877 Index++) { 878 if (Register >= mSmmCpuRegisterRanges[Index].Start && 879 Register <= mSmmCpuRegisterRanges[Index].End) { 522 880 return Register - mSmmCpuRegisterRanges[Index].Start + Offset; 523 881 } … … 530 888 Read a CPU Save State register on the target processor. 531 889 532 This function abstracts the differences that whether the CPU Save State register is in the 533 IA32 CPU Save State Map or X64 CPU Save State Map. 534 535 This function supports reading a CPU Save State register in SMBase relocation handler. 536 537 @param[in] CpuIndex Specifies the zero-based index of the CPU save state. 890 This function abstracts the differences that whether the CPU Save State 891 register is in the IA32 CPU Save State Map or X64 CPU Save State Map. 892 893 This function supports reading a CPU Save State register in SMBase relocation 894 handler. 895 896 @param[in] CpuIndex Specifies the zero-based index of the CPU save 897 state. 538 898 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. 539 @param[in] Width The number of bytes to read from the CPU save state. 540 @param[out] Buffer Upon return, this holds the CPU register value read from the save state. 899 @param[in] Width The number of bytes to read from the CPU save 900 state. 901 @param[out] Buffer Upon return, this holds the CPU register value 902 read from the save state. 541 903 542 904 @retval EFI_SUCCESS The register was read from Save State. 543 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor. 905 @retval EFI_NOT_FOUND The register is not defined for the Save State 906 of Processor. 544 907 @retval EFI_INVALID_PARAMTER This or Buffer is NULL. 545 908 546 909 **/ 547 static EFI_STATUS 910 STATIC 911 EFI_STATUS 548 912 ReadSaveStateRegisterByIndex ( 549 913 IN UINTN CpuIndex, … … 559 923 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { 560 924 // 561 // If 32-bit mode width is zero, then the specified register can not be accessed 925 // If 32-bit mode width is zero, then the specified register can not be 926 // accessed 562 927 // 563 928 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) { … … 566 931 567 932 // 568 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed 933 // If Width is bigger than the 32-bit mode width, then the specified 934 // register can not be accessed 569 935 // 570 936 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { … … 576 942 // 577 943 ASSERT(CpuSaveState != NULL); 578 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width); 944 CopyMem ( 945 Buffer, 946 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, 947 Width 948 ); 579 949 } else { 580 950 // 581 // If 64-bit mode width is zero, then the specified register can not be accessed 951 // If 64-bit mode width is zero, then the specified register can not be 952 // accessed 582 953 // 583 954 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) { … … 586 957 587 958 // 588 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed 959 // If Width is bigger than the 64-bit mode width, then the specified 960 // register can not be accessed 589 961 // 590 962 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { … … 595 967 // Write lower 32-bits of return buffer 596 968 // 597 CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width)); 969 CopyMem ( 970 Buffer, 971 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, 972 MIN (4, Width) 973 ); 598 974 if (Width >= 4) { 599 975 // 600 976 // Write upper 32-bits of return buffer 601 977 // 602 CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); 978 CopyMem ( 979 (UINT8 *)Buffer + 4, 980 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, 981 Width - 4 982 ); 603 983 } 604 984 } … … 621 1001 @retval EFI_SUCCESS The register was read from Save State. 622 1002 @retval EFI_INVALID_PARAMTER Buffer is NULL. 623 @retval EFI_UNSUPPORTED This function does not support reading Register.624 1003 @retval EFI_UNSUPPORTED This function does not support reading 1004 Register. 625 1005 **/ 626 1006 EFI_STATUS … … 675 1055 RegisterIndex = GetRegisterIndex (Register); 676 1056 if (RegisterIndex == 0) { 677 return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED; 1057 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? 1058 EFI_NOT_FOUND : 1059 EFI_UNSUPPORTED); 678 1060 } 679 1061 … … 695 1077 @retval EFI_SUCCESS The register was written to Save State. 696 1078 @retval EFI_INVALID_PARAMTER Buffer is NULL. 697 @retval EFI_UNSUPPORTED This function does not support writing Register. 1079 @retval EFI_UNSUPPORTED This function does not support writing 1080 Register. 698 1081 **/ 699 1082 EFI_STATUS … … 730 1113 RegisterIndex = GetRegisterIndex (Register); 731 1114 if (RegisterIndex == 0) { 732 return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED; 1115 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? 1116 EFI_NOT_FOUND : 1117 EFI_UNSUPPORTED); 733 1118 } 734 1119 … … 747 1132 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { 748 1133 // 749 // If 32-bit mode width is zero, then the specified register can not be accessed 1134 // If 32-bit mode width is zero, then the specified register can not be 1135 // accessed 750 1136 // 751 1137 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) { … … 754 1140 755 1141 // 756 // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed 1142 // If Width is bigger than the 32-bit mode width, then the specified 1143 // register can not be accessed 757 1144 // 758 1145 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { … … 763 1150 // 764 1151 ASSERT (CpuSaveState != NULL); 765 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); 1152 CopyMem ( 1153 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, 1154 Buffer, 1155 Width 1156 ); 766 1157 } else { 767 1158 // 768 // If 64-bit mode width is zero, then the specified register can not be accessed 1159 // If 64-bit mode width is zero, then the specified register can not be 1160 // accessed 769 1161 // 770 1162 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) { … … 773 1165 774 1166 // 775 // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed 1167 // If Width is bigger than the 64-bit mode width, then the specified 1168 // register can not be accessed 776 1169 // 777 1170 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { … … 782 1175 // Write lower 32-bits of SMM State register 783 1176 // 784 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width)); 1177 CopyMem ( 1178 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, 1179 Buffer, 1180 MIN (4, Width) 1181 ); 785 1182 if (Width >= 4) { 786 1183 // 787 1184 // Write upper 32-bits of SMM State register 788 1185 // 789 CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); 1186 CopyMem ( 1187 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, 1188 (UINT8 *)Buffer + 4, 1189 Width - 4 1190 ); 790 1191 } 791 1192 } … … 806 1207 807 1208 /** 808 This API provides a method for a CPU to allocate a specific region for storing page tables. 1209 This API provides a method for a CPU to allocate a specific region for 1210 storing page tables. 809 1211 810 1212 This API can be called more once to allocate memory for page tables. 811 1213 812 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the 813 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL 814 is returned. If there is not enough memory remaining to satisfy the request, then NULL is 815 returned. 816 817 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM. 1214 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns 1215 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB 1216 boundary. If Pages is 0, then NULL is returned. If there is not enough 1217 memory remaining to satisfy the request, then NULL is returned. 1218 1219 This function can also return NULL if there is no preference on where the 1220 page tables are allocated in SMRAM. 818 1221 819 1222 @param Pages The number of 4 KB pages to allocate. … … 821 1224 @return A pointer to the allocated buffer for page tables. 822 1225 @retval NULL Fail to allocate a specific region for storing page tables, 823 Or there is no preference on where the page tables are allocated in SMRAM. 1226 Or there is no preference on where the page tables are 1227 allocated in SMRAM. 824 1228 825 1229 **/ -
trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
r77662 r80721 3 3 # 4 4 # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR> 5 # This program and the accompanying materials6 # are licensed and made available under the terms and conditions of the BSD License7 # which accompanies this distribution. The full text of the license may be found at8 # http://opensource.org/licenses/bsd-license.php9 5 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 6 # SPDX-License-Identifier: BSD-2-Clause-Patent 12 7 # 13 8 ## … … 34 29 BaseLib 35 30 BaseMemoryLib 36 PcdLib37 31 DebugLib 32 MemEncryptSevLib 38 33 SmmServicesTableLib 34 UefiBootServicesTableLib
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