Index: /trunk/include/VBox/vmm/iom.h
===================================================================
--- /trunk/include/VBox/vmm/iom.h	(revision 80959)
+++ /trunk/include/VBox/vmm/iom.h	(revision 80960)
@@ -243,4 +243,78 @@
 typedef FNIOMIOPORTOUTSTRING *PFNIOMIOPORTOUTSTRING;
 
+
+/**
+ * Port I/O Handler for IN operations.
+ *
+ * @returns VINF_SUCCESS or VINF_EM_*.
+ * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
+ *
+ * @param   pDevIns     The device instance.
+ * @param   pvUser      User argument.
+ * @param   uPort       Port number used for the IN operation.
+ * @param   pu32        Where to store the result.  This is always a 32-bit
+ *                      variable regardless of what @a cb might say.
+ * @param   cb          Number of bytes read.
+ * @remarks Caller enters the device critical section.
+ */
+typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWIN(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb);
+/** Pointer to a FNIOMIOPORTNEWIN(). */
+typedef FNIOMIOPORTNEWIN *PFNIOMIOPORTNEWIN;
+
+/**
+ * Port I/O Handler for string IN operations.
+ *
+ * @returns VINF_SUCCESS or VINF_EM_*.
+ * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
+ *
+ * @param   pDevIns     The device instance.
+ * @param   pvUser      User argument.
+ * @param   uPort       Port number used for the IN operation.
+ * @param   pbDst       Pointer to the destination buffer.
+ * @param   pcTransfers Pointer to the number of transfer units to read, on
+ *                      return remaining transfer units.
+ * @param   cb          Size of the transfer unit (1, 2 or 4 bytes).
+ * @remarks Caller enters the device critical section.
+ */
+typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWINSTRING(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint8_t *pbDst,
+                                                          uint32_t *pcTransfers, unsigned cb);
+/** Pointer to a FNIOMIOPORTNEWINSTRING(). */
+typedef FNIOMIOPORTNEWINSTRING *PFNIOMIOPORTNEWINSTRING;
+
+/**
+ * Port I/O Handler for OUT operations.
+ *
+ * @returns VINF_SUCCESS or VINF_EM_*.
+ *
+ * @param   pDevIns     The device instance.
+ * @param   pvUser      User argument.
+ * @param   uPort       Port number used for the OUT operation.
+ * @param   u32         The value to output.
+ * @param   cb          The value size in bytes.
+ * @remarks Caller enters the device critical section.
+ */
+typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWOUT(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb);
+/** Pointer to a FNIOMIOPORTNEWOUT(). */
+typedef FNIOMIOPORTNEWOUT *PFNIOMIOPORTNEWOUT;
+
+/**
+ * Port I/O Handler for string OUT operations.
+ *
+ * @returns VINF_SUCCESS or VINF_EM_*.
+ *
+ * @param   pDevIns     The device instance.
+ * @param   pvUser      User argument.
+ * @param   uPort       Port number used for the OUT operation.
+ * @param   pbSrc       Pointer to the source buffer.
+ * @param   pcTransfers Pointer to the number of transfer units to write, on
+ *                      return remaining transfer units.
+ * @param   cb          Size of the transfer unit (1, 2 or 4 bytes).
+ * @remarks Caller enters the device critical section.
+ */
+typedef DECLCALLBACK(VBOXSTRICTRC) FNIOMIOPORTNEWOUTSTRING(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, const uint8_t *pbSrc,
+                                                           uint32_t *pcTransfers, unsigned cb);
+/** Pointer to a FNIOMIOPORTNEWOUTSTRING(). */
+typedef FNIOMIOPORTNEWOUTSTRING *PFNIOMIOPORTNEWOUTSTRING;
+
 /**
  * I/O port description.
@@ -338,6 +412,6 @@
 
 VMMR3_INT_DECL(int)  IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
-                                       uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                       PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
+                                       uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
                                        const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
 VMMR3_INT_DECL(int)  IOMR3IoPortMap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
@@ -409,6 +483,6 @@
 VMMR0_INT_DECL(void) IOMR0CleanupVM(PGVM pGVM);
 VMMR0_INT_DECL(int)  IOMR0IoPortSetUpContext(PGVM pGVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                             PFNIOMIOPORTOUT pfnOut,  PFNIOMIOPORTIN pfnIn,
-                                             PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser);
+                                             PFNIOMIOPORTNEWOUT pfnOut,  PFNIOMIOPORTNEWIN pfnIn,
+                                             PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser);
 VMMR0_INT_DECL(int)  IOMR0IoPortGrowRegistrationTables(PGVM pGVM, uint64_t cMinEntries);
 VMMR0_INT_DECL(int)  IOMR0IoPortGrowStatisticsTable(PGVM pGVM, uint64_t cMinEntries);
Index: /trunk/include/VBox/vmm/pdmdev.h
===================================================================
--- /trunk/include/VBox/vmm/pdmdev.h	(revision 80959)
+++ /trunk/include/VBox/vmm/pdmdev.h	(revision 80960)
@@ -1058,4 +1058,13 @@
     DECLRCCALLBACKMEMBER(void,  pfnUnlock,(PPDMDEVINS pDevIns));
 
+    /**
+     * Gets a bus by it's PDM ordinal (typically the parent bus).
+     *
+     * @returns Pointer to the device instance of the bus.
+     * @param   pDevIns         The PCI bus device instance.
+     * @param   idxPdmBus       The PDM ordinal value of the bus to get.
+     */
+    DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
+
     /** Just a safety precaution. */
     uint32_t                    u32TheEnd;
@@ -1111,5 +1120,4 @@
     DECLR0CALLBACKMEMBER(void,  pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));
 
-
     /**
      * Acquires the PDM lock.
@@ -1128,4 +1136,13 @@
      */
     DECLR0CALLBACKMEMBER(void,  pfnUnlock,(PPDMDEVINS pDevIns));
+
+    /**
+     * Gets a bus by it's PDM ordinal (typically the parent bus).
+     *
+     * @returns Pointer to the device instance of the bus.
+     * @param   pDevIns         The PCI bus device instance.
+     * @param   idxPdmBus       The PDM ordinal value of the bus to get.
+     */
+    DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
 
     /** Just a safety precaution. */
@@ -1138,5 +1155,5 @@
 
 /** Current PDMPCIHLPR0 version number. */
-#define PDM_PCIHLPR0_VERSION                    PDM_VERSION_MAKE(0xfffc, 3, 0)
+#define PDM_PCIHLPR0_VERSION                    PDM_VERSION_MAKE(0xfffc, 4, 0)
 
 /**
@@ -1190,28 +1207,4 @@
 
     /**
-     * Gets the address of the RC PCI Bus helpers.
-     *
-     * This should be called at both construction and relocation time
-     * to obtain the correct address of the RC helpers.
-     *
-     * @returns RC pointer to the PCI Bus helpers.
-     * @param   pDevIns         Device instance of the PCI Bus.
-     * @thread  EMT only.
-     */
-    DECLR3CALLBACKMEMBER(PCPDMPCIHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
-
-    /**
-     * Gets the address of the R0 PCI Bus helpers.
-     *
-     * This should be called at both construction and relocation time
-     * to obtain the correct address of the R0 helpers.
-     *
-     * @returns R0 pointer to the PCI Bus helpers.
-     * @param   pDevIns         Device instance of the PCI Bus.
-     * @thread  EMT only.
-     */
-    DECLR3CALLBACKMEMBER(PCPDMPCIHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
-
-    /**
      * Acquires the PDM lock.
      *
@@ -1229,4 +1222,13 @@
      */
     DECLR3CALLBACKMEMBER(void,  pfnUnlock,(PPDMDEVINS pDevIns));
+
+    /**
+     * Gets a bus by it's PDM ordinal (typically the parent bus).
+     *
+     * @returns Pointer to the device instance of the bus.
+     * @param   pDevIns         The PCI bus device instance.
+     * @param   idxPdmBus       The PDM ordinal value of the bus to get.
+     */
+    DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
 
     /** Just a safety precaution. */
@@ -1239,5 +1241,5 @@
 
 /** Current PDMPCIHLPR3 version number. */
-#define PDM_PCIHLPR3_VERSION                    PDM_VERSION_MAKE(0xfffb, 3, 1)
+#define PDM_PCIHLPR3_VERSION                    PDM_VERSION_MAKE(0xfffb, 4, 0)
 
 
@@ -2297,6 +2299,6 @@
      */
     DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
-                                                 uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                                 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
+                                                 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                                 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
                                                  const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
 
@@ -4410,6 +4412,6 @@
      */
     DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                                       PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                                       PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr,
+                                                       PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
                                                        void *pvUser));
 
@@ -4766,6 +4768,6 @@
      */
     DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                                       PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                                       PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr,
+                                                       PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
                                                        void *pvUser));
 
@@ -5532,6 +5534,6 @@
  * Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
  */
-DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTOUT pfnOut,
-                                            PFNIOMIOPORTIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
+DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
+                                            PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
                                             PIOMIOPORTHANDLE phIoPorts)
 {
@@ -5547,5 +5549,5 @@
  */
 DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
-                                      PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn, void *pvUser, const char *pszDesc,
+                                      PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser, const char *pszDesc,
                                       PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
 {
@@ -5558,6 +5560,6 @@
  */
 DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
-                                        uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                        PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser,
+                                        uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                        PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
                                         const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
 {
@@ -5589,5 +5591,5 @@
  */
 DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                            PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn, void *pvUser)
+                                            PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
 {
     return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
@@ -5598,6 +5600,6 @@
  */
 DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                              PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                              PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser)
+                                              PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                              PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
 {
     return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
Index: /trunk/include/VBox/vmm/pdmpcidevint.h
===================================================================
--- /trunk/include/VBox/vmm/pdmpcidevint.h	(revision 80959)
+++ /trunk/include/VBox/vmm/pdmpcidevint.h	(revision 80960)
@@ -178,13 +178,6 @@
     R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
 
-    /** Pointer to the PCI bus of the device. (R0 ptr)
-     * @note Only used by ich9pcibridgeSetIrq to find the host (root) bus. */
-    R0PTRTYPE(struct DEVPCIBUS *)   pBusR0;
     /** Page used for MSI-X state.            (R0 ptr) */
     R0PTRTYPE(void *)               pMsixPageR0;
-
-    /** Pointer to the PCI bus of the device. (RC ptr)
-     * @note Only used by ich9pcibridgeSetIrq to find the host (root) bus. */
-    RCPTRTYPE(struct DEVPCIBUS *)   pBusRC;
     /** Page used for MSI-X state.            (RC ptr) */
     RCPTRTYPE(void *)               pMsixPageRC;
@@ -211,8 +204,6 @@
     /** Offset to the PBA for MSI-X.   */
     uint16_t                        offMsixPba;
-#if HC_ARCH_BITS == 32
-    /** Add padding to align aIORegions to an 8 byte boundary. */
-    uint8_t                         abPadding2[12];
-#endif
+    /** Add padding to align aIORegions to an 16 byte boundary. */
+    uint8_t                         abPadding2[HC_ARCH_BITS == 32 ? 4+8 : 4+8];
 
     /** Pointer to bus specific data. (R3 ptr) */
Index: /trunk/src/VBox/Devices/Bus/DevPCI.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevPCI.cpp	(revision 80959)
+++ /trunk/src/VBox/Devices/Bus/DevPCI.cpp	(revision 80960)
@@ -85,8 +85,4 @@
 
 static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
-PDMBOTHCBDECL(int)  pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
-PDMBOTHCBDECL(int)  pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
-PDMBOTHCBDECL(int)  pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
-PDMBOTHCBDECL(int)  pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
 
 #ifdef IN_RING3
@@ -290,5 +286,5 @@
  * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
  *
- * @param   pPdmDev         The PDM device instance for the PCI bus.
+ * @param   pDevIns         The PDM device instance for the PCI bus.
  * @param   pGlobals        Device instance of the host PCI bus.
  * @param   pBusCC          Context specific data for the PCI bus.
@@ -807,7 +803,7 @@
 
 /**
- * @callback_method_impl{FNIOMIOPORTOUT, PCI address}
- */
-PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
+ * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
 {
     LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
@@ -827,7 +823,7 @@
 
 /**
- * @callback_method_impl{FNIOMIOPORTIN, PCI address}
- */
-PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
+ * @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
 {
     RT_NOREF2(Port, pvUser);
@@ -849,7 +845,7 @@
 
 /**
- * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
- */
-PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
+ * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
 {
     LogFunc(("Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
@@ -864,12 +860,12 @@
     else
         AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
-    return VBOXSTRICTRC_TODO(rcStrict);
-}
-
-
-/**
- * @callback_method_impl{FNIOMIOPORTIN, PCI data}
- */
-PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
+    return rcStrict;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
+ */
+static DECLCALLBACK(VBOXSTRICTRC) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
 {
     NOREF(pvUser);
@@ -880,5 +876,5 @@
         PCI_UNLOCK(pDevIns);
         LogFunc(("Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
-        return VBOXSTRICTRC_TODO(rcStrict);
+        return rcStrict;
     }
     AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
@@ -889,7 +885,8 @@
 
 /**
- * @callback_method_impl{FNIOMIOPORTOUT, PCI data}
- */
-DECLCALLBACK(int) pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
+ * @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
 {
     RT_NOREF2(pvUser, Port);
@@ -908,7 +905,8 @@
 
 /**
- * @callback_method_impl{FNIOMIOPORTIN, PCI data}
- */
-DECLCALLBACK(int) pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
+ * @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
 {
     RT_NOREF5(pDevIns, pvUser, Port, pu32, cb);
@@ -1269,6 +1267,5 @@
      * Validate and read configuration.
      */
-    if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
-        return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
+    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
 
     /* query whether we got an IOAPIC */
@@ -1279,25 +1276,12 @@
                                 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
 
-    /* check if RC code is enabled. */
-    bool fGCEnabled;
-    rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
-
-    /* check if R0 code is enabled. */
-    bool fR0Enabled;
-    rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
-    Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
-
+    Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic,  pDevIns->fR0Enabled, pDevIns->fRCEnabled));
+
+    /*
+     * Init data and register the PCI bus.
+     */
     PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
 
-    /*
-     * Init data and register the PCI bus.
-     */
     pGlobals->uPciBiosIo   = 0xc000;
     pGlobals->uPciBiosMmio = 0xf0000000;
@@ -1368,32 +1352,18 @@
      * Register I/O ports and save state.
      */
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
-    if (RT_FAILURE(rc))
-        return rc;
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
-    if (RT_FAILURE(rc))
-        return rc;
-    if (fGCEnabled)
-    {
-        rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-        rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-    }
-    if (fR0Enabled)
-    {
-        rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-        rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-    }
-
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead, NULL, NULL, "i440FX (Fake PCI BIOS trigger)");
-    if (RT_FAILURE(rc))
-        return rc;
+    static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
+    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
+                                     &pGlobals->hIoPortAddress);
+    AssertLogRelRCReturn(rc, rc);
+
+    static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
+    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
+                                     &pGlobals->hIoPortData);
+    AssertLogRelRCReturn(rc, rc);
+
+    static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
+    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
+                                     "i440FX (Fake PCI BIOS trigger)", s_aMagicDesc,  &pGlobals->hIoPortMagic);
+    AssertLogRelRCReturn(rc, rc);
 
 
@@ -1402,6 +1372,5 @@
                                 NULL, pciR3SaveExec, NULL,
                                 NULL, pciR3LoadExec, NULL);
-    if (RT_FAILURE(rc))
-        return rc;
+    AssertLogRelRCReturn(rc, rc);
 
     PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
@@ -1426,4 +1395,9 @@
     PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
 
+    /* Mirror the ring-3 device lock disabling: */
+    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    AssertRCReturn(rc, rc);
+
+    /* Set up the RZ PCI bus callbacks: */
     PDMPCIBUSREGCC PciBusReg;
     PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
@@ -1431,6 +1405,13 @@
     PciBusReg.pfnSetIrq     = pciSetIrq;
     PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
-    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
-    AssertRC(rc);
+    rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
+    AssertRCReturn(rc, rc);
+
+    /* Set up I/O port callbacks, except for the magic port: */
+    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
+    AssertLogRelRCReturn(rc, rc);
+
+    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
+    AssertLogRelRCReturn(rc, rc);
 
     return rc;
@@ -1447,5 +1428,5 @@
     /* .uReserved0 = */             0,
     /* .szName = */                 "pci",
-    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
+    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
     /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
     /* .cMaxInstances = */          1,
@@ -1531,4 +1512,36 @@
      * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
      */
+#if 1
+    PDEVPCIBUSCC const  pBridgeBusCC  = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC); /* For keep using our own pcihlp.  */
+    PPDMDEVINS const    pBridgeDevIns = pDevIns;                                 /* ditto */
+
+    PDEVPCIBUS          pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PPDMDEVINS          pDevInsBus;
+    PPDMPCIDEV          pPciDevBus    = &pBus->PciDev;
+    uint8_t             uDevFnBridge  = pPciDevBus->uDevFn;
+    int                 iIrqPinBridge = ((pPciDev->uDevFn >> 3) + iIrq) & 3;
+
+    /* Walk the chain until we reach the host bus. */
+    Assert(pBus->iBus != 0);
+    for (;;)
+    {
+        /* Get the parent. */
+        pDevInsBus = pBridgeBusCC->CTX_SUFF(pPciHlp)->pfnGetBusByNo(pBridgeDevIns, pPciDevBus->Int.s.idxPdmBus);
+        AssertLogRelReturnVoid(pDevInsBus);
+
+        pBus       = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
+        pPciDevBus = &pBus->PciDev;
+        if (pBus->iBus == 0)
+            break;
+
+        uDevFnBridge  = pPciDevBus->uDevFn;
+        iIrqPinBridge = ((uDevFnBridge >> 3) + iIrqPinBridge) & 3;
+    }
+
+    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
+    Assert(pDevInsBus->pReg == &g_DevicePCI);
+    pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
+                      uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
+#else  /* (old code for reference) */
     PDEVPCIBUS   pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     PDEVPCIBUSCC pBusCC        = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
@@ -1550,4 +1563,5 @@
     AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
     pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), pBusCC, uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
+#endif
 }
 
@@ -1830,5 +1844,5 @@
     /* .uReserved0 = */             0,
     /* .szName = */                 "pcibridge",
-    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
+    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
     /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI,
     /* .cMaxInstances = */          ~0U,
Index: /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 80959)
+++ /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 80960)
@@ -122,5 +122,5 @@
 }
 
-PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
+static void ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
 {
     LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
@@ -129,5 +129,5 @@
 }
 
-PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
+static void ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
 {
     /*
@@ -138,4 +138,45 @@
      * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
      */
+#if 1
+    PDEVPCIBUSCC const  pBridgeBusCC  = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC); /* For keep using our own pcihlp.  */
+    PPDMDEVINS const    pBridgeDevIns = pDevIns;                                 /* ditto */
+
+    PDEVPCIBUS          pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+    PPDMDEVINS          pDevInsBus;
+    PPDMPCIDEV          pPciDevBus    = &pBus->PciDev;
+    uint8_t             uDevFnBridge  = pPciDevBus->uDevFn;
+    int                 iIrqPinBridge = ((pPciDev->uDevFn >> 3) + iIrq) & 3;
+
+    /* Walk the chain until we reach the host bus. */
+    Assert(pBus->iBus != 0);
+    for (;;)
+    {
+        /* Get the parent. */
+        pDevInsBus = pBridgeBusCC->CTX_SUFF(pPciHlp)->pfnGetBusByNo(pBridgeDevIns, pPciDevBus->Int.s.idxPdmBus);
+        AssertLogRelReturnVoid(pDevInsBus);
+
+        pBus       = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
+        pPciDevBus = &pBus->PciDev;
+        if (pBus->iBus == 0)
+            break;
+
+        uDevFnBridge  = pPciDevBus->uDevFn;
+        iIrqPinBridge = ((uDevFnBridge >> 3) + iIrqPinBridge) & 3;
+    }
+
+    AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
+    Assert(pDevInsBus->pReg == &g_DevicePciIch9);
+
+    /*
+     * For MSI/MSI-X enabled devices the iIrq doesn't denote the pin but rather a vector which is completely
+     * orthogonal to the pin based approach. The vector is not subject to the pin based routing with PCI bridges.
+     */
+    int iIrqPinVector = iIrqPinBridge;
+    if (   MsiIsEnabled(pPciDev)
+        || MsixIsEnabled(pPciDev))
+        iIrqPinVector = iIrq;
+    ich9pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
+                          uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
+#else  /* (old code for reference) */
     PDEVPCIBUS     pBus          = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
     PPDMPCIDEV     pPciDevBus    = pPciDev;
@@ -166,4 +207,5 @@
     ich9pciSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
                           uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
+#endif
 }
 
@@ -182,5 +224,6 @@
  * @param   cb          The value size in bytes.
  */
-DECLCALLBACK(int) ich9pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
+static DECLCALLBACK(VBOXSTRICTRC)
+ich9pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
 {
     RT_NOREF2(pvUser, uPort);
@@ -210,5 +253,6 @@
  * @param   cb          Number of bytes read.
  */
-DECLCALLBACK(int) ich9pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
+static DECLCALLBACK(VBOXSTRICTRC)
+ich9pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
 {
     RT_NOREF5(pDevIns, pvUser, uPort, pu32, cb);
@@ -234,5 +278,6 @@
  * @param   cb          The value size in bytes.
  */
-PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
+static DECLCALLBACK(VBOXSTRICTRC)
+ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
 {
     LogFlowFunc(("Port=%#x u32=%#x cb=%d\n", uPort, u32, cb));
@@ -258,18 +303,12 @@
 
 /**
- * Port I/O Handler for PCI address IN operations.
+ * @callback_method_impl{FNIOMIOPORTNEWIN,
+ *                       Port I/O Handler for PCI data IN operations.
  *
- * Emulates reads from Configuration Address Port at 0CF8h for
- * Configuration Mechanism #1.
- *
- * @returns VBox status code.
- *
- * @param   pDevIns     ICH9 device instance.
- * @param   pvUser      User argument - ignored.
- * @param   uPort       Port number used for the IN operation.
- * @param   pu32        Where to store the result.
- * @param   cb          Number of bytes read.
- */
-PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
+ * Emulates reads from Configuration Address Port at 0CF8h for Configuration
+ * Mechanism \#1.
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
 {
     RT_NOREF2(uPort, pvUser);
@@ -291,5 +330,5 @@
 
 
-/*
+/**
  * Perform configuration space write.
  */
@@ -344,22 +383,17 @@
 
 /**
- * Port I/O Handler for PCI data OUT operations.
+ * @callback_method_impl{FNIOMIOPORTNEWOUT,
+ *                       Port I/O Handler for PCI data OUT operations.
  *
- * Emulates writes to Configuration Data Port at 0CFCh for
- * Configuration Mechanism #1.
- *
- * @returns VBox status code.
- *
- * @param   pDevIns     ICH9 device instance.
- * @param   pvUser      User argument - ignored.
- * @param   uPort       Port number used for the OUT operation.
- * @param   u32         The value to output.
- * @param   cb          The value size in bytes.
- */
-PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
+ * Emulates writes to Configuration Data Port at 0CFCh for Configuration
+ * Mechanism \#1.
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
 {
     PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     LogFlowFunc(("Port=%#x u32=%#x cb=%d (config=%#10x)\n", uPort, u32, cb, pThis->uConfigReg));
     NOREF(pvUser);
+
     VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     if (!(uPort % cb))
@@ -367,9 +401,6 @@
         PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
 
-        do /* do-brain-dead-while-false-utter-stupidity-loop */
-        {
-            /* Configuration space mapping enabled? */
-            if (!(pThis->uConfigReg & (1 << 31)))
-                break;
+        if (pThis->uConfigReg & (1 << 31))
+        {
 
             /* Decode target device from Configuration Address Port */
@@ -379,5 +410,5 @@
             /* Perform configuration space write */
             rcStrict = ich9pciConfigWrite(pDevIns, pThis, &aPciAddr, u32, cb, VINF_IOM_R3_IOPORT_WRITE);
-        } while (0);
+        }
 
         PCI_UNLOCK(pDevIns);
@@ -385,9 +416,10 @@
     else
         AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", uPort, u32, cb));
-    return VBOXSTRICTRC_TODO(rcStrict);
-}
-
-
-/*
+
+    return rcStrict;
+}
+
+
+/**
  * Perform configuration space read.
  */
@@ -449,18 +481,12 @@
 
 /**
- * Port I/O Handler for PCI data IN operations.
+ * @callback_method_impl{FNIOMIOPORTNEWIN,
+ *                       Port I/O Handler for PCI data IN operations.
  *
- * Emulates reads from Configuration Data Port at 0CFCh for
- * Configuration Mechanism #1.
- *
- * @returns VBox status code.
- *
- * @param   pDevIns     ICH9 device instance.
- * @param   pvUser      User argument - ignored.
- * @param   uPort       Port number used for the IN operation.
- * @param   pu32        Where to store the result.
- * @param   cb          Number of bytes read.
- */
-PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
+ * Emulates reads from Configuration Data Port at 0CFCh for Configuration
+ * Mechanism \#1.
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
 {
     NOREF(pvUser);
@@ -489,5 +515,5 @@
 
         LogFlowFunc(("Port=%#x cb=%#x (config=%#10x) -> %#x (%Rrc)\n", uPort, cb, *pu32, pThis->uConfigReg, VBOXSTRICTRC_VAL(rcStrict)));
-        return VBOXSTRICTRC_TODO(rcStrict);
+        return rcStrict;
     }
     AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", uPort, cb));
@@ -3027,64 +3053,35 @@
     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
 
+    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
+    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIBUS   pBus     = &pPciRoot->PciBus;
+    Assert(ASMMemIsZero(pPciRoot, sizeof(*pPciRoot))); /* code used to memset it for some funny reason. just temp insurance. */
+
     /*
      * Validate and read configuration.
      */
-    if (!CFGMR3AreValuesValid(pCfg,
-                              "IOAPIC\0"
-                              "GCEnabled\0"
-                              "R0Enabled\0"
-                              "McfgBase\0"
-                              "McfgLength\0"
-                              ))
-        return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
+    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC|McfgBase|McfgLength", "");
 
     /* query whether we got an IOAPIC */
-    bool fUseIoApic;
-    int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
-
-    /* check if RC code is enabled. */
-    bool fGCEnabled;
-    rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
-    /* check if R0 code is enabled. */
-    bool fR0Enabled;
-    rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
-
-    Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
+    int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pPciRoot->fUseIoApic, false /** @todo default to true? */);
+    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"IOAPIC\"")));
+
+    if (!pPciRoot->fUseIoApic)
+        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Must use IO-APIC with ICH9 chipset"));
+
+    rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pPciRoot->u64PciConfigMMioAddress, 0);
+    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\"")));
+
+    rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pPciRoot->u64PciConfigMMioLength, 0);
+    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\"")));
+
+    Log(("PCI: fUseIoApic=%RTbool McfgBase=%#RX64 McfgLength=%#RX64 fR0Enabled=%RTbool fRCEnabled=%RTbool\n", pPciRoot->fUseIoApic,
+         pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
 
     /*
      * Init data.
      */
-    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
-    PDEVPCIBUS   pBus     = &pPciRoot->PciBus;
-    PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
-
-    /* Zero out everything */
-    Assert(ASMMemIsZero(pPciRoot, sizeof(*pPciRoot)));
-    memset(pPciRoot, 0, sizeof(*pPciRoot)); /** @todo unnecessary as instance data is always set to zero by the allocator, see assertion above. */
-
     /* And fill values */
-    if (!fUseIoApic)
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Must use IO-APIC with ICH9 chipset"));
-    rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pPciRoot->u64PciConfigMMioAddress, 0);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to read \"McfgBase\""));
-    rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pPciRoot->u64PciConfigMMioLength, 0);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to read \"McfgLength\""));
-
     pBusCC->pDevInsR3             = pDevIns;
-    pPciRoot->fUseIoApic          = fUseIoApic;
     pPciRoot->PciBus.fTypePiix3   = false;
     pPciRoot->PciBus.fTypeIch9    = true;
@@ -3092,4 +3089,10 @@
     pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pPciRoot->PciBus.apDevices));
     AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
+
+    /*
+     * Disable default device locking.
+     */
+    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    AssertRCReturn(rc, rc);
 
     /*
@@ -3140,37 +3143,27 @@
 
     /*
-     * Register I/O ports and save state.
+     * Register I/O ports.
      */
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
-    if (RT_FAILURE(rc))
-        return rc;
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
-    if (RT_FAILURE(rc))
-        return rc;
-    if (fGCEnabled)
-    {
-        rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-        rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-    }
-    if (fR0Enabled)
-    {
-        rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-        rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
-        if (RT_FAILURE(rc))
-            return rc;
-    }
-
-    rc = PDMDevHlpIOPortRegister(pDevIns, 0x0410, 1, NULL, ich9pciR3IOPortMagicPCIWrite, ich9pciR3IOPortMagicPCIRead, NULL, NULL, "ICH9 (Fake PCI BIOS trigger)");
-    if (RT_FAILURE(rc))
-        return rc;
-
+    static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
+    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead,
+                                     "ICH9 (PCI)", s_aAddrDesc, &pPciRoot->hIoPortAddress);
+    AssertLogRelRCReturn(rc, rc);
+
+    static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
+    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, ich9pciIOPortDataWrite, ich9pciIOPortDataRead,
+                                     "ICH9 (PCI)", s_aDataDesc, &pPciRoot->hIoPortData);
+    AssertLogRelRCReturn(rc, rc);
+
+    static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
+    rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, ich9pciR3IOPortMagicPCIWrite, ich9pciR3IOPortMagicPCIRead,
+                                     "ICH9 (Fake PCI BIOS trigger)", s_aMagicDesc, &pPciRoot->hIoPortMagic);
+    AssertLogRelRCReturn(rc, rc);
+
+    /*
+     * MMIO handlers.
+     */
     if (pPciRoot->u64PciConfigMMioAddress != 0)
     {
+/** @todo implement new-style MMIO   */
         rc = PDMDevHlpMMIORegister(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, NULL /*pvUser*/,
                                    IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
@@ -3178,5 +3171,5 @@
         AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc,  pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
 
-        if (fGCEnabled)
+        if (pDevIns->fRCEnabled)
         {
             rc = PDMDevHlpMMIORegisterRC(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
@@ -3186,5 +3179,5 @@
 
 
-        if (fR0Enabled)
+        if (pDevIns->fR0Enabled)
         {
             rc = PDMDevHlpMMIORegisterR0(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
@@ -3194,4 +3187,7 @@
     }
 
+    /*
+     * Saved state and info handlers.
+     */
     rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION,
                                 sizeof(*pBus) + 16*128, "pgm",
@@ -3199,7 +3195,5 @@
                                 NULL, ich9pciR3SaveExec, NULL,
                                 NULL, ich9pciR3LoadExec, NULL);
-    if (RT_FAILURE(rc))
-        return rc;
-
+    AssertRCReturn(rc, rc);
 
     /** @todo other chipset devices shall be registered too */
@@ -3293,19 +3287,19 @@
     if (!RTStrCmp(pszExpressPortType, "EndPtDev"))
         return VBOX_PCI_EXP_TYPE_ENDPOINT;
-    else if (!RTStrCmp(pszExpressPortType, "LegEndPtDev"))
+    if (!RTStrCmp(pszExpressPortType, "LegEndPtDev"))
         return VBOX_PCI_EXP_TYPE_LEG_END;
-    else if (!RTStrCmp(pszExpressPortType, "RootCmplxRootPort"))
+    if (!RTStrCmp(pszExpressPortType, "RootCmplxRootPort"))
         return VBOX_PCI_EXP_TYPE_ROOT_PORT;
-    else if (!RTStrCmp(pszExpressPortType, "ExpressSwUpstream"))
+    if (!RTStrCmp(pszExpressPortType, "ExpressSwUpstream"))
         return VBOX_PCI_EXP_TYPE_UPSTREAM;
-    else if (!RTStrCmp(pszExpressPortType, "ExpressSwDownstream"))
+    if (!RTStrCmp(pszExpressPortType, "ExpressSwDownstream"))
         return VBOX_PCI_EXP_TYPE_DOWNSTREAM;
-    else if (!RTStrCmp(pszExpressPortType, "Express2PciBridge"))
+    if (!RTStrCmp(pszExpressPortType, "Express2PciBridge"))
         return VBOX_PCI_EXP_TYPE_PCI_BRIDGE;
-    else if (!RTStrCmp(pszExpressPortType, "Pci2ExpressBridge"))
+    if (!RTStrCmp(pszExpressPortType, "Pci2ExpressBridge"))
         return VBOX_PCI_EXP_TYPE_PCIE_BRIDGE;
-    else if (!RTStrCmp(pszExpressPortType, "RootCmplxIntEp"))
+    if (!RTStrCmp(pszExpressPortType, "RootCmplxIntEp"))
         return VBOX_PCI_EXP_TYPE_ROOT_INT_EP;
-    else if (!RTStrCmp(pszExpressPortType, "RootCmplxEc"))
+    if (!RTStrCmp(pszExpressPortType, "RootCmplxEc"))
         return VBOX_PCI_EXP_TYPE_ROOT_EC;
 
@@ -3371,5 +3365,4 @@
         if (pDev)
         {
-            pDev->Int.s.pBusRC += offDelta;
             if (pDev->Int.s.pMsixPageRC)
                 pDev->Int.s.pMsixPageRC += offDelta;
@@ -3402,4 +3395,5 @@
 }
 
+
 /**
  * @interface_method_impl{PDMDEVREG,pfnDestruct}
@@ -3427,46 +3421,27 @@
      * Validate and read configuration.
      */
-    if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0" "ExpressEnabled\0" "ExpressPortType\0"))
-        return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
-
-    /* check if RC code is enabled. */
-    bool fGCEnabled;
-    int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
-
-    /* check if R0 code is enabled. */
-    bool fR0Enabled;
-    rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
-    Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
+    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "ExpressEnabled|ExpressPortType", "");
 
     /* check if we're supposed to implement a PCIe bridge. */
     bool fExpress;
-    rc = CFGMR3QueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to query boolean value \"ExpressEnabled\""));
-
-    char *pszExpressPortType;
-    rc = CFGMR3QueryStringAllocDef(pCfg, "ExpressPortType",
-                                   &pszExpressPortType, "RootCmplxIntEp");
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("LsiLogic configuration error: failed to read \"ExpressPortType\" as string"));
-
-    uint8_t uExpressPortType = ich9pcibridgeR3GetExpressPortTypeFromString(pszExpressPortType);
-    MMR3HeapFree(pszExpressPortType);
-
-    pDevIns->IBase.pfnQueryInterface = ich9pcibridgeQueryInterface;
+    int rc = CFGMR3QueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
+    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ExpressEnabled\"")));
+
+    char szExpressPortType[80];
+    rc = CFGMR3QueryStringDef(pCfg, "ExpressPortType", szExpressPortType, sizeof(szExpressPortType), "RootCmplxIntEp");
+    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read \"ExpressPortType\" as string")));
+
+    uint8_t const uExpressPortType = ich9pcibridgeR3GetExpressPortTypeFromString(szExpressPortType);
+    Log(("PCI/bridge#%u: fR0Enabled=%RTbool fRCEnabled=%RTbool fExpress=%RTbool uExpressPortType=%u (%s)\n",
+         iInstance, pDevIns->fR0Enabled, pDevIns->fRCEnabled, fExpress, uExpressPortType, szExpressPortType));
 
     /*
      * Init data and register the PCI bus.
      */
+    pDevIns->IBase.pfnQueryInterface = ich9pcibridgeQueryInterface;
+
     PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
+
     pBus->fTypePiix3  = false;
     pBus->fTypeIch9   = true;
@@ -3474,5 +3449,6 @@
     pBusCC->pDevInsR3 = pDevIns;
     /** @todo r=klaus figure out how to extend this to allow PCIe config space
-     * extension, which increases the config space from 256 bytes to 4K. */
+     * extension, which increases the config space from 256 bytes to 4K.
+     * bird: What does this allocation have to do with PCIe config space?!?  */
     pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
     AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
@@ -3595,6 +3571,6 @@
     rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
                                 PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
-    if (RT_FAILURE(rc))
-        return rc;
+    AssertLogRelRCReturn(rc, rc);
+
     pBus->PciDev.Int.s.pfnBridgeConfigRead  = ich9pcibridgeConfigRead;
     pBus->PciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
@@ -3610,7 +3586,5 @@
                                 NULL, ich9pcibridgeR3SaveExec, NULL,
                                 NULL, ich9pcibridgeR3LoadExec, NULL);
-    if (RT_FAILURE(rc))
-        return rc;
-
+    AssertLogRelRCReturn(rc, rc);
 
     return VINF_SUCCESS;
@@ -3625,18 +3599,29 @@
 {
     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
-    PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
+    PDEVPCIROOT  pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
 
+    /* Mirror the ring-3 device lock disabling: */
+    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    AssertRCReturn(rc, rc);
+
+    /* Set up the RZ PCI bus callbacks: */
     PDMPCIBUSREGCC PciBusReg;
     PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
-    PciBusReg.iBus          = pGlobals->PciBus.iBus;
+    PciBusReg.iBus          = pPciRoot->PciBus.iBus;
     PciBusReg.pfnSetIrq     = ich9pciSetIrq;
     PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
-    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
-    AssertRC(rc);
-
-    /* Disable default device locking. */
-    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     AssertRCReturn(rc, rc);
+
+    /* Set up I/O port callbacks, except for the magic port: */
+    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pPciRoot->hIoPortAddress, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL);
+    AssertLogRelRCReturn(rc, rc);
+
+    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pPciRoot->hIoPortData, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL);
+    AssertLogRelRCReturn(rc, rc);
+
+    /* Set up MMIO callbacks: */
+    /** @todo new-style MMIO */
 
     return rc;
@@ -3653,4 +3638,9 @@
     PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
 
+    /* Mirror the ring-3 device lock disabling: */
+    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    AssertRCReturn(rc, rc);
+
+    /* Set up the RZ PCI bus callbacks: */
     PDMPCIBUSREGCC PciBusReg;
     PciBusReg.u32Version    = PDM_PCIBUSREGCC_VERSION;
@@ -3658,9 +3648,5 @@
     PciBusReg.pfnSetIrq     = ich9pcibridgeSetIrq;
     PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
-    int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
-    AssertRC(rc);
-
-    /* Disable default device locking. */
-    rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
+    rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
     AssertRCReturn(rc, rc);
 
@@ -3678,5 +3664,5 @@
     /* .uReserved0 = */             0,
     /* .szName = */                 "ich9pci",
-    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
+    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
     /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
     /* .cMaxInstances = */          1,
@@ -3752,5 +3738,5 @@
     /* .uReserved0 = */             0,
     /* .szName = */                 "ich9pcibridge",
-    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
+    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 | PDM_DEVREG_FLAGS_NEW_STYLE,
     /* .fClass = */                 PDM_DEVREG_CLASS_BUS_PCI,
     /* .cMaxInstances = */          ~0U,
Index: /trunk/src/VBox/Devices/Bus/DevPciInternal.h
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevPciInternal.h	(revision 80959)
+++ /trunk/src/VBox/Devices/Bus/DevPciInternal.h	(revision 80960)
@@ -169,4 +169,11 @@
     } Piix3;
 
+    /** The address I/O port handle. */
+    IOMIOPORTHANDLE         hIoPortAddress;
+    /** The data I/O port handle. */
+    IOMIOPORTHANDLE         hIoPortData;
+    /** The magic I/O port handle. */
+    IOMIOPORTHANDLE         hIoPortMagic;
+
 #if 1 /* Will be moved into the BIOS "soon". */
     /** Current bus number - obsolete (still used by DevPCI, but merge will fix that). */
Index: /trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h	(revision 80959)
+++ /trunk/src/VBox/Devices/Bus/DevPciMerge1.cpp.h	(revision 80960)
@@ -192,6 +192,4 @@
     pPciDev->Int.s.pBusR3           = pBus;
     Assert(pBus == PDMINS_2_DATA(pDevIns, PDEVPCIBUS));
-    pPciDev->Int.s.pBusR0           = PDMINS_2_DATA_R0PTR(pDevIns);
-    pPciDev->Int.s.pBusRC           = PDMINS_2_DATA_RCPTR(pDevIns);
     pPciDev->Int.s.pfnConfigRead    = NULL;
     pPciDev->Int.s.pfnConfigWrite   = NULL;
Index: /trunk/src/VBox/Devices/PC/DevRTC.cpp
===================================================================
--- /trunk/src/VBox/Devices/PC/DevRTC.cpp	(revision 80959)
+++ /trunk/src/VBox/Devices/PC/DevRTC.cpp	(revision 80960)
@@ -348,5 +348,5 @@
  * @callback_method_impl{FNIOMIOPORTIN}
  */
-PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
+PDMBOTHCBDECL(VBOXSTRICTRC) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
 {
     NOREF(pvUser);
@@ -406,5 +406,5 @@
  * @callback_method_impl{FNIOMIOPORTOUT}
  */
-PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
+PDMBOTHCBDECL(VBOXSTRICTRC) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
 {
     NOREF(pvUser);
Index: /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp	(revision 80959)
+++ /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp	(revision 80960)
@@ -104,6 +104,6 @@
          * Found an entry, get the data so we can leave the IOM lock.
          */
-        PFNIOMIOPORTIN pfnInCallback = pRegEntry->pfnInCallback;
-        PPDMDEVINS     pDevIns       = pRegEntry->pDevIns;
+        PFNIOMIOPORTNEWIN pfnInCallback = pRegEntry->pfnInCallback;
+        PPDMDEVINS        pDevIns       = pRegEntry->pDevIns;
 #ifndef IN_RING3
         if (   pfnInCallback
@@ -349,7 +349,7 @@
          * Found an entry, get the data so we can leave the IOM lock.
          */
-        PFNIOMIOPORTINSTRING pfnInStrCallback = pRegEntry->pfnInStrCallback;
-        PFNIOMIOPORTIN       pfnInCallback    = pRegEntry->pfnInCallback;
-        PPDMDEVINS           pDevIns          = pRegEntry->pDevIns;
+        PFNIOMIOPORTNEWINSTRING pfnInStrCallback = pRegEntry->pfnInStrCallback;
+        PFNIOMIOPORTNEWIN       pfnInCallback    = pRegEntry->pfnInCallback;
+        PPDMDEVINS              pDevIns          = pRegEntry->pDevIns;
 #ifndef IN_RING3
         if (   pfnInCallback
@@ -671,6 +671,6 @@
          * Found an entry, get the data so we can leave the IOM lock.
          */
-        PFNIOMIOPORTOUT pfnOutCallback   = pRegEntry->pfnOutCallback;
-        PPDMDEVINS      pDevIns          = pRegEntry->pDevIns;
+        PFNIOMIOPORTNEWOUT pfnOutCallback   = pRegEntry->pfnOutCallback;
+        PPDMDEVINS         pDevIns          = pRegEntry->pDevIns;
 #ifndef IN_RING3
         if (   pfnOutCallback
@@ -892,7 +892,7 @@
          * Found an entry, get the data so we can leave the IOM lock.
          */
-        PFNIOMIOPORTOUTSTRING   pfnOutStrCallback = pRegEntry->pfnOutStrCallback;
-        PFNIOMIOPORTOUT         pfnOutCallback    = pRegEntry->pfnOutCallback;
-        PPDMDEVINS              pDevIns           = pRegEntry->pDevIns;
+        PFNIOMIOPORTNEWOUTSTRING   pfnOutStrCallback = pRegEntry->pfnOutStrCallback;
+        PFNIOMIOPORTNEWOUT         pfnOutCallback    = pRegEntry->pfnOutCallback;
+        PPDMDEVINS                 pDevIns           = pRegEntry->pDevIns;
 #ifndef IN_RING3
         if (   pfnOutCallback
Index: /trunk/src/VBox/VMM/VMMR0/IOMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/IOMR0.cpp	(revision 80959)
+++ /trunk/src/VBox/VMM/VMMR0/IOMR0.cpp	(revision 80960)
@@ -90,6 +90,6 @@
  */
 VMMR0_INT_DECL(int)  IOMR0IoPortSetUpContext(PGVM pGVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                             PFNIOMIOPORTOUT pfnOut,  PFNIOMIOPORTIN pfnIn,
-                                             PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, void *pvUser)
+                                             PFNIOMIOPORTNEWOUT pfnOut,  PFNIOMIOPORTNEWIN pfnIn,
+                                             PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
 {
     /*
Index: /trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp	(revision 80959)
+++ /trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp	(revision 80960)
@@ -192,6 +192,6 @@
 /** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
 static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
-                                                          PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                                          PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr,
+                                                          PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                                          PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
                                                           void *pvUser)
 {
@@ -1110,4 +1110,16 @@
 
 
+/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
+static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
+{
+    PDMDEV_ASSERT_DEVINS(pDevIns);
+    PGVM pGVM = pDevIns->Internal.s.pGVM;
+    AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
+    PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
+    LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
+    return pRetDevIns;
+}
+
+
 /**
  * The Ring-0 PCI Bus Helper Callbacks.
@@ -1121,4 +1133,5 @@
     pdmR0PciHlp_Lock,
     pdmR0PciHlp_Unlock,
+    pdmR0PciHlp_GetBusByNo,
     PDM_PCIHLPR0_VERSION, /* the end */
 };
Index: /trunk/src/VBox/VMM/VMMR3/IOM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/IOM.cpp	(revision 80959)
+++ /trunk/src/VBox/VMM/VMMR3/IOM.cpp	(revision 80960)
@@ -148,4 +148,8 @@
 static FNIOMIOPORTINSTRING  iomR3IOPortDummyInStr;
 static FNIOMIOPORTOUTSTRING iomR3IOPortDummyOutStr;
+static FNIOMIOPORTNEWIN        iomR3IOPortDummyNewIn;
+static FNIOMIOPORTNEWOUT       iomR3IOPortDummyNewOut;
+static FNIOMIOPORTNEWINSTRING  iomR3IOPortDummyNewInStr;
+static FNIOMIOPORTNEWOUTSTRING iomR3IOPortDummyNewOutStr;
 
 #ifdef VBOX_WITH_STATISTICS
@@ -452,6 +456,6 @@
  */
 VMMR3_INT_DECL(int)  IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
-                                       uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                       PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
+                                       uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                       PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
                                        const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
 {
@@ -524,8 +528,8 @@
     pVM->iom.s.paIoPortRegs[idx].pvUser             = pvUser;
     pVM->iom.s.paIoPortRegs[idx].pDevIns            = pDevIns;
-    pVM->iom.s.paIoPortRegs[idx].pfnOutCallback     = pfnOut    ? pfnOut    : iomR3IOPortDummyOut;
-    pVM->iom.s.paIoPortRegs[idx].pfnInCallback      = pfnIn     ? pfnIn     : iomR3IOPortDummyIn;
-    pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback  = pfnOutStr ? pfnOutStr : iomR3IOPortDummyOutStr;
-    pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback   = pfnInStr  ? pfnInStr  : iomR3IOPortDummyInStr;
+    pVM->iom.s.paIoPortRegs[idx].pfnOutCallback     = pfnOut    ? pfnOut    : iomR3IOPortDummyNewOut;
+    pVM->iom.s.paIoPortRegs[idx].pfnInCallback      = pfnIn     ? pfnIn     : iomR3IOPortDummyNewIn;
+    pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback  = pfnOutStr ? pfnOutStr : iomR3IOPortDummyNewOutStr;
+    pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback   = pfnInStr  ? pfnInStr  : iomR3IOPortDummyNewInStr;
     pVM->iom.s.paIoPortRegs[idx].pszDesc            = pszDesc;
     pVM->iom.s.paIoPortRegs[idx].paExtDescs         = paExtDescs;
@@ -592,6 +596,6 @@
                         /* Insert after the entry we just considered: */
                         pEntry += 1;
-                        if (iEnd < cEntries)
-                            memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - iEnd));
+                        if (i < cEntries)
+                            memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
                         break;
                     }
@@ -604,6 +608,6 @@
                     {
                         /* Insert at the entry we just considered: */
-                        if (iEnd < cEntries)
-                            memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - iEnd));
+                        if (i < cEntries)
+                            memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
                         break;
                     }
@@ -761,5 +765,5 @@
 
         RTIOPORT uPortPrev = paEntries[0].uLastPort;
-        for (i = 1; i <= cEntries; i++)
+        for (i = 1; i < cEntries - 1; i++)
         {
             AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
@@ -1697,4 +1701,61 @@
 
 /**
+ * @callback_method_impl{FNIOMIOPORTNEWIN,
+ *      Dummy Port I/O Handler for IN operations.}
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+iomR3IOPortDummyNewIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
+{
+    NOREF(pDevIns); NOREF(pvUser); NOREF(Port);
+    switch (cb)
+    {
+        case 1: *pu32 = 0xff; break;
+        case 2: *pu32 = 0xffff; break;
+        case 4: *pu32 = UINT32_C(0xffffffff); break;
+        default:
+            AssertReleaseMsgFailed(("cb=%d\n", cb));
+            return VERR_IOM_IOPORT_IPE_2;
+    }
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMIOPORTNEWINSTRING,
+ *      Dummy Port I/O Handler for string IN operations.}
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+iomR3IOPortDummyNewInStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t *pbDst, uint32_t *pcTransfer, unsigned cb)
+{
+    NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbDst); NOREF(pcTransfer); NOREF(cb);
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMIOPORTNEWOUT,
+ *      Dummy Port I/O Handler for OUT operations.}
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+iomR3IOPortDummyNewOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
+{
+    NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(u32); NOREF(cb);
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
+ *      Dummy Port I/O Handler for string OUT operations.}
+ */
+static DECLCALLBACK(VBOXSTRICTRC)
+iomR3IOPortDummyNewOutStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t const *pbSrc, uint32_t *pcTransfer, unsigned cb)
+{
+    NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbSrc); NOREF(pcTransfer); NOREF(cb);
+    return VINF_SUCCESS;
+}
+
+
+/**
  * Display a single I/O port ring-3 range.
  *
Index: /trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp	(revision 80959)
+++ /trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp	(revision 80960)
@@ -99,6 +99,6 @@
 /** @interface_method_impl{PDMDEVHLPR3,pfnIoPortCreateEx} */
 static DECLCALLBACK(int) pdmR3DevHlp_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
-                                                    uint32_t iPciRegion, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
-                                                    PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, RTR3PTR pvUser,
+                                                    uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
+                                                    PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
                                                     const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
 {
Index: /trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp	(revision 80959)
+++ /trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp	(revision 80960)
@@ -295,38 +295,13 @@
 
 
-/** @interface_method_impl{PDMPCIHLPR3,pfnGetRCHelpers} */
-static DECLCALLBACK(PCPDMPCIHLPRC) pdmR3PciHlp_GetRCHelpers(PPDMDEVINS pDevIns)
-{
-    PDMDEV_ASSERT_DEVINS(pDevIns);
-    PVM pVM = pDevIns->Internal.s.pVMR3;
-    VM_ASSERT_EMT(pVM);
-
-    RTRCPTR pRCHelpers = NIL_RTRCPTR;
-    if (VM_IS_RAW_MODE_ENABLED(pVM))
-    {
-        int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciHlp", &pRCHelpers);
-        AssertReleaseRC(rc);
-        AssertRelease(pRCHelpers);
-    }
-
-    LogFlow(("pdmR3PciHlp_GetRCHelpers: caller='%s'/%d: returns %RRv\n",
-             pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
-    return pRCHelpers;
-}
-
-
-/** @interface_method_impl{PDMPCIHLPR3,pfnGetR0Helpers} */
-static DECLCALLBACK(PCPDMPCIHLPR0) pdmR3PciHlp_GetR0Helpers(PPDMDEVINS pDevIns)
-{
-    PDMDEV_ASSERT_DEVINS(pDevIns);
-    PVM pVM = pDevIns->Internal.s.pVMR3;
-    VM_ASSERT_EMT(pVM);
-    PCPDMPCIHLPR0 pR0Helpers = 0;
-    int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciHlp", &pR0Helpers);
-    AssertReleaseRC(rc);
-    AssertRelease(pR0Helpers);
-    LogFlow(("pdmR3PciHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
-             pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
-    return pR0Helpers;
+/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
+static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
+{
+    PDMDEV_ASSERT_DEVINS(pDevIns);
+    PVM pVM = pDevIns->Internal.s.pVMR3;
+    AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
+    PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
+    LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
+    return pRetDevIns;
 }
 
@@ -342,8 +317,7 @@
     pdmR3PciHlp_IoApicSendMsi,
     pdmR3PciHlp_IsMMIO2Base,
-    pdmR3PciHlp_GetRCHelpers,
-    pdmR3PciHlp_GetR0Helpers,
     pdmR3PciHlp_Lock,
     pdmR3PciHlp_Unlock,
+    pdmR3PciHlp_GetBusByNo,
     PDM_PCIHLPR3_VERSION, /* the end */
 };
Index: /trunk/src/VBox/VMM/include/IOMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/IOMInternal.h	(revision 80959)
+++ /trunk/src/VBox/VMM/include/IOMInternal.h	(revision 80960)
@@ -167,11 +167,11 @@
     R0PTRTYPE(PPDMDEVINS)               pDevIns;
     /** Pointer to OUT callback function. */
-    R0PTRTYPE(PFNIOMIOPORTOUT)          pfnOutCallback;
+    R0PTRTYPE(PFNIOMIOPORTNEWOUT)       pfnOutCallback;
     /** Pointer to IN callback function. */
-    R0PTRTYPE(PFNIOMIOPORTIN)           pfnInCallback;
+    R0PTRTYPE(PFNIOMIOPORTNEWIN)        pfnInCallback;
     /** Pointer to string OUT callback function. */
-    R0PTRTYPE(PFNIOMIOPORTOUTSTRING)    pfnOutStrCallback;
+    R0PTRTYPE(PFNIOMIOPORTNEWOUTSTRING) pfnOutStrCallback;
     /** Pointer to string IN callback function. */
-    R0PTRTYPE(PFNIOMIOPORTINSTRING)     pfnInStrCallback;
+    R0PTRTYPE(PFNIOMIOPORTNEWINSTRING)  pfnInStrCallback;
     /** The entry of the first statistics entry, UINT16_MAX if no stats. */
     uint16_t                            idxStats;
@@ -196,11 +196,11 @@
     R3PTRTYPE(PPDMDEVINS)               pDevIns;
     /** Pointer to OUT callback function. */
-    R3PTRTYPE(PFNIOMIOPORTOUT)          pfnOutCallback;
+    R3PTRTYPE(PFNIOMIOPORTNEWOUT)       pfnOutCallback;
     /** Pointer to IN callback function. */
-    R3PTRTYPE(PFNIOMIOPORTIN)           pfnInCallback;
+    R3PTRTYPE(PFNIOMIOPORTNEWIN)        pfnInCallback;
     /** Pointer to string OUT callback function. */
-    R3PTRTYPE(PFNIOMIOPORTOUTSTRING)    pfnOutStrCallback;
+    R3PTRTYPE(PFNIOMIOPORTNEWOUTSTRING) pfnOutStrCallback;
     /** Pointer to string IN callback function. */
-    R3PTRTYPE(PFNIOMIOPORTINSTRING)     pfnInStrCallback;
+    R3PTRTYPE(PFNIOMIOPORTNEWINSTRING)  pfnInStrCallback;
     /** Description / Name. For easing debugging. */
     R3PTRTYPE(const char *)             pszDesc;
