Changeset 81031 in vbox for trunk/src/VBox/Devices/Network
- Timestamp:
- Sep 26, 2019 7:26:33 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 133634
- Location:
- trunk/src/VBox/Devices/Network
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Network/DevE1000.cpp
r80923 r81031 1094 1094 /** Base port of I/O space region. */ 1095 1095 RTIOPORT IOPortBase; 1096 /** EMT: */1097 PDMPCIDEV pciDevice;1098 1096 /** EMT: Last time the interrupt was acknowledged. */ 1099 1097 uint64_t u64AckedAt; … … 6284 6282 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 6285 6283 { 6284 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *); 6286 6285 RT_NOREF(pPciDev, iRegion); 6287 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *);6288 int rc; 6289 6286 Assert(pPciDev == pDevIns->apPciDevs[0]); 6287 6288 int rc; 6290 6289 switch (enmType) 6291 6290 { … … 7605 7604 Assert(eChip < RT_ELEMENTS(g_aChips)); 7606 7605 /* Configure PCI Device, assume 32-bit mode ******************************/ 7607 P CIDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);7608 P CIDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);7609 P CIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);7610 P CIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);7611 7612 P CIDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);7606 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId); 7607 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId); 7608 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId); 7609 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId); 7610 7611 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000); 7613 7612 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */ 7614 P CIDevSetWord( pPciDev, VBOX_PCI_STATUS,7615 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);7613 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS, 7614 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ); 7616 7615 /* Stepping A2 */ 7617 P CIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);7616 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02); 7618 7617 /* Ethernet adapter */ 7619 P CIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);7620 P CIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);7618 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00); 7619 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200); 7621 7620 /* normal single function Ethernet controller */ 7622 P CIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);7621 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00); 7623 7622 /* Memory Register Base Address */ 7624 P CIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);7623 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000); 7625 7624 /* Memory Flash Base Address */ 7626 P CIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);7625 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000); 7627 7626 /* IO Register Base Address */ 7628 P CIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);7627 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001); 7629 7628 /* Expansion ROM Base Address */ 7630 P CIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);7629 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000); 7631 7630 /* Capabilities Pointer */ 7632 P CIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);7631 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC); 7633 7632 /* Interrupt Pin: INTA# */ 7634 P CIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);7633 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01); 7635 7634 /* Max_Lat/Min_Gnt: very high priority and time slice */ 7636 P CIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);7637 P CIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);7635 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF); 7636 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00); 7638 7637 7639 7638 /* PCI Power Management Registers ****************************************/ 7640 7639 /* Capability ID: PCI Power Management Registers */ 7641 P CIDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);7640 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM); 7642 7641 /* Next Item Pointer: PCI-X */ 7643 P CIDevSetByte( pPciDev, 0xDC + 1, 0xE4);7642 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4); 7644 7643 /* Power Management Capabilities: PM disabled, DSI */ 7645 P CIDevSetWord( pPciDev, 0xDC + 2,7646 0x0002 | VBOX_PCI_PM_CAP_DSI);7644 PDMPciDevSetWord( pPciDev, 0xDC + 2, 7645 0x0002 | VBOX_PCI_PM_CAP_DSI); 7647 7646 /* Power Management Control / Status Register: PM disabled */ 7648 P CIDevSetWord( pPciDev, 0xDC + 4, 0x0000);7647 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000); 7649 7648 /* PMCSR_BSE Bridge Support Extensions: Not supported */ 7650 P CIDevSetByte( pPciDev, 0xDC + 6, 0x00);7649 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00); 7651 7650 /* Data Register: PM disabled, always 0 */ 7652 P CIDevSetByte( pPciDev, 0xDC + 7, 0x00);7651 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00); 7653 7652 7654 7653 /* PCI-X Configuration Registers *****************************************/ 7655 7654 /* Capability ID: PCI-X Configuration Registers */ 7656 P CIDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);7655 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX); 7657 7656 #ifdef E1K_WITH_MSI 7658 P CIDevSetByte( pPciDev, 0xE4 + 1, 0x80);7657 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80); 7659 7658 #else 7660 7659 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */ 7661 P CIDevSetByte( pPciDev, 0xE4 + 1, 0x00);7660 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00); 7662 7661 #endif 7663 7662 /* PCI-X Command: Enable Relaxed Ordering */ 7664 P CIDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);7663 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO); 7665 7664 /* PCI-X Status: 32-bit, 66MHz*/ 7666 7665 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */ 7667 P CIDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);7666 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8); 7668 7667 } 7669 7668 … … 7834 7833 7835 7834 /* Set PCI config registers and register ourselves with the PCI bus. */ 7836 e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip); 7837 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice); 7835 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]); 7836 e1kConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip); 7837 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]); 7838 7838 if (RT_FAILURE(rc)) 7839 7839 return rc; -
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r80923 r81031 305 305 * PCNET state. 306 306 * 307 * @extends PDMPCIDEV308 307 * @implements PDMIBASE 309 308 * @implements PDMINETWORKDOWN … … 313 312 typedef struct PCNETSTATE 314 313 { 315 PDMPCIDEV PciDev;316 317 314 /** Pointer to the device instance - R3. */ 318 315 PPDMDEVINSR3 pDevInsR3; … … 3420 3417 3421 3418 #ifdef IN_RING3 /* move down */ 3422 static void pcnetR3HardReset(PP CNETSTATE pThis)3419 static void pcnetR3HardReset(PPDMDEVINS pDevIns, PPCNETSTATE pThis) 3423 3420 { 3424 3421 int i; … … 3432 3429 { 3433 3430 Log(("#%d INTA=%d\n", PCNET_INST_NR, pThis->iISR)); 3434 PDMDevHlpPCISetIrq( PCNETSTATE_2_DEVINS(pThis), 0, pThis->iISR);3431 PDMDevHlpPCISetIrq(pDevIns, 0, pThis->iISR); 3435 3432 } 3436 3433 else 3437 3434 { 3438 3435 Log(("#%d IRQ=%d, state=%d\n", PCNET_INST_NR, pThis->uIsaIrq, pThis->iISR)); 3439 PDMDevHlpISASetIrq( PCNETSTATE_2_DEVINS(pThis), pThis->uIsaIrq, pThis->iISR);3436 PDMDevHlpISASetIrq(pDevIns, pThis->uIsaIrq, pThis->iISR); 3440 3437 } 3441 3438 } … … 3482 3479 pThis->aBCR[BCR_MIICAS ] = 0x20; /* Auto-negotiation on. */ 3483 3480 pThis->aBCR[BCR_MIIADDR ] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */ 3484 pThis->aBCR[BCR_PCIVID] = PCIDevGetVendorId(&pThis->PciDev); 3485 pThis->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(&pThis->PciDev); 3486 pThis->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(&pThis->PciDev); 3481 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; 3482 pThis->aBCR[BCR_PCIVID] = PCIDevGetVendorId(pPciDev); 3483 pThis->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(pPciDev); 3484 pThis->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(pPciDev); 3487 3485 3488 3486 /* Reset the error counter. */ … … 4082 4080 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 4083 4081 { 4084 RT_NOREF(iRegion, cb, enmType);4085 int rc;4086 RT IOPORT Port = (RTIOPORT)GCPhysAddress;4087 PPCNETSTATE pThis = PCIDEV_2_PCNETSTATE(pPciDev); 4088 4082 PPCNETSTATE pThis = PDMINS_2_DATA(pDevIns, PPCNETSTATE); 4083 RTIOPORT Port = (RTIOPORT)GCPhysAddress; 4084 RT_NOREF(iRegion, cb, enmType, pPciDev); 4085 4086 Assert(pDevIns->apPciDevs[0] == pPciDev); 4089 4087 Assert(enmType == PCI_ADDRESS_SPACE_IO); 4090 4088 Assert(cb >= 0x20); 4091 4089 4092 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 0x10, 0, pcnetIOPortAPromWrite,4093 pcnetIOPortAPromRead, NULL, NULL, "PCnet APROM");4090 int rc = PDMDevHlpIOPortRegister(pDevIns, Port, 0x10, 0, pcnetIOPortAPromWrite, 4091 pcnetIOPortAPromRead, NULL, NULL, "PCnet APROM"); 4094 4092 if (RT_FAILURE(rc)) 4095 4093 return rc; … … 4133 4131 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 4134 4132 { 4135 RT_NOREF(iRegion, cb, enmType);4136 PPCNETSTATE pThis = PCIDEV_2_PCNETSTATE(pPciDev);4137 int rc; 4138 4133 PPCNETSTATE pThis = PDMINS_2_DATA(pDevIns, PPCNETSTATE); 4134 RT_NOREF(iRegion, cb, enmType, pPciDev); 4135 4136 Assert(pDevIns->apPciDevs[0] == pPciDev); 4139 4137 Assert(enmType == PCI_ADDRESS_SPACE_MEM); 4140 4138 Assert(cb >= PCNET_PNPMMIO_SIZE); 4141 4139 4142 4140 /* We use the assigned size here, because we only support page aligned MMIO ranges. */ 4143 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pThis,4144 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,4145 pcnetMMIOWrite, pcnetMMIORead, "PCnet");4141 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pThis, 4142 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU, 4143 pcnetMMIOWrite, pcnetMMIORead, "PCnet"); 4146 4144 if (RT_FAILURE(rc)) 4147 4145 return rc; … … 4542 4540 /* older saved states contain the shared memory region which was never used for ages. */ 4543 4541 void *pvSharedMMIOR3; 4544 rc = PDMDevHlpMMIO2Register(pDevIns, &pThis->PciDev, 2, _512K, 0, (void **)&pvSharedMMIOR3, "PCnetSh");4542 rc = PDMDevHlpMMIO2Register(pDevIns, pDevIns->apPciDevs[0], 2, _512K, 0, (void **)&pvSharedMMIOR3, "PCnetSh"); 4545 4543 if (RT_FAILURE(rc)) 4546 4544 rc = PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, … … 5062 5060 5063 5061 /** @todo How to flush the queues? */ 5064 pcnetR3HardReset(p This);5062 pcnetR3HardReset(pDevIns, pThis); 5065 5063 } 5066 5064 … … 5257 5255 5258 5256 /* PCI Device */ 5259 PCIDevSetVendorId(&pThis->PciDev, 0x1022); 5260 PCIDevSetDeviceId(&pThis->PciDev, 0x2000); 5261 pThis->PciDev.abConfig[0x04] = 0x07; /* command */ 5262 pThis->PciDev.abConfig[0x05] = 0x00; 5263 pThis->PciDev.abConfig[0x06] = 0x80; /* status */ 5264 pThis->PciDev.abConfig[0x07] = 0x02; 5265 pThis->PciDev.abConfig[0x08] = pThis->uDevType == DEV_AM79C973 ? 0x40 : 0x10; /* revision */ 5266 pThis->PciDev.abConfig[0x09] = 0x00; 5267 pThis->PciDev.abConfig[0x0a] = 0x00; /* ethernet network controller */ 5268 pThis->PciDev.abConfig[0x0b] = 0x02; 5269 pThis->PciDev.abConfig[0x0e] = 0x00; /* header_type */ 5270 5271 pThis->PciDev.abConfig[0x10] = 0x01; /* IO Base */ 5272 pThis->PciDev.abConfig[0x11] = 0x00; 5273 pThis->PciDev.abConfig[0x12] = 0x00; 5274 pThis->PciDev.abConfig[0x13] = 0x00; 5275 pThis->PciDev.abConfig[0x14] = 0x00; /* MMIO Base */ 5276 pThis->PciDev.abConfig[0x15] = 0x00; 5277 pThis->PciDev.abConfig[0x16] = 0x00; 5278 pThis->PciDev.abConfig[0x17] = 0x00; 5257 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; 5258 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); 5259 5260 PDMPciDevSetVendorId(pPciDev, 0x1022); 5261 PDMPciDevSetDeviceId(pPciDev, 0x2000); 5262 PDMPciDevSetByte(pPciDev, 0x04, 0x07); /* command */ 5263 PDMPciDevSetByte(pPciDev, 0x05, 0x00); 5264 PDMPciDevSetByte(pPciDev, 0x06, 0x80); /* status */ 5265 PDMPciDevSetByte(pPciDev, 0x07, 0x02); 5266 PDMPciDevSetByte(pPciDev, 0x08, pThis->uDevType == DEV_AM79C973 ? 0x40 : 0x10); /* revision */ 5267 PDMPciDevSetByte(pPciDev, 0x09, 0x00); 5268 PDMPciDevSetByte(pPciDev, 0x0a, 0x00); /* ethernet network controller */ 5269 PDMPciDevSetByte(pPciDev, 0x0b, 0x02); 5270 PDMPciDevSetByte(pPciDev, 0x0e, 0x00); /* header_type */ 5271 PDMPciDevSetByte(pPciDev, 0x10, 0x01); /* IO Base */ 5272 PDMPciDevSetByte(pPciDev, 0x11, 0x00); 5273 PDMPciDevSetByte(pPciDev, 0x12, 0x00); 5274 PDMPciDevSetByte(pPciDev, 0x13, 0x00); 5275 PDMPciDevSetByte(pPciDev, 0x14, 0x00); /* MMIO Base */ 5276 PDMPciDevSetByte(pPciDev, 0x15, 0x00); 5277 PDMPciDevSetByte(pPciDev, 0x16, 0x00); 5278 PDMPciDevSetByte(pPciDev, 0x17, 0x00); 5279 5279 5280 5280 /* subsystem and subvendor IDs */ 5281 pThis->PciDev.abConfig[0x2c] = 0x22; /* subsystem vendor id */5282 pThis->PciDev.abConfig[0x2d] = 0x10;5283 pThis->PciDev.abConfig[0x2e] = 0x00; /* subsystem id */5284 pThis->PciDev.abConfig[0x2f] = 0x20;5285 pThis->PciDev.abConfig[0x3d] = 1; /* interrupt pin 0 */5286 pThis->PciDev.abConfig[0x3e] = 0x06;5287 pThis->PciDev.abConfig[0x3f] = 0xff;5281 PDMPciDevSetByte(pPciDev, 0x2c, 0x22); /* subsystem vendor id */ 5282 PDMPciDevSetByte(pPciDev, 0x2d, 0x10); 5283 PDMPciDevSetByte(pPciDev, 0x2e, 0x00); /* subsystem id */ 5284 PDMPciDevSetByte(pPciDev, 0x2f, 0x20); 5285 PDMPciDevSetByte(pPciDev, 0x3d, 1); /* interrupt pin 0 */ 5286 PDMPciDevSetByte(pPciDev, 0x3e, 0x06); 5287 PDMPciDevSetByte(pPciDev, 0x3f, 0xff); 5288 5288 5289 5289 /* … … 5303 5303 if (PCNET_IS_PCI(pThis)) 5304 5304 { 5305 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);5305 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev); 5306 5306 if (RT_FAILURE(rc)) 5307 5307 return rc; … … 5476 5476 * Reset the device state. (Do after attaching.) 5477 5477 */ 5478 pcnetR3HardReset(p This);5478 pcnetR3HardReset(pDevIns, pThis); 5479 5479 5480 5480 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Public/Net/PCnet%u/BytesReceived", iInstance); -
trunk/src/VBox/Devices/Network/DevVirtioNet.cpp
r80704 r81031 1973 1973 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 1974 1974 { 1975 PVNETSTATE pThis = PDMINS_2_DATA(pDevIns, PVNETSTATE); 1975 1976 RT_NOREF(pPciDev, iRegion); 1976 PVNETSTATE pThis = PDMINS_2_DATA(pDevIns, PVNETSTATE);1977 int rc;1978 1977 1979 1978 if (enmType != PCI_ADDRESS_SPACE_IO) … … 1985 1984 1986 1985 pThis->VPCI.IOPortBase = (RTIOPORT)GCPhysAddress; 1987 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->VPCI.IOPortBase,1988 cb, 0, vnetIOPortOut, vnetIOPortIn,1989 NULL, NULL, "VirtioNet");1986 int rc = PDMDevHlpIOPortRegister(pDevIns, pThis->VPCI.IOPortBase, 1987 cb, 0, vnetIOPortOut, vnetIOPortIn, 1988 NULL, NULL, "VirtioNet"); 1990 1989 #ifdef VNET_GC_SUPPORT 1991 1990 AssertRCReturn(rc, rc);
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