Index: trunk/src/VBox/Devices/Network/DevE1000.cpp
===================================================================
--- trunk/src/VBox/Devices/Network/DevE1000.cpp	(revision 80986)
+++ trunk/src/VBox/Devices/Network/DevE1000.cpp	(revision 81031)
@@ -1094,6 +1094,4 @@
     /** Base port of I/O space region. */
     RTIOPORT    IOPortBase;
-    /** EMT: */
-    PDMPCIDEV   pciDevice;
     /** EMT: Last time the interrupt was acknowledged.  */
     uint64_t    u64AckedAt;
@@ -6284,8 +6282,9 @@
                                 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
 {
+    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *);
     RT_NOREF(pPciDev, iRegion);
-    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *);
-    int       rc;
-
+    Assert(pPciDev == pDevIns->apPciDevs[0]);
+
+    int rc;
     switch (enmType)
     {
@@ -7605,65 +7604,65 @@
     Assert(eChip < RT_ELEMENTS(g_aChips));
     /* Configure PCI Device, assume 32-bit mode ******************************/
-    PCIDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
-    PCIDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
-    PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
-    PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
-
-    PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND,            0x0000);
+    PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
+    PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
+    PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
+    PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
+
+    PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND,            0x0000);
     /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
-    PCIDevSetWord( pPciDev, VBOX_PCI_STATUS,
-                   VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST |  VBOX_PCI_STATUS_66MHZ);
+    PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
+                      VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST |  VBOX_PCI_STATUS_66MHZ);
     /* Stepping A2 */
-    PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID,          0x02);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID,          0x02);
     /* Ethernet adapter */
-    PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG,           0x00);
-    PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE,       0x0200);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG,           0x00);
+    PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE,       0x0200);
     /* normal single function Ethernet controller */
-    PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE,          0x00);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE,          0x00);
     /* Memory Register Base Address */
-    PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
+    PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
     /* Memory Flash Base Address */
-    PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
+    PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
     /* IO Register Base Address */
-    PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
+    PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
     /* Expansion ROM Base Address */
-    PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS,    0x00000000);
+    PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS,    0x00000000);
     /* Capabilities Pointer */
-    PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST,      0xDC);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST,      0xDC);
     /* Interrupt Pin: INTA# */
-    PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN,        0x01);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN,        0x01);
     /* Max_Lat/Min_Gnt: very high priority and time slice */
-    PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT,              0xFF);
-    PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT,              0x00);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT,              0xFF);
+    PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT,              0x00);
 
     /* PCI Power Management Registers ****************************************/
     /* Capability ID: PCI Power Management Registers */
-    PCIDevSetByte( pPciDev, 0xDC,            VBOX_PCI_CAP_ID_PM);
+    PDMPciDevSetByte( pPciDev, 0xDC,            VBOX_PCI_CAP_ID_PM);
     /* Next Item Pointer: PCI-X */
-    PCIDevSetByte( pPciDev, 0xDC + 1,                      0xE4);
+    PDMPciDevSetByte( pPciDev, 0xDC + 1,                      0xE4);
     /* Power Management Capabilities: PM disabled, DSI */
-    PCIDevSetWord( pPciDev, 0xDC + 2,
-                    0x0002 | VBOX_PCI_PM_CAP_DSI);
+    PDMPciDevSetWord( pPciDev, 0xDC + 2,
+                      0x0002 | VBOX_PCI_PM_CAP_DSI);
     /* Power Management Control / Status Register: PM disabled */
-    PCIDevSetWord( pPciDev, 0xDC + 4,                    0x0000);
+    PDMPciDevSetWord( pPciDev, 0xDC + 4,                    0x0000);
     /* PMCSR_BSE Bridge Support Extensions: Not supported */
-    PCIDevSetByte( pPciDev, 0xDC + 6,                      0x00);
+    PDMPciDevSetByte( pPciDev, 0xDC + 6,                      0x00);
     /* Data Register: PM disabled, always 0 */
-    PCIDevSetByte( pPciDev, 0xDC + 7,                      0x00);
+    PDMPciDevSetByte( pPciDev, 0xDC + 7,                      0x00);
 
     /* PCI-X Configuration Registers *****************************************/
     /* Capability ID: PCI-X Configuration Registers */
-    PCIDevSetByte( pPciDev, 0xE4,          VBOX_PCI_CAP_ID_PCIX);
+    PDMPciDevSetByte( pPciDev, 0xE4,          VBOX_PCI_CAP_ID_PCIX);
 #ifdef E1K_WITH_MSI
-    PCIDevSetByte( pPciDev, 0xE4 + 1,                      0x80);
+    PDMPciDevSetByte( pPciDev, 0xE4 + 1,                      0x80);
 #else
     /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
-    PCIDevSetByte( pPciDev, 0xE4 + 1,                      0x00);
+    PDMPciDevSetByte( pPciDev, 0xE4 + 1,                      0x00);
 #endif
     /* PCI-X Command: Enable Relaxed Ordering */
-    PCIDevSetWord( pPciDev, 0xE4 + 2,        VBOX_PCI_X_CMD_ERO);
+    PDMPciDevSetWord( pPciDev, 0xE4 + 2,        VBOX_PCI_X_CMD_ERO);
     /* PCI-X Status: 32-bit, 66MHz*/
     /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
-    PCIDevSetDWord(pPciDev, 0xE4 + 4,                0x0040FFF8);
+    PDMPciDevSetDWord(pPciDev, 0xE4 + 4,                0x0040FFF8);
 }
 
@@ -7834,6 +7833,7 @@
 
     /* Set PCI config registers and register ourselves with the PCI bus. */
-    e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip);
-    rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice);
+    PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
+    e1kConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
+    rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
     if (RT_FAILURE(rc))
         return rc;
Index: trunk/src/VBox/Devices/Network/DevPCNet.cpp
===================================================================
--- trunk/src/VBox/Devices/Network/DevPCNet.cpp	(revision 80986)
+++ trunk/src/VBox/Devices/Network/DevPCNet.cpp	(revision 81031)
@@ -305,5 +305,4 @@
  * PCNET state.
  *
- * @extends     PDMPCIDEV
  * @implements  PDMIBASE
  * @implements  PDMINETWORKDOWN
@@ -313,6 +312,4 @@
 typedef struct PCNETSTATE
 {
-    PDMPCIDEV                           PciDev;
-
     /** Pointer to the device instance - R3. */
     PPDMDEVINSR3                        pDevInsR3;
@@ -3420,5 +3417,5 @@
 
 #ifdef IN_RING3 /* move down */
-static void pcnetR3HardReset(PPCNETSTATE pThis)
+static void pcnetR3HardReset(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
 {
     int      i;
@@ -3432,10 +3429,10 @@
         {
             Log(("#%d INTA=%d\n", PCNET_INST_NR, pThis->iISR));
-            PDMDevHlpPCISetIrq(PCNETSTATE_2_DEVINS(pThis), 0, pThis->iISR);
+            PDMDevHlpPCISetIrq(pDevIns, 0, pThis->iISR);
         }
         else
         {
             Log(("#%d IRQ=%d, state=%d\n", PCNET_INST_NR, pThis->uIsaIrq, pThis->iISR));
-            PDMDevHlpISASetIrq(PCNETSTATE_2_DEVINS(pThis), pThis->uIsaIrq, pThis->iISR);
+            PDMDevHlpISASetIrq(pDevIns, pThis->uIsaIrq, pThis->iISR);
         }
     }
@@ -3482,7 +3479,8 @@
     pThis->aBCR[BCR_MIICAS  ] = 0x20;   /* Auto-negotiation on. */
     pThis->aBCR[BCR_MIIADDR ] = 0;  /* Internal PHY on Am79C973 would be (0x1e << 5) */
-    pThis->aBCR[BCR_PCIVID] = PCIDevGetVendorId(&pThis->PciDev);
-    pThis->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(&pThis->PciDev);
-    pThis->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(&pThis->PciDev);
+    PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
+    pThis->aBCR[BCR_PCIVID] = PCIDevGetVendorId(pPciDev);
+    pThis->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(pPciDev);
+    pThis->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(pPciDev);
 
     /* Reset the error counter. */
@@ -4082,14 +4080,14 @@
                                         RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
 {
-    RT_NOREF(iRegion, cb, enmType);
-    int         rc;
-    RTIOPORT    Port    = (RTIOPORT)GCPhysAddress;
-    PPCNETSTATE pThis   = PCIDEV_2_PCNETSTATE(pPciDev);
-
+    PPCNETSTATE pThis = PDMINS_2_DATA(pDevIns, PPCNETSTATE);
+    RTIOPORT    Port  = (RTIOPORT)GCPhysAddress;
+    RT_NOREF(iRegion, cb, enmType, pPciDev);
+
+    Assert(pDevIns->apPciDevs[0] == pPciDev);
     Assert(enmType == PCI_ADDRESS_SPACE_IO);
     Assert(cb >= 0x20);
 
-    rc = PDMDevHlpIOPortRegister(pDevIns, Port, 0x10, 0, pcnetIOPortAPromWrite,
-                                 pcnetIOPortAPromRead, NULL, NULL, "PCnet APROM");
+    int rc = PDMDevHlpIOPortRegister(pDevIns, Port, 0x10, 0, pcnetIOPortAPromWrite,
+                                     pcnetIOPortAPromRead, NULL, NULL, "PCnet APROM");
     if (RT_FAILURE(rc))
         return rc;
@@ -4133,15 +4131,15 @@
                                       RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
 {
-    RT_NOREF(iRegion, cb, enmType);
-    PPCNETSTATE pThis = PCIDEV_2_PCNETSTATE(pPciDev);
-    int         rc;
-
+    PPCNETSTATE pThis = PDMINS_2_DATA(pDevIns, PPCNETSTATE);
+    RT_NOREF(iRegion, cb, enmType, pPciDev);
+
+    Assert(pDevIns->apPciDevs[0] == pPciDev);
     Assert(enmType == PCI_ADDRESS_SPACE_MEM);
     Assert(cb >= PCNET_PNPMMIO_SIZE);
 
     /* We use the assigned size here, because we only support page aligned MMIO ranges. */
-    rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pThis,
-                               IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
-                               pcnetMMIOWrite, pcnetMMIORead, "PCnet");
+    int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pThis,
+                                   IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
+                                   pcnetMMIOWrite, pcnetMMIORead, "PCnet");
     if (RT_FAILURE(rc))
         return rc;
@@ -4542,5 +4540,5 @@
         /* older saved states contain the shared memory region which was never used for ages. */
         void *pvSharedMMIOR3;
-        rc = PDMDevHlpMMIO2Register(pDevIns, &pThis->PciDev, 2, _512K, 0, (void **)&pvSharedMMIOR3, "PCnetSh");
+        rc = PDMDevHlpMMIO2Register(pDevIns, pDevIns->apPciDevs[0], 2, _512K, 0, (void **)&pvSharedMMIOR3, "PCnetSh");
         if (RT_FAILURE(rc))
             rc = PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
@@ -5062,5 +5060,5 @@
 
     /** @todo How to flush the queues? */
-    pcnetR3HardReset(pThis);
+    pcnetR3HardReset(pDevIns, pThis);
 }
 
@@ -5257,33 +5255,35 @@
 
     /* PCI Device */
-    PCIDevSetVendorId(&pThis->PciDev, 0x1022);
-    PCIDevSetDeviceId(&pThis->PciDev, 0x2000);
-    pThis->PciDev.abConfig[0x04] = 0x07; /* command */
-    pThis->PciDev.abConfig[0x05] = 0x00;
-    pThis->PciDev.abConfig[0x06] = 0x80; /* status */
-    pThis->PciDev.abConfig[0x07] = 0x02;
-    pThis->PciDev.abConfig[0x08] = pThis->uDevType == DEV_AM79C973 ? 0x40 : 0x10; /* revision */
-    pThis->PciDev.abConfig[0x09] = 0x00;
-    pThis->PciDev.abConfig[0x0a] = 0x00; /* ethernet network controller */
-    pThis->PciDev.abConfig[0x0b] = 0x02;
-    pThis->PciDev.abConfig[0x0e] = 0x00; /* header_type */
-
-    pThis->PciDev.abConfig[0x10] = 0x01; /* IO Base */
-    pThis->PciDev.abConfig[0x11] = 0x00;
-    pThis->PciDev.abConfig[0x12] = 0x00;
-    pThis->PciDev.abConfig[0x13] = 0x00;
-    pThis->PciDev.abConfig[0x14] = 0x00; /* MMIO Base */
-    pThis->PciDev.abConfig[0x15] = 0x00;
-    pThis->PciDev.abConfig[0x16] = 0x00;
-    pThis->PciDev.abConfig[0x17] = 0x00;
+    PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
+    PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
+
+    PDMPciDevSetVendorId(pPciDev,       0x1022);
+    PDMPciDevSetDeviceId(pPciDev,       0x2000);
+    PDMPciDevSetByte(pPciDev, 0x04,     0x07); /* command */
+    PDMPciDevSetByte(pPciDev, 0x05,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x06,     0x80); /* status */
+    PDMPciDevSetByte(pPciDev, 0x07,     0x02);
+    PDMPciDevSetByte(pPciDev, 0x08,     pThis->uDevType == DEV_AM79C973 ? 0x40 : 0x10); /* revision */
+    PDMPciDevSetByte(pPciDev, 0x09,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x0a,     0x00); /* ethernet network controller */
+    PDMPciDevSetByte(pPciDev, 0x0b,     0x02);
+    PDMPciDevSetByte(pPciDev, 0x0e,     0x00); /* header_type */
+    PDMPciDevSetByte(pPciDev, 0x10,     0x01); /* IO Base */
+    PDMPciDevSetByte(pPciDev, 0x11,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x12,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x13,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x14,     0x00); /* MMIO Base */
+    PDMPciDevSetByte(pPciDev, 0x15,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x16,     0x00);
+    PDMPciDevSetByte(pPciDev, 0x17,     0x00);
 
     /* subsystem and subvendor IDs */
-    pThis->PciDev.abConfig[0x2c] = 0x22; /* subsystem vendor id */
-    pThis->PciDev.abConfig[0x2d] = 0x10;
-    pThis->PciDev.abConfig[0x2e] = 0x00; /* subsystem id */
-    pThis->PciDev.abConfig[0x2f] = 0x20;
-    pThis->PciDev.abConfig[0x3d] = 1;    /* interrupt pin 0 */
-    pThis->PciDev.abConfig[0x3e] = 0x06;
-    pThis->PciDev.abConfig[0x3f] = 0xff;
+    PDMPciDevSetByte(pPciDev, 0x2c,     0x22); /* subsystem vendor id */
+    PDMPciDevSetByte(pPciDev, 0x2d,     0x10);
+    PDMPciDevSetByte(pPciDev, 0x2e,     0x00); /* subsystem id */
+    PDMPciDevSetByte(pPciDev, 0x2f,     0x20);
+    PDMPciDevSetByte(pPciDev, 0x3d,     1);    /* interrupt pin 0 */
+    PDMPciDevSetByte(pPciDev, 0x3e,     0x06);
+    PDMPciDevSetByte(pPciDev, 0x3f,     0xff);
 
     /*
@@ -5303,5 +5303,5 @@
     if (PCNET_IS_PCI(pThis))
     {
-        rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
+        rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
         if (RT_FAILURE(rc))
             return rc;
@@ -5476,5 +5476,5 @@
      * Reset the device state. (Do after attaching.)
      */
-    pcnetR3HardReset(pThis);
+    pcnetR3HardReset(pDevIns, pThis);
 
     PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes,       STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,          "Amount of data received",            "/Public/Net/PCnet%u/BytesReceived", iInstance);
Index: trunk/src/VBox/Devices/Network/DevVirtioNet.cpp
===================================================================
--- trunk/src/VBox/Devices/Network/DevVirtioNet.cpp	(revision 80986)
+++ trunk/src/VBox/Devices/Network/DevVirtioNet.cpp	(revision 81031)
@@ -1973,7 +1973,6 @@
                                  RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
 {
+    PVNETSTATE pThis = PDMINS_2_DATA(pDevIns, PVNETSTATE);
     RT_NOREF(pPciDev, iRegion);
-    PVNETSTATE pThis = PDMINS_2_DATA(pDevIns, PVNETSTATE);
-    int       rc;
 
     if (enmType != PCI_ADDRESS_SPACE_IO)
@@ -1985,7 +1984,7 @@
 
     pThis->VPCI.IOPortBase = (RTIOPORT)GCPhysAddress;
-    rc = PDMDevHlpIOPortRegister(pDevIns, pThis->VPCI.IOPortBase,
-                                 cb, 0, vnetIOPortOut, vnetIOPortIn,
-                                 NULL, NULL, "VirtioNet");
+    int rc = PDMDevHlpIOPortRegister(pDevIns, pThis->VPCI.IOPortBase,
+                                     cb, 0, vnetIOPortOut, vnetIOPortIn,
+                                     NULL, NULL, "VirtioNet");
 #ifdef VNET_GC_SUPPORT
     AssertRCReturn(rc, rc);
