Changeset 81035 in vbox

Timestamp:

Sep 26, 2019 8:22:35 PM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

133638

Message:

DevPci: Allow access to config space above 256 bytes with ICH9. bugref:9218

Location:

trunk

Files:

• include/VBox/vmm/pdmpcidevint.h (modified) (1 diff)
• src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (8 diffs)
• src/VBox/Devices/Bus/MsixCommon.cpp (modified) (4 diffs)

trunk/include/VBox/vmm/pdmpcidevint.h

@@ -194 +194 @@
 
     /** Pointer to bus specific data. (R3 ptr) */
-    R3PTRTYPE(const void *)         pPciBusPtrR3;
+    R3PTRTYPE(const void *)         pvPciBusPtrR3;
     /** I/O regions. */
     PCIIOREGION                     aIORegions[VBOX_PCI_NUM_REGIONS];

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -151 +151 @@
     int                 iIrqPinBridge  = ((pPciDev->uDevFn >> 3) + iIrq) & 3;
     uint64_t            bmSeen[256/64] = { 0, 0, 0, 0 };
-    ASMBitSet(bmSeen, RT_MIN(pPciDevBus->Int.s.idxPdmBus, 255));
+    ASMBitSet(bmSeen, pPciDevBus->Int.s.idxPdmBus); AssertCompile(sizeof(pPciDevBus->Int.s.idxPdmBus) == 1);
 
     /* Walk the chain until we reach the host bus. */
@@ -2458 +2458 @@
 {
     uint32_t uValue;
-    if (uAddress + cb <= 256)
+    if (uAddress + cb <= RT_MIN(pPciDev->cbConfig, sizeof(pPciDev->abConfig)))
     {
         switch (cb)
@@ -2491 +2491 @@
     else
     {
-        if (uAddress + cb < _4K)
-            LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
-                    pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
-        else
-            AssertFailed();
+        AssertMsgFailed(("Read after end of PCI config space: %#x LB %u\n", uAddress, cb));
         uValue = 0;
     }
@@ -2824 +2820 @@
     VBOXSTRICTRC rcStrict = VINF_SUCCESS;
 
-    if (uAddress + cb <= 256)
+    if (uAddress + cb <= RT_MIN(pPciDev->cbConfig, sizeof(pPciDev->abConfig)))
     {
         /*
@@ -2905 +2901 @@
                             break;
                         }
-                        else if (uAddress < VBOX_PCI_BASE_ADDRESS_2 || uAddress > VBOX_PCI_BASE_ADDRESS_5+3)
+                        if (uAddress < VBOX_PCI_BASE_ADDRESS_2 || uAddress > VBOX_PCI_BASE_ADDRESS_5+3)
                         {
                             /* PCI bridges have only BAR0, BAR1 and ROM */
@@ -2913 +2909 @@
                             break;
                         }
-                        else if (   uAddress == VBOX_PCI_IO_BASE
-                                 || uAddress == VBOX_PCI_IO_LIMIT
-                                 || uAddress == VBOX_PCI_MEMORY_BASE
-                                 || uAddress == VBOX_PCI_MEMORY_LIMIT
-                                 || uAddress == VBOX_PCI_PREF_MEMORY_BASE
-                                 || uAddress == VBOX_PCI_PREF_MEMORY_LIMIT)
+                        if (   uAddress == VBOX_PCI_IO_BASE
+                            || uAddress == VBOX_PCI_IO_LIMIT
+                            || uAddress == VBOX_PCI_MEMORY_BASE
+                            || uAddress == VBOX_PCI_MEMORY_LIMIT
+                            || uAddress == VBOX_PCI_PREF_MEMORY_BASE
+                            || uAddress == VBOX_PCI_PREF_MEMORY_LIMIT)
                         {
                             /* All bridge address decoders have the low 4 bits
@@ -2948 +2944 @@
         }
     }
-    else if (uAddress + cb <= _4K)
-        LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
-                pPciDev->pszNameR3, pPciDev->Int.s.CTX_SUFF(pDevIns)->iInstance, uAddress));
     else
-        AssertMsgFailed(("Write after end of PCI config space\n"));
+        AssertMsgFailed(("Write after end of PCI config space: %#x LB %u\n", uAddress, cb));
 
     return rcStrict;
@@ -3624 +3617 @@
     pBus->fPureBridge = true;
     pBusCC->pDevInsR3 = pDevIns;
-    /** @todo r=klaus figure out how to extend this to allow PCIe config space
-     * extension, which increases the config space from 256 bytes to 4K.
-     * bird: What does this allocation have to do with PCIe config space?!?  */
     pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices));
     AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);

trunk/src/VBox/Devices/Bus/MsixCommon.cpp

@@ -120 +120 @@
 PDMBOTHCBDECL(int) msixR3MMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
 {
-    LogFlowFunc(("\n"));
-
-    uint32_t off = (uint32_t)(GCPhysAddr & 0xffff);
     PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
+    uint32_t   off     = (uint32_t)(GCPhysAddr & 0xffff);
+    LogFlowFunc(("GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb));
 
     /// @todo qword accesses?
     RT_NOREF(pDevIns);
-    AssertMsgReturn(cb == 4,
-                    ("MSI-X must be accessed with 4-byte reads"),
-                    VERR_INTERNAL_ERROR);
-    AssertMsgReturn(off + cb <= pPciDev->Int.s.cbMsixRegion,
-                    ("Out of bounds access for the MSI-X region\n"),
-                    VINF_IOM_MMIO_UNUSED_FF);
-
-    *(uint32_t *)pv = *(uint32_t *)msixGetPageOffset(pPciDev, off);
+    AssertMsgReturn(cb == 4, ("MSI-X must be accessed with 4-byte reads\n"), VERR_INTERNAL_ERROR);
+    AssertMsgReturn(off + cb <= pPciDev->Int.s.cbMsixRegion, ("Out of bounds access for the MSI-X region\n"), VINF_IOM_MMIO_UNUSED_FF);
+    *(uint32_t *)pv = *(uint32_t *)&pPciDev->abMsixState[off];
+
     return VINF_SUCCESS;
 }
@@ -140 +135 @@
 PDMBOTHCBDECL(int) msixR3MMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
 {
-    LogFlowFunc(("\n"));
-
     PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
-    uint32_t off = (uint32_t)(GCPhysAddr & 0xffff);
+    uint32_t   off     = (uint32_t)(GCPhysAddr & 0xffff);
+    LogFlowFunc(("GCPhysAddr=%RGp cb=%d\n", GCPhysAddr, cb));
 
     /// @todo qword accesses?
-    AssertMsgReturn(cb == 4,
-                    ("MSI-X must be accessed with 4-byte reads"),
-                    VERR_INTERNAL_ERROR);
-    AssertMsgReturn(off + cb <= pPciDev->Int.s.offMsixPba,
-                    ("Trying to write to PBA\n"), VINF_SUCCESS);
-
-    *(uint32_t *)msixGetPageOffset(pPciDev, off) = *(uint32_t *)pv;
-
-    msixR3CheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
+    AssertMsgReturn(cb == 4, ("MSI-X must be accessed with 4-byte reads\n"), VERR_INTERNAL_ERROR);
+    AssertMsgReturn(off + cb <= pPciDev->Int.s.offMsixPba, ("Trying to write to PBA\n"), VINF_SUCCESS);
+    *(uint32_t *)&pPciDev->abMsixState[off] = *(uint32_t *)pv;
+
+    /* (See MsixR3Init the setting up of pvPciBusPtrR3.) */
+    msixR3CheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pvPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
     return VINF_SUCCESS;
 }
@@ -167 +158 @@
     NOREF(iRegion); NOREF(enmType);
 
-    int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pPciDev,
-                                   IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
-                                   msixR3MMIOWrite, msixR3MMIORead, "MSI-X tables");
-
-    if (RT_FAILURE(rc))
-        return rc;
-
-    return VINF_SUCCESS;
+    return PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pPciDev,
+                                 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
+                                 msixR3MMIOWrite, msixR3MMIORead, "MSI-X tables");
 }
 
@@ -228 +214 @@
 
     /* R3 PCI helper */
-    pDev->Int.s.pPciBusPtrR3    = pPciHlp;
+    pDev->Int.s.pvPciBusPtrR3   = pPciHlp;
 
     PCIDevSetByte(pDev,  iCapOffset + 0, VBOX_PCI_CAP_ID_MSIX);