VirtualBox

Changeset 81380 in vbox


Ignore:
Timestamp:
Oct 19, 2019 8:05:18 PM (5 years ago)
Author:
vboxsync
Message:

DevE1000: Start converting it to the new device model. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Network/DevE1000.cpp

    r81218 r81380  
    10791079    RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
    10801080    RTRCPTR                 RCPtrAlignment;
    1081 
    10821081#if HC_ARCH_BITS != 32
    10831082    uint32_t                Alignment1;
    10841083#endif
     1084
     1085    /** Handle to PCI region \#0, the MMIO region. */
     1086    IOMIOPORTHANDLE         hMmioRegion;
     1087    /** Handle to PCI region \#2, the I/O ports. */
     1088    IOMIOPORTHANDLE         hIoPorts;
     1089
    10851090    PDMCRITSECT cs;                  /**< Critical section - what is it protecting? */
    10861091    PDMCRITSECT csRx;                                     /**< RX Critical section. */
    … …  
    60026007 * @thread  EMT
    60036008 */
    6004 static int e1kRegReadAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
     6009static VBOXSTRICTRC e1kRegReadAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
    60056010{
    60066011    Assert(!(offReg & 3));
    … …  
    60096014     * Lookup the register and check that it's readable.
    60106015     */
    6011     int rc     = VINF_SUCCESS;
    6012     int idxReg = e1kRegLookup(offReg);
     6016    VBOXSTRICTRC rc     = VINF_SUCCESS;
     6017    int          idxReg = e1kRegLookup(offReg);
    60136018    if (RT_LIKELY(idxReg != -1))
    60146019    {
    … …  
    60546059 * @thread  EMT
    60556060 */
    6056 static int e1kRegWriteAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
    6057 {
    6058     int        rc    = VINF_SUCCESS;
    6059     int         index = e1kRegLookup(offReg);
     6061static VBOXSTRICTRC e1kRegWriteAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
     6062{
     6063    VBOXSTRICTRC rc    = VINF_SUCCESS;
     6064    int          index = e1kRegLookup(offReg);
    60606065    if (RT_LIKELY(index != -1))
    60616066    {
    … …  
    60946099
    60956100/**
    6096  * @callback_method_impl{FNIOMMMIOREAD}
    6097  */
    6098 PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
     6101 * @callback_method_impl{FNIOMMMIONEWREAD}
     6102 */
     6103static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
    60996104{
    61006105    RT_NOREF2(pvUser, cb);
    … …  
    61026107    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
    61036108
    6104     uint32_t  offReg = GCPhysAddr - pThis->addrMMReg;
    6105     Assert(offReg < E1K_MM_SIZE);
     6109    Assert(off < E1K_MM_SIZE);
    61066110    Assert(cb == 4);
    6107     Assert(!(GCPhysAddr & 3));
    6108 
    6109     int rc = e1kRegReadAlignedU32(pThis, offReg, (uint32_t *)pv);
     6111    Assert(!(off & 3));
     6112
     6113    VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pThis, (uint32_t)off, (uint32_t *)pv);
    61106114
    61116115    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
    6112     return rc;
    6113 }
    6114 
    6115 /**
    6116  * @callback_method_impl{FNIOMMMIOWRITE}
    6117  */
    6118 PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
     6116    return rcStrict;
     6117}
     6118
     6119/**
     6120 * @callback_method_impl{FNIOMMMIONEWWRITE}
     6121 */
     6122static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
    61196123{
    61206124    RT_NOREF2(pvUser, cb);
    … …  
    61226126    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
    61236127
    6124     uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
    6125     Assert(offReg < E1K_MM_SIZE);
     6128    Assert(off < E1K_MM_SIZE);
    61266129    Assert(cb == 4);
    6127     Assert(!(GCPhysAddr & 3));
    6128 
    6129     int rc = e1kRegWriteAlignedU32(pThis, offReg, *(uint32_t const *)pv);
     6130    Assert(!(off & 3));
     6131
     6132    VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pThis, (uint32_t)off, *(uint32_t const *)pv);
    61306133
    61316134    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
    6132     return rc;
    6133 }
    6134 
    6135 /**
    6136  * @callback_method_impl{FNIOMIOPORTIN}
    6137  */
    6138 PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
    6139 {
    6140     PE1KSTATE   pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
    6141     int        rc;
     6135    return rcStrict;
     6136}
     6137
     6138/**
     6139 * @callback_method_impl{FNIOMIOPORTNEWIN}
     6140 */
     6141static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
     6142{
     6143    PE1KSTATE    pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     6144    VBOXSTRICTRC rc;
    61426145    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
    61436146    RT_NOREF_PV(pvUser);
    61446147
    6145     uPort -= pThis->IOPortBase;
    61466148    if (RT_LIKELY(cb == 4))
    6147         switch (uPort)
     6149        switch (offPort)
    61486150        {
    61496151            case 0x00: /* IOADDR */
    … …  
    61646166
    61656167            default:
    6166                 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, uPort));
     6168                E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
    61676169                //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
    61686170                rc = VINF_SUCCESS;
    … …  
    61706172    else
    61716173    {
    6172         E1kLog(("%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x", pThis->szPrf, uPort, cb));
    6173         rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb);
     6174        E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
     6175        rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
    61746176    }
    61756177    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
    … …  
    61796181
    61806182/**
    6181  * @callback_method_impl{FNIOMIOPORTOUT}
    6182  */
    6183 PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
    6184 {
    6185     PE1KSTATE   pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
    6186     int        rc;
     6183 * @callback_method_impl{FNIOMIOPORTNEWOUT}
     6184 */
     6185static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
     6186{
     6187    PE1KSTATE    pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     6188    VBOXSTRICTRC rc;
    61876189    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
    61886190    RT_NOREF_PV(pvUser);
    61896191
    6190     E1kLog2(("%s e1kIOPortOut: uPort=%RTiop value=%08x\n", pThis->szPrf, uPort, u32));
     6192    E1kLog2(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
    61916193    if (RT_LIKELY(cb == 4))
    61926194    {
    6193         uPort -= pThis->IOPortBase;
    6194         switch (uPort)
     6195        switch (offPort)
    61956196        {
    61966197            case 0x00: /* IOADDR */
    … …  
    62146215
    62156216            default:
    6216                 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, uPort));
    6217                 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", uPort);
     6217                E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
     6218                rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
    62186219        }
    62196220    }
    62206221    else
    62216222    {
    6222         E1kLog(("%s e1kIOPortOut: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb));
    6223         rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: uPort=%RTiop cb=%#x\n", pThis->szPrf, uPort, cb);
     6223        E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
     6224        rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
    62246225    }
    62256226
    … …  
    62856286/**
    62866287 * @callback_method_impl{FNPCIIOREGIONMAP}
    6287  */
    6288 static DECLCALLBACK(int) e1kMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
    6289                                 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
     6288 *
     6289 * @todo Can remove this one later, it's realy just here for taking down
     6290 *       addresses for e1kInfo(), an alignment assertion and sentimentality.
     6291 */
     6292static DECLCALLBACK(int) e1kR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
     6293                                  RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
    62906294{
    62916295    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    6292     RT_NOREF(pPciDev, iRegion);
     6296    E1kLog(("%s e1kR3Map: iRegion=%u GCPhysAddress=%RGp\n", pThis->szPrf, iRegion, GCPhysAddress));
     6297    RT_NOREF(pPciDev, iRegion, cb);
    62936298    Assert(pPciDev == pDevIns->apPciDevs[0]);
    62946299
    6295     int rc;
    62966300    switch (enmType)
    62976301    {
    62986302        case PCI_ADDRESS_SPACE_IO:
    62996303            pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
    6300             rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase, cb, NULL /*pvUser*/,
    6301                                          e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
    6302             if (pThis->fR0Enabled && RT_SUCCESS(rc))
    6303                 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase, cb, NIL_RTR0PTR /*pvUser*/,
    6304                                              "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
    6305             if (pThis->fRCEnabled && RT_SUCCESS(rc))
    6306                 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, cb, NIL_RTRCPTR /*pvUser*/,
    6307                                                "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
    63086304            break;
    63096305
    63106306        case PCI_ADDRESS_SPACE_MEM:
    6311             /*
    6312              * From the spec:
    6313              *    For registers that should be accessed as 32-bit double words,
    6314              *    partial writes (less than a 32-bit double word) is ignored.
    6315              *    Partial reads return all 32 bits of data regardless of the
    6316              *    byte enables.
    6317              */
    6318 #ifdef E1K_WITH_PREREG_MMIO
    63196307            pThis->addrMMReg = GCPhysAddress;
    6320             if (GCPhysAddress == NIL_RTGCPHYS)
    6321                 rc = VINF_SUCCESS;
    6322             else
    6323             {
    6324                 Assert(!(GCPhysAddress & 7));
    6325                 rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
    6326             }
    6327 #else
    6328             pThis->addrMMReg = GCPhysAddress; Assert(!(GCPhysAddress & 7));
    6329             rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
    6330                                        IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
    6331                                        e1kMMIOWrite, e1kMMIORead, "E1000");
    6332             if (pThis->fR0Enabled && RT_SUCCESS(rc))
    6333                 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
    6334                                              "e1kMMIOWrite", "e1kMMIORead");
    6335             if (pThis->fRCEnabled && RT_SUCCESS(rc))
    6336                 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
    6337                                              "e1kMMIOWrite", "e1kMMIORead");
    6338 #endif
     6308            Assert(!(GCPhysAddress & 7) || GCPhysAddress == NIL_RTGCPHYS);
    63396309            break;
    63406310
    63416311        default:
    63426312            /* We should never get here */
    6343             AssertMsgFailed(("Invalid PCI address space param in map callback"));
    6344             rc = VERR_INTERNAL_ERROR;
    6345             break;
    6346     }
    6347     return rc;
     6313            AssertMsgFailedReturn(("Invalid PCI address space param in map callback"), VERR_INTERNAL_ERROR);
     6314    }
     6315    return VINF_SUCCESS;
    63486316}
    63496317
    … …  
    72507218                    pDevIns->iInstance, pThis->IOPortBase, pThis->addrMMReg,
    72517219                    &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
    7252                     pThis->fRCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
     7220                    pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
    72537221
    72547222    e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
    … …  
    76077575 * @thread  EMT
    76087576 */
    7609 static DECLCALLBACK(void) e1kConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
     7577static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
    76107578{
    76117579    Assert(eChip < RT_ELEMENTS(g_aChips));
    … …  
    77317699     * Validate configuration.
    77327700     */
    7733     if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0"
    7734                                     "LineSpeed\0" "GCEnabled\0" "R0Enabled\0"
    7735                                     "ItrEnabled\0" "ItrRxEnabled\0"
    7736                                     "EthernetCRC\0" "GSOEnabled\0" "LinkUpDelay\0"))
    7737         return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
    7738                                 N_("Invalid configuration for E1000 device"));
     7701    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
     7702                                  "MAC|"
     7703                                  "CableConnected|"
     7704                                  "AdapterType|"
     7705                                  "LineSpeed|"
     7706                                  "ItrEnabled|"
     7707                                  "ItrRxEnabled|"
     7708                                  "EthernetCRC|"
     7709                                  "GSOEnabled|"
     7710                                  "LinkUpDelay", "");
    77397711
    77407712    /** @todo LineSpeed unused! */
    77417713
    7742     /* Get config params */
     7714    /*
     7715     * Get config params
     7716     */
    77437717    rc = CFGMR3QueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
    77447718    if (RT_FAILURE(rc))
    … …  
    77547728                                N_("Configuration error: Failed to get the value of 'AdapterType'"));
    77557729    Assert(pThis->eChip <= E1K_CHIP_82545EM);
    7756     rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fRCEnabled, true);
    7757     if (RT_FAILURE(rc))
    7758         return PDMDEV_SET_ERROR(pDevIns, rc,
    7759                                 N_("Configuration error: Failed to get the value of 'GCEnabled'"));
    7760 
    7761     rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
    7762     if (RT_FAILURE(rc))
    7763         return PDMDEV_SET_ERROR(pDevIns, rc,
    7764                                 N_("Configuration error: Failed to get the value of 'R0Enabled'"));
    77657730
    77667731    rc = CFGMR3QueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
    … …  
    77997764        LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
    78007765
    7801     LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s GC=%s\n", pThis->szPrf,
     7766    LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
    78027767            g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
    78037768            pThis->fEthernetCRC ? "on" : "off",
    … …  
    78067771            pThis->fItrRxEnabled ? "enabled" : "disabled",
    78077772            pThis->fTidEnabled ? "enabled" : "disabled",
    7808             pThis->fR0Enabled ? "enabled" : "disabled",
    7809             pThis->fRCEnabled ? "enabled" : "disabled"));
     7773            pDevIns->fR0Enabled ? "enabled" : "disabled",
     7774            pDevIns->fRCEnabled ? "enabled" : "disabled"));
     7775
     7776    /*
     7777     * Initialize sub-components and register everything with the VMM.
     7778     */
    78107779
    78117780    /* Initialize the EEPROM. */
    … …  
    78207789
    78217790    rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
    7822     if (RT_FAILURE(rc))
    7823         return rc;
     7791    AssertRCReturn(rc, rc);
    78247792    rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
    7825     if (RT_FAILURE(rc))
    7826         return rc;
     7793    AssertRCReturn(rc, rc);
    78277794#ifdef E1K_WITH_TX_CS
    78287795    rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
    7829     if (RT_FAILURE(rc))
    7830         return rc;
    7831 #endif /* E1K_WITH_TX_CS */
     7796    AssertRCReturn(rc, rc);
     7797#endif
    78327798
    78337799    /* Saved state registration. */
    … …  
    78367802                                e1kSavePrep, e1kSaveExec, NULL,
    78377803                                e1kLoadPrep, e1kLoadExec, e1kLoadDone);
    7838     if (RT_FAILURE(rc))
    7839         return rc;
     7804    AssertRCReturn(rc, rc);
    78407805
    78417806    /* Set PCI config registers and register ourselves with the PCI bus. */
    78427807    PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
    7843     e1kConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
     7808    e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
    78447809    rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
    7845     if (RT_FAILURE(rc))
    7846         return rc;
     7810    AssertRCReturn(rc, rc);
    78477811
    78487812#ifdef E1K_WITH_MSI
    … …  
    78577821#endif
    78587822
    7859 
    7860     /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
    7861     rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, e1kMap);
    7862     if (RT_FAILURE(rc))
    7863         return rc;
    7864 #ifdef E1K_WITH_PREREG_MMIO
    7865     rc = PDMDevHlpMMIOExPreRegister(pDevIns, 0, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD, "E1000",
    7866                                     NULL        /*pvUserR3*/, e1kMMIOWrite, e1kMMIORead, NULL /*pfnFillR3*/,
    7867                                     NIL_RTR0PTR /*pvUserR0*/, pThis->fR0Enabled ? "e1kMMIOWrite" : NULL,
    7868                                     pThis->fR0Enabled ? "e1kMMIORead" : NULL, NULL /*pszFillR0*/,
    7869                                     NIL_RTRCPTR /*pvUserRC*/, pThis->fRCEnabled ? "e1kMMIOWrite" : NULL,
    7870                                     pThis->fRCEnabled ? "e1kMMIORead" : NULL, NULL /*pszFillRC*/);
    7871     AssertLogRelRCReturn(rc, rc);
    7872 #endif
    7873     /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
    7874     rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE, PCI_ADDRESS_SPACE_IO, e1kMap);
    7875     if (RT_FAILURE(rc))
    7876         return rc;
     7823    /*
     7824     * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
     7825     * From the spec (regarding flags):
     7826     *    For registers that should be accessed as 32-bit double words,
     7827     *    partial writes (less than a 32-bit double word) is ignored.
     7828     *    Partial reads return all 32 bits of data regardless of the
     7829     *    byte enables.
     7830     */
     7831    rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
     7832                               pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
     7833                               e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
     7834    AssertRCReturn(rc, rc);
     7835    rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, e1kR3Map);
     7836    AssertRCReturn(rc, rc);
     7837
     7838    /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
     7839    rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
     7840                               e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", NULL /*paExtDescs*/, &pThis->hIoPorts);
     7841    AssertRCReturn(rc, rc);
     7842    rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts, e1kR3Map);
     7843    AssertRCReturn(rc, rc);
    78777844
    78787845    /* Create transmit queue */
     7846/** @todo Convert queues to be accessed via handles. Create a ring-3 task thingy for 1 item queues. */
    78797847    rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
    78807848                              e1kTxQueueConsumer, true, "E1000-Xmit", &pThis->pTxQueueR3);
    7881     if (RT_FAILURE(rc))
    7882         return rc;
     7849    AssertRCReturn(rc, rc);
    78837850    pThis->pTxQueueR0 = PDMQueueR0Ptr(pThis->pTxQueueR3);
    78847851    pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
    … …  
    78877854    rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
    78887855                              e1kCanRxQueueConsumer, true, "E1000-Rcv", &pThis->pCanRxQueueR3);
    7889     if (RT_FAILURE(rc))
    7890         return rc;
     7856    AssertRCReturn(rc, rc);
    78917857    pThis->pCanRxQueueR0 = PDMQueueR0Ptr(pThis->pCanRxQueueR3);
    78927858    pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
    … …  
    78977863                                TMTIMER_FLAGS_NO_CRIT_SECT,
    78987864                                "E1000 Transmit Delay Timer", &pThis->pTXDTimerR3);
    7899     if (RT_FAILURE(rc))
    7900         return rc;
     7865    AssertRCReturn(rc, rc);
    79017866    pThis->pTXDTimerR0 = TMTimerR0Ptr(pThis->pTXDTimerR3);
    79027867    pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
    … …  
    81088073}
    81098074
    8110 #endif /* IN_RING3 */
     8075#else  /* !IN_RING3 */
     8076
     8077/**
     8078 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
     8079 */
     8080static DECLCALLBACK(int)  e1kRZConstruct(PPDMDEVINS pDevIns)
     8081{
     8082    PE1KSTATE   pThis   = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     8083    //PE1KSTATER0 pThisCC = PDMINS_2_DATA_CC(pDevIns, PRTCSTATECC);
     8084    //pThisCC->CTX_SUFF(pDevIns) = pDevIns;
     8085
     8086    int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
     8087    AssertRCReturn(rc, rc);
     8088
     8089    rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
     8090    AssertRCReturn(rc, rc);
     8091
     8092    return VINF_SUCCESS;
     8093}
     8094
     8095#endif /* !IN_RING3 */
    81118096
    81128097/**
    … …  
    81558140#elif defined(IN_RING0)
    81568141    /* .pfnEarlyConstruct = */      NULL,
    8157     /* .pfnConstruct = */           NULL,
     8142    /* .pfnConstruct = */           e1kRZConstruct,
    81588143    /* .pfnDestruct = */            NULL,
    81598144    /* .pfnFinalDestruct = */       NULL,
    … …  
    81688153    /* .pfnReserved7 = */           NULL,
    81698154#elif defined(IN_RC)
    8170     /* .pfnConstruct = */           NULL,
     8155    /* .pfnConstruct = */           e1kRZConstruct,
    81718156    /* .pfnReserved0 = */           NULL,
    81728157    /* .pfnReserved1 = */           NULL,
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette