VirtualBox

Changeset 81477 in vbox for trunk


Ignore:
Timestamp:
Oct 23, 2019 9:02:53 AM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
134202
Message:

DevPCI: CFGM and SSM via helpers. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r81136 r81477  
    926926 *
    927927 * @returns VBox status code.
     928 * @param   pHlp            The device helpers.
    928929 * @param   pBus            The bus to save.
    929930 * @param   pSSM            The saved state handle.
    930931 */
    931 static int pciR3CommonSaveExec(PDEVPCIBUS pBus, PSSMHANDLE pSSM)
     932static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
    932933{
    933934    /*
    … …  
    939940        if (pDev)
    940941        {
    941             SSMR3PutU32(pSSM, uDevFn);
    942             SSMR3PutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
    943 
    944             SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
     942            pHlp->pfnSSMPutU32(pSSM, uDevFn);
     943            pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
     944
     945            pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
    945946
    946947            /* Save the type an size of all the regions. */
    947948            for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
    948949            {
    949                 SSMR3PutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
    950                 SSMR3PutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
     950                pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
     951                pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
    951952            }
    952953        }
    953954    }
    954     return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
     955    return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
    955956}
    956957
    … …  
    961962static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    962963{
    963     PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     964    PDEVPCIROOT   pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     965    PCPDMDEVHLPR3 pHlp  = pDevIns->pHlpR3;
    964966
    965967    /*
    966968     * Bus state data.
    967969     */
    968     SSMR3PutU32(pSSM, pThis->uConfigReg);
    969     SSMR3PutBool(pSSM, pThis->fUseIoApic);
     970    pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
     971    pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
    970972
    971973    /*
    … …  
    973975     */
    974976    for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
    975         SSMR3PutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
     977        pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
    976978    for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
    977         SSMR3PutU32(pSSM, pThis->auPciApicIrqLevels[i]);
    978 
    979     SSMR3PutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
    980     SSMR3PutS32(pSSM, pThis->Piix3.iAcpiIrq);
    981 
    982     SSMR3PutU32(pSSM, UINT32_MAX);      /* separator */
     979        pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
     980
     981    pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
     982    pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
     983
     984    pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);      /* separator */
    983985
    984986    /*
    985987     * Join paths with pcibridgeR3SaveExec.
    986988     */
    987     return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
     989    return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
    988990}
    989991
    … …  
    10011003static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    10021004{
    1003     uint32_t    u32;
    1004     int         rc;
     1005    PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
     1006    uint32_t      u32;
     1007    int           rc;
    10051008
    10061009    Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
    … …  
    10321035    {
    10331036        /* index / terminator */
    1034         rc = SSMR3GetU32(pSSM, &u32);
     1037        rc = pHlp->pfnSSMGetU32(pSSM, &u32);
    10351038        if (RT_FAILURE(rc))
    10361039            return rc;
    … …  
    10511054                LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
    10521055                        PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
    1053                 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
    1054                     return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
    1055                                             uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
     1056                if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
     1057                    return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
     1058                                                   uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
    10561059            }
    10571060        }
    … …  
    10651068        RT_ZERO(u.DevTmp);
    10661069        u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
    1067         SSMR3GetMem(pSSM, u.DevTmp.abConfig, 256);
     1070        pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
    10681071        if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
    10691072        {
    10701073            int32_t i32Temp;
    10711074            /* Irq value not needed anymore. */
    1072             rc = SSMR3GetS32(pSSM, &i32Temp);
     1075            rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
    10731076            if (RT_FAILURE(rc))
    10741077                return rc;
    … …  
    10761079        else
    10771080        {
    1078             rc = SSMR3GetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
     1081            rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
    10791082            if (RT_FAILURE(rc))
    10801083                return rc;
    … …  
    10861089            for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
    10871090            {
    1088                 SSMR3GetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
    1089                 rc = SSMR3GetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
     1091                pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
     1092                rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
    10901093                AssertLogRelRCReturn(rc, rc);
    10911094            }
    … …  
    10981101            LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
    10991102                    PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
    1100             if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
    1101                 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
    1102                                         uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
     1103            if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
     1104                return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
     1105                                               uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
    11031106            continue;
    11041107        }
    … …  
    11071110        if (   u.DevTmp.abConfig[0] != pDev->abConfig[0]
    11081111            || u.DevTmp.abConfig[1] != pDev->abConfig[1])
    1109             return SSMR3SetCfgError(pSSM, RT_SRC_POS,
    1110                                     N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
    1111                                     uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
     1112            return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
     1113                                           N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
     1114                                           uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
    11121115
    11131116        /* commit the loaded device config. */
    … …  
    11301133static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    11311134{
    1132     PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    1133     PDEVPCIBUS  pBus  = &pThis->PciBus;
    1134     uint32_t    u32;
    1135     int         rc;
     1135    PDEVPCIROOT   pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1136    PDEVPCIBUS    pBus  = &pThis->PciBus;
     1137    PCPDMDEVHLPR3 pHlp  = pDevIns->pHlpR3;
     1138    uint32_t      u32;
     1139    int           rc;
    11361140
    11371141    /*
    … …  
    11451149     * Bus state data.
    11461150     */
    1147     SSMR3GetU32(pSSM, &pThis->uConfigReg);
     1151    pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
    11481152    if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
    1149         SSMR3GetBool(pSSM, &pThis->fUseIoApic);
     1153        pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
    11501154
    11511155    /* Load IRQ states. */
    … …  
    11531157    {
    11541158        for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
    1155             SSMR3GetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
     1159            pHlp->pfnSSMGetU32(pSSM, (uint32_t *)&pThis->Piix3.auPciLegacyIrqLevels[i]);
    11561160        for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
    1157             SSMR3GetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
    1158 
    1159         SSMR3GetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
    1160         SSMR3GetS32(pSSM, &pThis->Piix3.iAcpiIrq);
     1161            pHlp->pfnSSMGetU32(pSSM, (uint32_t *)&pThis->auPciApicIrqLevels[i]);
     1162
     1163        pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
     1164        pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
    11611165    }
    11621166
    11631167    /* separator */
    1164     rc = SSMR3GetU32(pSSM, &u32);
     1168    rc = pHlp->pfnSSMGetU32(pSSM, &u32);
    11651169    if (RT_FAILURE(rc))
    11661170        return rc;
    … …  
    12571261static DECLCALLBACK(int)   pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
    12581262{
    1259     RT_NOREF1(iInstance);
     1263    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     1264    PCPDMDEVHLPR3 pHlp     = pDevIns->pHlpR3;
     1265    PDEVPCIBUSCC  pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1266    PDEVPCIROOT   pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     1267    RT_NOREF(iInstance);
    12601268    Assert(iInstance == 0);
    1261     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    12621269
    12631270    /*
    … …  
    12681275    /* query whether we got an IOAPIC */
    12691276    bool fUseIoApic;
    1270     int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
     1277    int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
    12711278    if (RT_FAILURE(rc))
    12721279        return PDMDEV_SET_ERROR(pDevIns, rc,
    … …  
    12781285     * Init data and register the PCI bus.
    12791286     */
    1280     PDEVPCIBUSCC pBusCC   = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    1281     PDEVPCIROOT  pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
    1282 
    12831287    pGlobals->uPciBiosIo   = 0xc000;
    12841288    pGlobals->uPciBiosMmio = 0xf0000000;
    … …  
    16151619static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    16161620{
    1617     PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    1618     return pciR3CommonSaveExec(pThis, pSSM);
     1621    return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
    16191622}
    16201623
    … …  
    16651668static DECLCALLBACK(int)   pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
    16661669{
    1667     RT_NOREF(iInstance);
    16681670    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    1669 
    1670     /*
    1671      * Validate and read configuration.
    1672      */
    1673     if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
    1674         return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
    1675 
    1676     /* check if RC code is enabled. */
    1677     bool fGCEnabled;
    1678     int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
    1679     if (RT_FAILURE(rc))
    1680         return PDMDEV_SET_ERROR(pDevIns, rc,
    1681                                 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
    1682 
    1683     /* check if R0 code is enabled. */
    1684     bool fR0Enabled;
    1685     rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
    1686     if (RT_FAILURE(rc))
    1687         return PDMDEV_SET_ERROR(pDevIns, rc,
    1688                                 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
    1689     Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
    1690 
     1671    RT_NOREF(iInstance, pCfg);
    16911672    PDEVPCIBUS   pBus   = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
    16921673    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
     1674
     1675    /*
     1676     * Validate and read configuration (none left).
     1677     */
     1678    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
     1679    Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
    16931680
    16941681    /*
    … …  
    17111698    PciBusReg.pfnSetIrqR3                = pcibridgeSetIrq;
    17121699    PciBusReg.u32EndVersion              = PDM_PCIBUSREGCC_VERSION;
    1713     rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
     1700    int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
    17141701    if (RT_FAILURE(rc))
    1715         return PDMDEV_SET_ERROR(pDevIns, rc,
    1716                                 N_("Failed to register ourselves as a PCI Bus"));
     1702        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
    17171703    Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
    17181704    if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
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