Changeset 81794 in vbox for trunk/src/VBox/Devices/Storage
- Timestamp:
- Nov 12, 2019 10:54:37 AM (5 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Storage/DevFdc.cpp
r81591 r81794 653 653 uint8_t irq_lvl; 654 654 uint8_t dma_chann; 655 uint 32_t io_base;655 uint16_t io_base; 656 656 /* Controller state */ 657 657 struct TMTIMER *result_timer; … … 2232 2232 static DECLCALLBACK(int) fdcSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 2233 2233 { 2234 fdctrl_t *pThis = PDMDEVINS_2_DATA(pDevIns, fdctrl_t *); 2234 fdctrl_t *pThis = PDMDEVINS_2_DATA(pDevIns, fdctrl_t *); 2235 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 2235 2236 unsigned int i; 2236 2237 2237 2238 /* Save the FDC I/O registers... */ 2238 SSMR3PutU8(pSSM, pThis->sra);2239 SSMR3PutU8(pSSM, pThis->srb);2240 SSMR3PutU8(pSSM, pThis->dor);2241 SSMR3PutU8(pSSM, pThis->tdr);2242 SSMR3PutU8(pSSM, pThis->dsr);2243 SSMR3PutU8(pSSM, pThis->msr);2239 pHlp->pfnSSMPutU8(pSSM, pThis->sra); 2240 pHlp->pfnSSMPutU8(pSSM, pThis->srb); 2241 pHlp->pfnSSMPutU8(pSSM, pThis->dor); 2242 pHlp->pfnSSMPutU8(pSSM, pThis->tdr); 2243 pHlp->pfnSSMPutU8(pSSM, pThis->dsr); 2244 pHlp->pfnSSMPutU8(pSSM, pThis->msr); 2244 2245 /* ...the status registers... */ 2245 SSMR3PutU8(pSSM, pThis->status0);2246 SSMR3PutU8(pSSM, pThis->status1);2247 SSMR3PutU8(pSSM, pThis->status2);2246 pHlp->pfnSSMPutU8(pSSM, pThis->status0); 2247 pHlp->pfnSSMPutU8(pSSM, pThis->status1); 2248 pHlp->pfnSSMPutU8(pSSM, pThis->status2); 2248 2249 /* ...the command FIFO... */ 2249 SSMR3PutU32(pSSM, sizeof(pThis->fifo));2250 SSMR3PutMem(pSSM, &pThis->fifo, sizeof(pThis->fifo));2251 SSMR3PutU32(pSSM, pThis->data_pos);2252 SSMR3PutU32(pSSM, pThis->data_len);2253 SSMR3PutU8(pSSM, pThis->data_state);2254 SSMR3PutU8(pSSM, pThis->data_dir);2250 pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->fifo)); 2251 pHlp->pfnSSMPutMem(pSSM, &pThis->fifo, sizeof(pThis->fifo)); 2252 pHlp->pfnSSMPutU32(pSSM, pThis->data_pos); 2253 pHlp->pfnSSMPutU32(pSSM, pThis->data_len); 2254 pHlp->pfnSSMPutU8(pSSM, pThis->data_state); 2255 pHlp->pfnSSMPutU8(pSSM, pThis->data_dir); 2255 2256 /* ...and miscellaneous internal FDC state. */ 2256 SSMR3PutU8(pSSM, pThis->reset_sensei);2257 SSMR3PutU8(pSSM, pThis->eot);2258 SSMR3PutU8(pSSM, pThis->timer0);2259 SSMR3PutU8(pSSM, pThis->timer1);2260 SSMR3PutU8(pSSM, pThis->precomp_trk);2261 SSMR3PutU8(pSSM, pThis->config);2262 SSMR3PutU8(pSSM, pThis->lock);2263 SSMR3PutU8(pSSM, pThis->pwrd);2264 SSMR3PutU8(pSSM, pThis->version);2257 pHlp->pfnSSMPutU8(pSSM, pThis->reset_sensei); 2258 pHlp->pfnSSMPutU8(pSSM, pThis->eot); 2259 pHlp->pfnSSMPutU8(pSSM, pThis->timer0); 2260 pHlp->pfnSSMPutU8(pSSM, pThis->timer1); 2261 pHlp->pfnSSMPutU8(pSSM, pThis->precomp_trk); 2262 pHlp->pfnSSMPutU8(pSSM, pThis->config); 2263 pHlp->pfnSSMPutU8(pSSM, pThis->lock); 2264 pHlp->pfnSSMPutU8(pSSM, pThis->pwrd); 2265 pHlp->pfnSSMPutU8(pSSM, pThis->version); 2265 2266 2266 2267 /* Save the number of drives and per-drive state. Note that the media 2267 2268 * states will be updated in fd_revalidate() and need not be saved. 2268 2269 */ 2269 SSMR3PutU8(pSSM, pThis->num_floppies);2270 pHlp->pfnSSMPutU8(pSSM, pThis->num_floppies); 2270 2271 Assert(RT_ELEMENTS(pThis->drives) == pThis->num_floppies); 2271 2272 for (i = 0; i < pThis->num_floppies; ++i) … … 2273 2274 fdrive_t *d = &pThis->drives[i]; 2274 2275 2275 SSMR3PutMem(pSSM, &d->Led, sizeof(d->Led));2276 SSMR3PutU32(pSSM, d->drive);2277 SSMR3PutU8(pSSM, d->dsk_chg);2278 SSMR3PutU8(pSSM, d->perpendicular);2279 SSMR3PutU8(pSSM, d->head);2280 SSMR3PutU8(pSSM, d->track);2281 SSMR3PutU8(pSSM, d->sect);2276 pHlp->pfnSSMPutMem(pSSM, &d->Led, sizeof(d->Led)); 2277 pHlp->pfnSSMPutU32(pSSM, d->drive); 2278 pHlp->pfnSSMPutU8(pSSM, d->dsk_chg); 2279 pHlp->pfnSSMPutU8(pSSM, d->perpendicular); 2280 pHlp->pfnSSMPutU8(pSSM, d->head); 2281 pHlp->pfnSSMPutU8(pSSM, d->track); 2282 pHlp->pfnSSMPutU8(pSSM, d->sect); 2282 2283 } 2283 2284 return TMR3TimerSave (pThis->result_timer, pSSM); … … 2290 2291 static DECLCALLBACK(int) fdcLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 2291 2292 { 2292 fdctrl_t *pThis = PDMDEVINS_2_DATA(pDevIns, fdctrl_t *); 2293 fdctrl_t *pThis = PDMDEVINS_2_DATA(pDevIns, fdctrl_t *); 2294 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 2293 2295 unsigned int i; 2294 2296 uint32_t val32; 2295 2297 uint8_t val8; 2298 int rc; 2296 2299 2297 2300 if (uVersion > FDC_SAVESTATE_CURRENT) … … 2314 2317 VERR_SSM_DATA_UNIT_FORMAT_CHANGED); 2315 2318 /* Now load the old state. */ 2316 SSMR3GetU8(pSSM, &pThis->version);2319 pHlp->pfnSSMGetU8(pSSM, &pThis->version); 2317 2320 /* Toss IRQ level, DMA channel, I/O base, and state. */ 2318 SSMR3GetU8(pSSM, &val8);2319 SSMR3GetU8(pSSM, &val8);2320 SSMR3GetU32(pSSM, &val32);2321 SSMR3GetU8(pSSM, &val8);2321 pHlp->pfnSSMGetU8(pSSM, &val8); 2322 pHlp->pfnSSMGetU8(pSSM, &val8); 2323 pHlp->pfnSSMGetU32(pSSM, &val32); 2324 pHlp->pfnSSMGetU8(pSSM, &val8); 2322 2325 /* Translate dma_en. */ 2323 SSMR3GetU8(pSSM, &val8); 2326 rc = pHlp->pfnSSMGetU8(pSSM, &val8); 2327 AssertRCReturn(rc, rc); 2324 2328 if (val8) 2325 2329 pThis->dor |= FD_DOR_DMAEN; 2326 SSMR3GetU8(pSSM, &pThis->cur_drv);2330 pHlp->pfnSSMGetU8(pSSM, &pThis->cur_drv); 2327 2331 /* Translate bootsel. */ 2328 SSMR3GetU8(pSSM, &val8); 2332 rc = pHlp->pfnSSMGetU8(pSSM, &val8); 2333 AssertRCReturn(rc, rc); 2329 2334 pThis->tdr |= val8 << 2; 2330 SSMR3GetMem(pSSM, &pThis->fifo, FD_SECTOR_LEN);2331 SSMR3GetU32(pSSM, &pThis->data_pos);2332 SSMR3GetU32(pSSM, &pThis->data_len);2333 SSMR3GetU8(pSSM, &pThis->data_state);2334 SSMR3GetU8(pSSM, &pThis->data_dir);2335 SSMR3GetU8(pSSM, &pThis->status0);2336 SSMR3GetU8(pSSM, &pThis->eot);2337 SSMR3GetU8(pSSM, &pThis->timer0);2338 SSMR3GetU8(pSSM, &pThis->timer1);2339 SSMR3GetU8(pSSM, &pThis->precomp_trk);2340 SSMR3GetU8(pSSM, &pThis->config);2341 SSMR3GetU8(pSSM, &pThis->lock);2342 SSMR3GetU8(pSSM, &pThis->pwrd);2335 pHlp->pfnSSMGetMem(pSSM, &pThis->fifo, FD_SECTOR_LEN); 2336 pHlp->pfnSSMGetU32(pSSM, &pThis->data_pos); 2337 pHlp->pfnSSMGetU32(pSSM, &pThis->data_len); 2338 pHlp->pfnSSMGetU8(pSSM, &pThis->data_state); 2339 pHlp->pfnSSMGetU8(pSSM, &pThis->data_dir); 2340 pHlp->pfnSSMGetU8(pSSM, &pThis->status0); 2341 pHlp->pfnSSMGetU8(pSSM, &pThis->eot); 2342 pHlp->pfnSSMGetU8(pSSM, &pThis->timer0); 2343 pHlp->pfnSSMGetU8(pSSM, &pThis->timer1); 2344 pHlp->pfnSSMGetU8(pSSM, &pThis->precomp_trk); 2345 pHlp->pfnSSMGetU8(pSSM, &pThis->config); 2346 pHlp->pfnSSMGetU8(pSSM, &pThis->lock); 2347 pHlp->pfnSSMGetU8(pSSM, &pThis->pwrd); 2343 2348 2344 2349 for (i = 0; i < 2; ++i) … … 2346 2351 fdrive_t *d = &pThis->drives[i]; 2347 2352 2348 SSMR3GetMem(pSSM, &d->Led, sizeof (d->Led));2349 SSMR3GetU32(pSSM, &val32);2353 pHlp->pfnSSMGetMem(pSSM, &d->Led, sizeof (d->Led)); 2354 rc = pHlp->pfnSSMGetU32(pSSM, &val32); 2350 2355 d->drive = (fdrive_type_t)val32; 2351 SSMR3GetU32(pSSM, &val32); /* Toss drflags */ 2352 SSMR3GetU8(pSSM, &d->perpendicular); 2353 SSMR3GetU8(pSSM, &d->head); 2354 SSMR3GetU8(pSSM, &d->track); 2355 SSMR3GetU8(pSSM, &d->sect); 2356 SSMR3GetU8(pSSM, &val8); /* Toss dir, rw */ 2357 SSMR3GetU8(pSSM, &val8); 2358 SSMR3GetU32(pSSM, &val32); 2356 AssertRCReturn(rc, rc); 2357 pHlp->pfnSSMGetU32(pSSM, &val32); /* Toss drflags */ 2358 pHlp->pfnSSMGetU8(pSSM, &d->perpendicular); 2359 pHlp->pfnSSMGetU8(pSSM, &d->head); 2360 pHlp->pfnSSMGetU8(pSSM, &d->track); 2361 pHlp->pfnSSMGetU8(pSSM, &d->sect); 2362 pHlp->pfnSSMGetU8(pSSM, &val8); /* Toss dir, rw */ 2363 pHlp->pfnSSMGetU8(pSSM, &val8); 2364 rc = pHlp->pfnSSMGetU32(pSSM, &val32); 2365 AssertRCReturn(rc, rc); 2359 2366 d->flags = (fdrive_flags_t)val32; 2360 SSMR3GetU8(pSSM, &d->last_sect);2361 SSMR3GetU8(pSSM, &d->max_track);2362 SSMR3GetU16(pSSM, &d->bps);2363 SSMR3GetU8(pSSM, &d->ro);2367 pHlp->pfnSSMGetU8(pSSM, &d->last_sect); 2368 pHlp->pfnSSMGetU8(pSSM, &d->max_track); 2369 pHlp->pfnSSMGetU16(pSSM, &d->bps); 2370 pHlp->pfnSSMGetU8(pSSM, &d->ro); 2364 2371 } 2365 2372 } … … 2368 2375 Assert(uVersion == FDC_SAVESTATE_CURRENT); 2369 2376 /* Load the FDC I/O registers... */ 2370 SSMR3GetU8(pSSM, &pThis->sra);2371 SSMR3GetU8(pSSM, &pThis->srb);2372 SSMR3GetU8(pSSM, &pThis->dor);2373 SSMR3GetU8(pSSM, &pThis->tdr);2374 SSMR3GetU8(pSSM, &pThis->dsr);2375 SSMR3GetU8(pSSM, &pThis->msr);2377 pHlp->pfnSSMGetU8(pSSM, &pThis->sra); 2378 pHlp->pfnSSMGetU8(pSSM, &pThis->srb); 2379 pHlp->pfnSSMGetU8(pSSM, &pThis->dor); 2380 pHlp->pfnSSMGetU8(pSSM, &pThis->tdr); 2381 pHlp->pfnSSMGetU8(pSSM, &pThis->dsr); 2382 pHlp->pfnSSMGetU8(pSSM, &pThis->msr); 2376 2383 /* ...the status registers... */ 2377 SSMR3GetU8(pSSM, &pThis->status0);2378 SSMR3GetU8(pSSM, &pThis->status1);2379 SSMR3GetU8(pSSM, &pThis->status2);2384 pHlp->pfnSSMGetU8(pSSM, &pThis->status0); 2385 pHlp->pfnSSMGetU8(pSSM, &pThis->status1); 2386 pHlp->pfnSSMGetU8(pSSM, &pThis->status2); 2380 2387 /* ...the command FIFO, if the size matches... */ 2381 SSMR3GetU32(pSSM, &val32); 2388 rc = pHlp->pfnSSMGetU32(pSSM, &val32); 2389 AssertRCReturn(rc, rc); 2382 2390 AssertMsgReturn(sizeof(pThis->fifo) == val32, 2383 2391 ("The size of FIFO in saved state doesn't match!\n"), 2384 2392 VERR_SSM_DATA_UNIT_FORMAT_CHANGED); 2385 SSMR3GetMem(pSSM, &pThis->fifo, sizeof(pThis->fifo));2386 SSMR3GetU32(pSSM, &pThis->data_pos);2387 SSMR3GetU32(pSSM, &pThis->data_len);2388 SSMR3GetU8(pSSM, &pThis->data_state);2389 SSMR3GetU8(pSSM, &pThis->data_dir);2393 pHlp->pfnSSMGetMem(pSSM, &pThis->fifo, sizeof(pThis->fifo)); 2394 pHlp->pfnSSMGetU32(pSSM, &pThis->data_pos); 2395 pHlp->pfnSSMGetU32(pSSM, &pThis->data_len); 2396 pHlp->pfnSSMGetU8(pSSM, &pThis->data_state); 2397 pHlp->pfnSSMGetU8(pSSM, &pThis->data_dir); 2390 2398 /* ...and miscellaneous internal FDC state. */ 2391 SSMR3GetU8(pSSM, &pThis->reset_sensei);2392 SSMR3GetU8(pSSM, &pThis->eot);2393 SSMR3GetU8(pSSM, &pThis->timer0);2394 SSMR3GetU8(pSSM, &pThis->timer1);2395 SSMR3GetU8(pSSM, &pThis->precomp_trk);2396 SSMR3GetU8(pSSM, &pThis->config);2397 SSMR3GetU8(pSSM, &pThis->lock);2398 SSMR3GetU8(pSSM, &pThis->pwrd);2399 SSMR3GetU8(pSSM, &pThis->version);2399 pHlp->pfnSSMGetU8(pSSM, &pThis->reset_sensei); 2400 pHlp->pfnSSMGetU8(pSSM, &pThis->eot); 2401 pHlp->pfnSSMGetU8(pSSM, &pThis->timer0); 2402 pHlp->pfnSSMGetU8(pSSM, &pThis->timer1); 2403 pHlp->pfnSSMGetU8(pSSM, &pThis->precomp_trk); 2404 pHlp->pfnSSMGetU8(pSSM, &pThis->config); 2405 pHlp->pfnSSMGetU8(pSSM, &pThis->lock); 2406 pHlp->pfnSSMGetU8(pSSM, &pThis->pwrd); 2407 pHlp->pfnSSMGetU8(pSSM, &pThis->version); 2400 2408 2401 2409 /* Validate the number of drives. */ 2402 SSMR3GetU8(pSSM, &pThis->num_floppies); 2410 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->num_floppies); 2411 AssertRCReturn(rc, rc); 2403 2412 AssertMsgReturn(RT_ELEMENTS(pThis->drives) == pThis->num_floppies, 2404 2413 ("The number of drives in saved state doesn't match!\n"), … … 2410 2419 fdrive_t *d = &pThis->drives[i]; 2411 2420 2412 SSMR3GetMem(pSSM, &d->Led, sizeof(d->Led)); 2413 SSMR3GetU32(pSSM, &val32); 2421 pHlp->pfnSSMGetMem(pSSM, &d->Led, sizeof(d->Led)); 2422 rc = pHlp->pfnSSMGetU32(pSSM, &val32); 2423 AssertRCReturn(rc, rc); 2414 2424 d->drive = (fdrive_type_t)val32; 2415 SSMR3GetU8(pSSM, &d->dsk_chg);2416 SSMR3GetU8(pSSM, &d->perpendicular);2417 SSMR3GetU8(pSSM, &d->head);2418 SSMR3GetU8(pSSM, &d->track);2419 SSMR3GetU8(pSSM, &d->sect);2425 pHlp->pfnSSMGetU8(pSSM, &d->dsk_chg); 2426 pHlp->pfnSSMGetU8(pSSM, &d->perpendicular); 2427 pHlp->pfnSSMGetU8(pSSM, &d->head); 2428 pHlp->pfnSSMGetU8(pSSM, &d->track); 2429 pHlp->pfnSSMGetU8(pSSM, &d->sect); 2420 2430 } 2421 2431 } 2422 return TMR3TimerLoad 2432 return TMR3TimerLoad(pThis->result_timer, pSSM); 2423 2433 } 2424 2434 … … 2681 2691 static DECLCALLBACK(int) fdcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 2682 2692 { 2693 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 2694 fdctrl_t *pThis = PDMDEVINS_2_DATA(pDevIns, fdctrl_t *); 2695 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 2696 int rc; 2697 2683 2698 RT_NOREF(iInstance); 2684 fdctrl_t *pThis = PDMDEVINS_2_DATA(pDevIns, fdctrl_t *);2685 int rc;2686 unsigned i, j;2687 int ii;2688 bool mem_mapped;2689 uint16_t io_base;2690 uint8_t irq_lvl, dma_chann;2691 PPDMIBASE pBase;2692 2693 2699 Assert(iInstance == 0); 2694 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);2695 2700 2696 2701 /* 2697 2702 * Validate configuration. 2698 2703 */ 2699 if (!CFGMR3AreValuesValid(pCfg, "IRQ\0DMA\0MemMapped\0IOBase\0")) 2700 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES; 2704 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IRQ|DMA|MemMapped|IOBase", ""); 2701 2705 2702 2706 /* 2703 2707 * Read the configuration. 2704 2708 */ 2705 rc = CFGMR3QueryU8Def(pCfg, "IRQ", &irq_lvl, 6);2709 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IRQ", &pThis->irq_lvl, 6); 2706 2710 AssertMsgRCReturn(rc, ("Configuration error: Failed to read U8 IRQ, rc=%Rrc\n", rc), rc); 2707 2711 2708 rc = CFGMR3QueryU8Def(pCfg, "DMA", &dma_chann, 2);2712 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DMA", &pThis->dma_chann, 2); 2709 2713 AssertMsgRCReturn(rc, ("Configuration error: Failed to read U8 DMA, rc=%Rrc\n", rc), rc); 2710 2714 2711 rc = CFGMR3QueryU16Def(pCfg, "IOBase", &io_base, 0x3f0);2715 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "IOBase", &pThis->io_base, 0x3f0); 2712 2716 AssertMsgRCReturn(rc, ("Configuration error: Failed to read U16 IOBase, rc=%Rrc\n", rc), rc); 2713 2717 2714 rc = CFGMR3QueryBoolDef(pCfg, "MemMapped", &mem_mapped, false); 2718 bool fMemMapped; 2719 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "MemMapped", &fMemMapped, false); 2715 2720 AssertMsgRCReturn(rc, ("Configuration error: Failed to read bool value MemMapped rc=%Rrc\n", rc), rc); 2716 2721 … … 2718 2723 * Initialize data. 2719 2724 */ 2720 LogFlow(("fdcConstruct: irq_lvl=%d dma_chann=%d io_base=%#x\n", irq_lvl, dma_chann,io_base));2725 LogFlow(("fdcConstruct: irq_lvl=%d dma_chann=%d io_base=%#x\n", pThis->irq_lvl, pThis->dma_chann, pThis->io_base)); 2721 2726 pThis->pDevIns = pDevIns; 2722 2727 pThis->version = 0x90; /* Intel 82078 controller */ 2723 pThis->irq_lvl = irq_lvl;2724 pThis->dma_chann = dma_chann;2725 pThis->io_base = io_base;2726 2728 pThis->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2727 2729 pThis->num_floppies = MAX_FD; 2728 2730 2729 2731 /* Fill 'command_to_handler' lookup table */ 2730 for (i i = RT_ELEMENTS(handlers) - 1; ii >= 0; ii--)2731 for ( j = 0; j < sizeof(command_to_handler); j++)2732 for (int ii = RT_ELEMENTS(handlers) - 1; ii >= 0; ii--) 2733 for (unsigned j = 0; j < sizeof(command_to_handler); j++) 2732 2734 if ((j & handlers[ii].mask) == handlers[ii].value) 2733 2735 command_to_handler[j] = ii; … … 2736 2738 pThis->ILeds.pfnQueryStatusLed = fdcStatusQueryStatusLed; 2737 2739 2738 for ( i = 0; i < RT_ELEMENTS(pThis->drives); ++i)2740 for (unsigned i = 0; i < RT_ELEMENTS(pThis->drives); ++i) 2739 2741 { 2740 2742 fdrive_t *pDrv = &pThis->drives[i]; … … 2764 2766 if (pThis->dma_chann != 0xff) 2765 2767 { 2766 rc = PDMDevHlpDMARegister(pDevIns, dma_chann, &fdctrl_transfer_handler, pThis);2768 rc = PDMDevHlpDMARegister(pDevIns, pThis->dma_chann, &fdctrl_transfer_handler, pThis); 2767 2769 if (RT_FAILURE(rc)) 2768 2770 return rc; … … 2772 2774 * IO / MMIO. 2773 2775 */ 2774 if ( mem_mapped)2776 if (!fMemMapped) 2775 2777 { 2776 AssertMsgFailed(("Memory mapped floppy not support by now\n")); 2777 return VERR_NOT_SUPPORTED; 2778 } 2779 else 2780 { 2781 rc = PDMDevHlpIOPortRegister(pDevIns, io_base + 0x1, 5, pThis, 2778 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->io_base + 0x1, 5, pThis, 2782 2779 fdcIoPortWrite, fdcIoPortRead, NULL, NULL, "FDC#1"); 2783 2780 if (RT_FAILURE(rc)) 2784 2781 return rc; 2785 2782 2786 rc = PDMDevHlpIOPortRegister(pDevIns, io_base + 0x7, 1, pThis,2783 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->io_base + 0x7, 1, pThis, 2787 2784 fdcIoPortWrite, fdcIoPortRead, NULL, NULL, "FDC#2"); 2788 2785 if (RT_FAILURE(rc)) 2789 2786 return rc; 2790 2787 } 2788 else 2789 AssertMsgFailedReturn(("Memory mapped floppy not support by now\n"), VERR_NOT_SUPPORTED); 2791 2790 2792 2791 /* … … 2800 2799 * Attach the status port (optional). 2801 2800 */ 2801 PPDMIBASE pBase; 2802 2802 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBaseStatus, &pBase, "Status Port"); 2803 2803 if (RT_SUCCESS (rc)) 2804 2804 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS); 2805 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER) 2806 { 2807 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc)); 2808 return rc; 2809 } 2805 else 2806 AssertMsgReturn(rc == VERR_PDM_NO_ATTACHED_DRIVER, ("Failed to attach to status driver. rc=%Rrc\n", rc), rc); 2810 2807 2811 2808 /* 2812 2809 * Initialize drives. 2813 2810 */ 2814 for ( i = 0; i < RT_ELEMENTS(pThis->drives); i++)2811 for (unsigned i = 0; i < RT_ELEMENTS(pThis->drives); i++) 2815 2812 { 2816 2813 fdrive_t *pDrv = &pThis->drives[i]; … … 2826 2823 fdctrl_reset(pThis, 0); 2827 2824 2828 for ( i = 0; i < RT_ELEMENTS(pThis->drives); i++)2825 for (unsigned i = 0; i < RT_ELEMENTS(pThis->drives); i++) 2829 2826 fd_revalidate(&pThis->drives[i]); 2830 2827
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