Changeset 81799 in vbox for trunk/src/VBox/Devices/Storage
- Timestamp:
- Nov 12, 2019 12:47:35 PM (5 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Storage/DevFdc.cpp
r81795 r81799 49 49 #include <VBox/vmm/pdmdev.h> 50 50 #include <VBox/vmm/pdmstorageifs.h> 51 #include <VBox/AssertGuest.h> 51 52 #include <iprt/assert.h> 52 53 #include <iprt/string.h> … … 690 691 /** Status LUN: The Partner of ILeds. */ 691 692 PPDMILEDCONNECTORS pLedsConnector; 693 694 /** I/O ports: 0x3f1..0x3f5 */ 695 IOMIOPORTHANDLE hIoPorts1; 696 /** I/O port: 0x3f7 */ 697 IOMIOPORTHANDLE hIoPorts2; 692 698 }; 693 699 694 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 695 { 696 fdctrl_t *fdctrl = (fdctrl_t *)opaque; 700 static uint32_t fdctrl_read (fdctrl_t *fdctrl, uint32_t reg) 701 { 697 702 uint32_t retval; 698 703 … … 720 725 break; 721 726 default: 722 retval = (uint32_t)(-1);727 retval = UINT32_MAX; 723 728 break; 724 729 } … … 728 733 } 729 734 730 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 731 { 732 fdctrl_t *fdctrl = (fdctrl_t *)opaque; 733 735 static void fdctrl_write (fdctrl_t *fdctrl, uint32_t reg, uint32_t value) 736 { 734 737 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 735 738 … … 2182 2185 2183 2186 /** 2184 * @callback_method_impl{FNIOMIOPORT OUT}2187 * @callback_method_impl{FNIOMIOPORTNEWOUT, Handling 0x3f1..0x3f5 acceses.} 2185 2188 */ 2186 static DECLCALLBACK(int) fdcIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb) 2187 { 2188 RT_NOREF(pDevIns); 2189 static DECLCALLBACK(VBOXSTRICTRC) fdcIoPort1Write(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 2190 { 2191 RT_NOREF(pvUser); 2192 2189 2193 if (cb == 1) 2190 fdctrl_write (pvUser, uPort & 7, u32);2194 fdctrl_write(PDMDEVINS_2_DATA(pDevIns, fdctrl_t *), offPort + 1, u32); 2191 2195 else 2192 A ssertMsgFailed(("uPort=%#x cb=%d u32=%#x\n", uPort, cb, u32));2196 ASSERT_GUEST_MSG_FAILED(("offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32)); 2193 2197 return VINF_SUCCESS; 2194 2198 } … … 2196 2200 2197 2201 /** 2198 * @callback_method_impl{FNIOMIOPORT IN}2202 * @callback_method_impl{FNIOMIOPORTNEWIN, Handling 0x3f1..0x3f5 acceses.} 2199 2203 */ 2200 static DECLCALLBACK(int) fdcIoPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb) 2201 { 2202 RT_NOREF(pDevIns); 2204 static DECLCALLBACK(VBOXSTRICTRC) fdcIoPort1Read(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 2205 { 2206 RT_NOREF(pvUser); 2207 2203 2208 if (cb == 1) 2204 2209 { 2205 *pu32 = fdctrl_read (pvUser, uPort & 7); 2210 *pu32 = fdctrl_read(PDMDEVINS_2_DATA(pDevIns, fdctrl_t *), offPort + 1); 2211 return VINF_SUCCESS; 2212 } 2213 return VERR_IOM_IOPORT_UNUSED; 2214 } 2215 2216 2217 /** 2218 * @callback_method_impl{FNIOMIOPORTNEWOUT, Handling 0x3f7 access.} 2219 */ 2220 static DECLCALLBACK(VBOXSTRICTRC) fdcIoPort2Write(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 2221 { 2222 RT_NOREF(offPort, pvUser); 2223 Assert(offPort == 0); 2224 2225 if (cb == 1) 2226 fdctrl_write(PDMDEVINS_2_DATA(pDevIns, fdctrl_t *), 7, u32); 2227 else 2228 ASSERT_GUEST_MSG_FAILED(("offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32)); 2229 return VINF_SUCCESS; 2230 } 2231 2232 2233 /** 2234 * @callback_method_impl{FNIOMIOPORTNEWIN, Handling 0x3f7 access.} 2235 */ 2236 static DECLCALLBACK(VBOXSTRICTRC) fdcIoPort2Read(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 2237 { 2238 RT_NOREF(pvUser, offPort); 2239 Assert(offPort == 0); 2240 2241 if (cb == 1) 2242 { 2243 *pu32 = fdctrl_read(PDMDEVINS_2_DATA(pDevIns, fdctrl_t *), 7); 2206 2244 return VINF_SUCCESS; 2207 2245 } … … 2756 2794 /* 2757 2795 * IO / MMIO. 2796 * 2797 * We must skip I/O port 0x3f6 as it is the ATA alternate status register. 2798 * Why we skip registering status register A, though, isn't as clear. 2758 2799 */ 2759 2800 if (!fMemMapped) 2760 2801 { 2761 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->io_base + 0x1, 5, pThis, 2762 fdcIoPortWrite, fdcIoPortRead, NULL, NULL, "FDC#1"); 2763 if (RT_FAILURE(rc)) 2764 return rc; 2765 2766 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->io_base + 0x7, 1, pThis, 2767 fdcIoPortWrite, fdcIoPortRead, NULL, NULL, "FDC#2"); 2768 if (RT_FAILURE(rc)) 2769 return rc; 2802 static const IOMIOPORTDESC s_aDescs[] = 2803 { 2804 { "SRA", NULL, "Status register A", NULL }, 2805 { "SRB", NULL, "Status register B", NULL }, 2806 { "DOR", "DOR", "Digital output register", "Digital output register"}, 2807 { "TDR", "TDR", "Tape driver register", "Tape driver register"}, 2808 { "MSR", "DSR", "Main status register", "Datarate select register" }, 2809 { "FIFO", "FIFO", "Data FIFO", "Data FIFO" }, 2810 { "ATA", "ATA", NULL, NULL }, 2811 { "DIR", "CCR", "Digital input register", "Configuration control register"}, 2812 { NULL, NULL, NULL, NULL } 2813 }; 2814 2815 /* 0x3f1..0x3f5 */ 2816 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, pThis->io_base + 0x1, 5, fdcIoPort1Write, fdcIoPort1Read, 2817 "FDC#1", &s_aDescs[1], &pThis->hIoPorts1); 2818 AssertRCReturn(rc, rc); 2819 2820 /* 0x3f7 */ 2821 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, pThis->io_base + 0x7, 1, fdcIoPort2Write, fdcIoPort2Read, 2822 "FDC#2", &s_aDescs[7], &pThis->hIoPorts2); 2823 AssertRCReturn(rc, rc); 2770 2824 } 2771 2825 else … … 2816 2870 /* .uReserved0 = */ 0, 2817 2871 /* .szName = */ "i82078", 2818 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS ,2872 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_NEW_STYLE, 2819 2873 /* .fClass = */ PDM_DEVREG_CLASS_STORAGE, 2820 2874 /* .cMaxInstances = */ 1,
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