Changeset 81801 in vbox
- Timestamp:
- Nov 12, 2019 1:47:58 PM (5 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Storage/DevATA.cpp
r81765 r81801 538 538 uint8_t Alignment3[1]; /**< Explicit padding of the 1 byte gap. */ 539 539 /** Magic delay before triggering interrupts in DMA mode. */ 540 uint32_t DelayIRQMillies;540 uint32_t msDelayIRQ; 541 541 /** The event semaphore the thread is waiting on during suspended I/O. */ 542 542 RTSEMEVENT SuspendIOSem; … … 3955 3955 s->iLUN, s->uATARegNSector, s->uATARegSelect & 0x0f)); 3956 3956 ataR3LockLeave(pCtl); 3957 RTThreadSleep(pCtl-> DelayIRQMillies);3957 RTThreadSleep(pCtl->msDelayIRQ); 3958 3958 ataR3LockEnter(pCtl); 3959 3959 ataR3CmdOK(s, ATA_STAT_SEEK); … … 3969 3969 LogFlowFunc(("\n")); 3970 3970 ataR3LockLeave(pCtl); 3971 RTThreadSleep(pCtl-> DelayIRQMillies);3971 RTThreadSleep(pCtl->msDelayIRQ); 3972 3972 ataR3LockEnter(pCtl); 3973 3973 ataR3CmdOK(s, ATA_STAT_SEEK); … … 5759 5759 if ( iOriginalSourceSink == ATAFN_SS_WRITE_SECTORS 5760 5760 && s->cbTotalTransfer == 0 5761 && pCtl-> DelayIRQMillies)5761 && pCtl->msDelayIRQ) 5762 5762 { 5763 5763 /* Delay IRQ for writing. Required to get the Win2K … … 5767 5767 Log(("%s: delay IRQ hack\n", __FUNCTION__)); 5768 5768 ataR3LockLeave(pCtl); 5769 RTThreadSleep(pCtl-> DelayIRQMillies);5769 RTThreadSleep(pCtl->msDelayIRQ); 5770 5770 ataR3LockEnter(pCtl); 5771 5771 } … … 7388 7388 static DECLCALLBACK(int) ataR3Destruct(PPDMDEVINS pDevIns) 7389 7389 { 7390 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); 7390 7391 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7391 7392 int rc; 7392 7393 7393 7394 Log(("ataR3Destruct\n")); 7394 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);7395 7395 7396 7396 /* … … 7480 7480 char szType[20]; 7481 7481 7482 int rc = CFGMR3QueryStringDef(pCfg, "Type", &szType[0], sizeof(szType), "PIIX4");7482 int rc = pDevIns->pHlpR3->pfnCFGMQueryStringDef(pCfg, "Type", &szType[0], sizeof(szType), "PIIX4"); 7483 7483 if (RT_FAILURE(rc)) 7484 7484 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, … … 7505 7505 static DECLCALLBACK(int) ataR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 7506 7506 { 7507 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 7507 7508 PCIATAState *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *); 7509 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 7508 7510 PPDMIBASE pBase; 7509 7511 int rc; 7510 bool fRCEnabled; 7511 bool fR0Enabled; 7512 uint32_t DelayIRQMillies; 7512 uint32_t msDelayIRQ; 7513 7513 7514 7514 Assert(iInstance == 0); 7515 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);7516 7515 7517 7516 /* … … 7528 7527 * Validate and read configuration. 7529 7528 */ 7530 if (!CFGMR3AreValuesValid(pCfg, 7531 "GCEnabled\0" 7532 "R0Enabled\0" 7533 "IRQDelay\0" 7534 "Type\0") 7535 /** @todo || invalid keys */) 7536 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, 7537 N_("PIIX3 configuration error: unknown option specified")); 7538 7539 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true); 7529 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IRQDelay|Type", ""); 7530 7531 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IRQDelay", &msDelayIRQ, 0); 7540 7532 if (RT_FAILURE(rc)) 7541 return PDMDEV_SET_ERROR(pDevIns, rc, 7542 N_("PIIX3 configuration error: failed to read GCEnabled as boolean")); 7543 Log(("%s: fRCEnabled=%d\n", __FUNCTION__, fRCEnabled)); 7544 7545 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true); 7546 if (RT_FAILURE(rc)) 7547 return PDMDEV_SET_ERROR(pDevIns, rc, 7548 N_("PIIX3 configuration error: failed to read R0Enabled as boolean")); 7549 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled)); 7550 7551 rc = CFGMR3QueryU32Def(pCfg, "IRQDelay", &DelayIRQMillies, 0); 7552 if (RT_FAILURE(rc)) 7553 return PDMDEV_SET_ERROR(pDevIns, rc, 7554 N_("PIIX3 configuration error: failed to read IRQDelay as integer")); 7555 Log(("%s: DelayIRQMillies=%d\n", __FUNCTION__, DelayIRQMillies)); 7556 Assert(DelayIRQMillies < 50); 7533 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 configuration error: failed to read IRQDelay as integer")); 7534 Log(("%s: msDelayIRQ=%d\n", __FUNCTION__, msDelayIRQ)); 7535 Assert(msDelayIRQ < 50); 7557 7536 7558 7537 CHIPSET enmChipset = CHIPSET_PIIX3; … … 7578 7557 * as it explicitly checks for PCI id for IDE controllers. 7579 7558 */ 7580 switch ( pThis->u8Type)7559 switch (enmChipset) 7581 7560 { 7582 7561 case CHIPSET_ICH6: … … 7610 7589 break; 7611 7590 default: 7612 AssertMsgFailed(("Unsupported IDE chipset type: %d\n", pThis->u8Type));7591 AssertMsgFailed(("Unsupported IDE chipset type: %d\n", enmChipset)); 7613 7592 } 7614 7593 … … 7632 7611 7633 7612 pThis->pDevIns = pDevIns; 7634 pThis->fRCEnabled = fRCEnabled;7635 pThis->fR0Enabled = fR0Enabled;7613 pThis->fRCEnabled = pDevIns->fRCEnabled; 7614 pThis->fR0Enabled = pDevIns->fR0Enabled; 7636 7615 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++) 7637 7616 { … … 7639 7618 pThis->aCts[i].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 7640 7619 pThis->aCts[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 7641 pThis->aCts[i]. DelayIRQMillies = (uint32_t)DelayIRQMillies;7620 pThis->aCts[i].msDelayIRQ = msDelayIRQ; 7642 7621 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++) 7643 7622 { … … 7836 7815 7837 7816 /* Get user config if present using defaults otherwise. */ 7838 PCFGMNODE pCfgNode = CFGMR3GetChild(pCfg, s_apszCFGMKeys[i][j]);7839 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pIf->szSerialNumber, sizeof(pIf->szSerialNumber),7840 szSerial);7817 PCFGMNODE pCfgNode = pHlp->pfnCFGMGetChild(pCfg, s_apszCFGMKeys[i][j]); 7818 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "SerialNumber", pIf->szSerialNumber, sizeof(pIf->szSerialNumber), 7819 szSerial); 7841 7820 if (RT_FAILURE(rc)) 7842 7821 { … … 7848 7827 } 7849 7828 7850 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pIf->szFirmwareRevision, sizeof(pIf->szFirmwareRevision),7851 "1.0");7829 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "FirmwareRevision", pIf->szFirmwareRevision, 7830 sizeof(pIf->szFirmwareRevision), "1.0"); 7852 7831 if (RT_FAILURE(rc)) 7853 7832 { … … 7859 7838 } 7860 7839 7861 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pIf->szModelNumber, sizeof(pIf->szModelNumber),7862 pIf->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");7840 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ModelNumber", pIf->szModelNumber, sizeof(pIf->szModelNumber), 7841 pIf->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK"); 7863 7842 if (RT_FAILURE(rc)) 7864 7843 { … … 7873 7852 if (pIf->fATAPI) 7874 7853 { 7875 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pIf->szInquiryVendorId, sizeof(pIf->szInquiryVendorId),7876 "VBOX");7854 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ATAPIVendorId", pIf->szInquiryVendorId, 7855 sizeof(pIf->szInquiryVendorId), "VBOX"); 7877 7856 if (RT_FAILURE(rc)) 7878 7857 { … … 7884 7863 } 7885 7864 7886 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pIf->szInquiryProductId, sizeof(pIf->szInquiryProductId),7887 "CD-ROM");7865 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ATAPIProductId", pIf->szInquiryProductId, 7866 sizeof(pIf->szInquiryProductId), "CD-ROM"); 7888 7867 if (RT_FAILURE(rc)) 7889 7868 { … … 7895 7874 } 7896 7875 7897 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pIf->szInquiryRevision, sizeof(pIf->szInquiryRevision),7898 "1.0");7876 rc = pHlp->pfnCFGMQueryStringDef(pCfgNode, "ATAPIRevision", pIf->szInquiryRevision, 7877 sizeof(pIf->szInquiryRevision), "1.0"); 7899 7878 if (RT_FAILURE(rc)) 7900 7879 { … … 7906 7885 } 7907 7886 7908 rc = CFGMR3QueryBoolDef(pCfgNode, "OverwriteInquiry", &pIf->fOverwriteInquiry, true);7887 rc = pHlp->pfnCFGMQueryBoolDef(pCfgNode, "OverwriteInquiry", &pIf->fOverwriteInquiry, true); 7909 7888 if (RT_FAILURE(rc)) 7910 7889 return PDMDEV_SET_ERROR(pDevIns, rc, … … 7958 7937 AssertLogRelRCReturn(rc, rc); 7959 7938 7960 if ( fRCEnabled)7939 if (pDevIns->fRCEnabled) 7961 7940 { 7962 7941 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i, … … 7968 7947 } 7969 7948 7970 if ( fR0Enabled)7949 if (pDevIns->fR0Enabled) 7971 7950 { 7972 7951 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i, … … 7989 7968 7990 7969 AssertLogRelRCReturn(rc, rc); 7991 if ( fRCEnabled)7970 if (pDevIns->fRCEnabled) 7992 7971 { 7993 7972 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTGCPTR)i, … … 8000 7979 } 8001 7980 8002 if ( fR0Enabled)7981 if (pDevIns->fR0Enabled) 8003 7982 { 8004 7983 #if 0 … … 8021 8000 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers")); 8022 8001 8023 if ( fRCEnabled)8002 if (pDevIns->fRCEnabled) 8024 8003 { 8025 8004 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i, … … 8028 8007 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (GC)")); 8029 8008 } 8030 if ( fR0Enabled)8009 if (pDevIns->fR0Enabled) 8031 8010 { 8032 8011 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTR0PTR)i,
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