Changeset 81809 in vbox
- Timestamp:
- Nov 12, 2019 3:40:09 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 134600
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r81808 r81809 26 26 #include <VBox/vmm/pdmstorageifs.h> 27 27 #include <VBox/vmm/pdmcritsect.h> 28 #include <VBox/AssertGuest.h> 28 29 #include <VBox/scsi.h> 29 30 #include <iprt/asm.h> … … 342 343 /** Whether RC is enabled. */ 343 344 bool fGCEnabled; 344 /** Base address of the I/O ports. */ 345 RTIOPORT IOPortBase; 345 bool afPadding[2]; 346 346 347 347 /** Base address of the memory mapping. */ … … 487 487 #endif 488 488 489 /** ISA compatibility I/O ports. */ 490 IOMIOPORTHANDLE hIoPortsIsa; 491 /** PCI Region \#0: I/O ports. */ 492 IOMIOPORTHANDLE hIoPortsPci; 489 493 } BUSLOGIC; 490 494 /** Pointer to the shared BusLogic device emulation state. */ … … 1009 1013 *********************************************************************************************************************************/ 1010 1014 #ifdef IN_RING3 1011 static int buslogicR3RegisterISARange(P BUSLOGIC pBusLogic, uint8_t uBaseCode);1015 static int buslogicR3RegisterISARange(PPDMDEVINS pDevIns, PBUSLOGIC pBusLogic, uint8_t uBaseCode); 1012 1016 #endif 1013 1017 … … 1148 1152 /* Guest-initiated HBA reset does not affect ISA port I/O. */ 1149 1153 if (fResetIO) 1150 { 1151 buslogicR3RegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode); 1152 } 1154 buslogicR3RegisterISARange(pBusLogic->CTX_SUFF(pDevIns), pBusLogic, pBusLogic->uDefaultISABaseCode); 1153 1155 buslogicR3InitializeLocalRam(pBusLogic); 1154 1156 vboxscsiInitialize(&pBusLogic->VBoxSCSI); … … 1814 1816 * However, it is required for compatibility with old drivers. 1815 1817 */ 1816 #ifdef IN_RING3 1818 #ifdef IN_RING3 /* We can do this from ring-0 now, but we'd like to see the LogRel, so we keep going back to ring-3 anyway. */ 1817 1819 Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0])); 1818 buslogicR3RegisterISARange(pBusLogic , pBusLogic->aCommandBuffer[0]);1820 buslogicR3RegisterISARange(pBusLogic->CTX_SUFF(pDevIns), pBusLogic, pBusLogic->aCommandBuffer[0]); 1819 1821 pBusLogic->cbReplyParametersLeft = 0; 1820 1822 fSuppressIrq = true; … … 2660 2662 2661 2663 /** 2662 * Port I/O Handler for IN operations. 2663 * 2664 * @returns VBox status code. 2665 * 2666 * @param pDevIns The device instance. 2667 * @param pvUser User argument. 2668 * @param uPort Port number used for the IN operation. 2669 * @param pu32 Where to store the result. 2670 * @param cb Number of bytes read. 2671 */ 2672 PDMBOTHCBDECL(int) buslogicIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb) 2664 * @callback_method_impl{FNIOMIOPORTNEWIN} 2665 */ 2666 static DECLCALLBACK(VBOXSTRICTRC) 2667 buslogicIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 2673 2668 { 2674 2669 PBUSLOGIC pBusLogic = PDMDEVINS_2_DATA(pDevIns, PBUSLOGIC); 2675 unsigned iRegister = uPort % 4;2676 RT_NOREF _PV(pvUser); RT_NOREF_PV(cb);2677 2678 A ssert(cb == 1);2670 unsigned iRegister = offPort % 4; 2671 RT_NOREF(pvUser, cb); 2672 2673 ASSERT_GUEST(cb == 1); 2679 2674 2680 2675 return buslogicRegisterRead(pBusLogic, iRegister, pu32); … … 2682 2677 2683 2678 /** 2684 * Port I/O Handler for OUT operations. 2685 * 2686 * @returns VBox status code. 2687 * 2688 * @param pDevIns The device instance. 2689 * @param pvUser User argument. 2690 * @param uPort Port number used for the IN operation. 2691 * @param u32 The value to output. 2692 * @param cb The value size in bytes. 2693 */ 2694 PDMBOTHCBDECL(int) buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb) 2679 * @callback_method_impl{FNIOMIOPORTNEWOUT} 2680 */ 2681 static DECLCALLBACK(VBOXSTRICTRC) 2682 buslogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 2695 2683 { 2696 2684 PBUSLOGIC pBusLogic = PDMDEVINS_2_DATA(pDevIns, PBUSLOGIC); 2697 unsigned iRegister = uPort % 4; 2698 uint8_t uVal = (uint8_t)u32; 2699 RT_NOREF2(pvUser, cb); 2700 2701 Assert(cb == 1); 2702 2703 int rc = buslogicRegisterWrite(pDevIns, pBusLogic, iRegister, (uint8_t)uVal); 2704 2705 Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x uPort=%#x rc=%Rrc\n", 2706 pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, uPort, rc)); 2685 unsigned iRegister = offPort % 4; 2686 RT_NOREF(pvUser, cb); 2687 2688 ASSERT_GUEST(cb == 1); 2689 2690 int rc = buslogicRegisterWrite(pDevIns, pBusLogic, iRegister, (uint8_t)u32); 2691 2692 Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x offPort=%#x rc=%Rrc\n", 2693 pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, offPort, rc)); 2707 2694 2708 2695 return rc; … … 2891 2878 * 2892 2879 * @returns nothing. 2880 * @param pDevIns The device instance. 2893 2881 * @param pBusLogic Pointer to the BusLogic device instance. 2894 2882 * @param uBaseCode Encoded ISA I/O base; only low 3 bits are used. 2895 2883 */ 2896 static int buslogicR3RegisterISARange(P BUSLOGIC pBusLogic, uint8_t uBaseCode)2884 static int buslogicR3RegisterISARange(PPDMDEVINS pDevIns, PBUSLOGIC pBusLogic, uint8_t uBaseCode) 2897 2885 { 2898 2886 uint8_t uCode = uBaseCode & MAX_ISA_BASE; … … 2902 2890 LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase)); 2903 2891 2904 /* Check if the same port range is already registered. */2892 /* Check if the same port range actually changed. */ 2905 2893 if (uNewBase != pBusLogic->IOISABase) 2906 2894 { 2907 /* Un register the old range, if any. */2895 /* Unmap the old range, if necessary. */ 2908 2896 if (pBusLogic->IOISABase) 2909 rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4); 2910 2897 { 2898 rc = PDMDevHlpIoPortUnmap(pDevIns, pBusLogic->hIoPortsIsa); 2899 AssertRC(rc); 2900 } 2911 2901 if (RT_SUCCESS(rc)) 2912 2902 { … … 2917 2907 { 2918 2908 /* Register the new range if requested. */ 2919 rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL, 2920 buslogicIOPortWrite, buslogicIOPortRead, 2921 NULL, NULL, 2922 "BusLogic ISA"); 2909 rc = PDMDevHlpIoPortMap(pDevIns, pBusLogic->hIoPortsIsa, uNewBase); 2923 2910 if (RT_SUCCESS(rc)) 2924 2911 { … … 2988 2975 2989 2976 pThis->MMIOBase = GCPhysAddress; 2990 }2991 else if (enmType == PCI_ADDRESS_SPACE_IO)2992 {2993 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,2994 NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");2995 if (RT_FAILURE(rc))2996 return rc;2997 2998 if (pThis->fR0Enabled)2999 {3000 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,3001 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");3002 if (RT_FAILURE(rc))3003 return rc;3004 }3005 3006 if (pThis->fGCEnabled)3007 {3008 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,3009 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");3010 if (RT_FAILURE(rc))3011 return rc;3012 }3013 3014 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;3015 2977 } 3016 2978 else … … 3527 3489 PBUSLOGIC pThis = PDMDEVINS_2_DATA(pDevIns, PBUSLOGIC); 3528 3490 3529 buslogicR3RegisterISARange(p This, pThis->uISABaseCode);3491 buslogicR3RegisterISARange(pDevIns, pThis, pThis->uISABaseCode); 3530 3492 3531 3493 /* Kick of any requests we might need to redo. */ … … 3827 3789 pThis->uIsaIrq); 3828 3790 else 3829 pHlp->pfnPrintf(pHlp, "PCI I/O=% RTiopISA I/O=%RTiop MMIO=%RGp IRQ=%u ",3830 pThis->IOPortBase, pThis->IOISABase, pThis->MMIOBase,3791 pHlp->pfnPrintf(pHlp, "PCI I/O=%04x ISA I/O=%RTiop MMIO=%RGp IRQ=%u ", 3792 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortsPci), pThis->IOISABase, pThis->MMIOBase, 3831 3793 PCIDevGetInterruptLine(pDevIns->apPciDevs[0])); 3832 3794 pHlp->pfnPrintf(pHlp, "GC=%RTbool R0=%RTbool\n", … … 4277 4239 { 4278 4240 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev); 4279 if (RT_FAILURE(rc))4280 return rc; 4281 4282 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 32, PCI_ADDRESS_SPACE_IO, buslogicR3MmioMap);4283 if (RT_FAILURE(rc))4284 return rc;4241 AssertRCReturn(rc, rc); 4242 4243 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 32 /*cPorts*/, 4244 buslogicIOPortWrite, buslogicIOPortRead, NULL /*pvUser*/, 4245 "BusLogic PCI", NULL /*paExtDescs*/, &pThis->hIoPortsPci); 4246 AssertRCReturn(rc, rc); 4285 4247 4286 4248 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap); … … 4301 4263 4302 4264 /* Set up the compatibility I/O range. */ 4303 rc = buslogicR3RegisterISARange(pThis, pThis->uDefaultISABaseCode); 4265 rc = PDMDevHlpIoPortCreate(pDevIns, 4 /*cPorts*/, NULL /*pPciDev*/, UINT32_MAX /*iPciRegion*/, 4266 buslogicIOPortWrite, buslogicIOPortRead, NULL /*pvUser*/, 4267 "BusLogic ISA", NULL /*paExtDescs*/, &pThis->hIoPortsIsa); 4268 AssertRCReturn(rc, rc); 4269 4270 rc = buslogicR3RegisterISARange(pDevIns, pThis, pThis->uDefaultISABaseCode); 4304 4271 if (RT_FAILURE(rc)) 4305 4272 return PDMDEV_SET_ERROR(pDevIns, rc, N_("BusLogic cannot register ISA I/O handlers")); … … 4427 4394 } 4428 4395 4429 #endif /* IN_RING3 */ 4396 #else /* !IN_RING3 */ 4397 4398 /** 4399 * @callback_method_impl{PDMDEVREGR0,pfnConstruct} 4400 */ 4401 static DECLCALLBACK(int) buslogicRZConstruct(PPDMDEVINS pDevIns) 4402 { 4403 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 4404 PBUSLOGIC pThis = PDMDEVINS_2_DATA(pDevIns, PBUSLOGIC); 4405 4406 int rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsPci, buslogicIOPortWrite, buslogicIOPortRead, NULL /*pvUser*/); 4407 AssertRCReturn(rc, rc); 4408 4409 return VINF_SUCCESS; 4410 } 4411 4412 4413 #endif /* !IN_RING3 */ 4430 4414 4431 4415 /** … … 4476 4460 #elif defined(IN_RING0) 4477 4461 /* .pfnEarlyConstruct = */ NULL, 4478 /* .pfnConstruct = */ NULL,4462 /* .pfnConstruct = */ buslogicRZConstruct, 4479 4463 /* .pfnDestruct = */ NULL, 4480 4464 /* .pfnFinalDestruct = */ NULL, … … 4489 4473 /* .pfnReserved7 = */ NULL, 4490 4474 #elif defined(IN_RC) 4491 /* .pfnConstruct = */ NULL,4475 /* .pfnConstruct = */ buslogicRZConstruct, 4492 4476 /* .pfnReserved0 = */ NULL, 4493 4477 /* .pfnReserved1 = */ NULL,
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