VirtualBox

Changeset 81810 in vbox


Ignore:
Timestamp:
Nov 12, 2019 3:46:40 PM (5 years ago)
Author:
vboxsync
Message:

DevBusLogic.cpp: Converting it to the new PDM device style - MMIO (stubs). bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Storage/DevBusLogic.cpp

    r81809 r81810  
    345345    bool                            afPadding[2];
    346346
    347     /** Base address of the memory mapping. */
    348     RTGCPHYS                        MMIOBase;
    349 
    350347    /** Status register - Readonly. */
    351348    volatile uint8_t                regStatus;
     
    491488    /** PCI Region \#0: I/O ports. */
    492489    IOMIOPORTHANDLE                 hIoPortsPci;
     490    /** PCI Region \#1: MMIO (32 bytes, but probably rounded up to 4KB). */
     491    IOMMMIOHANDLE                   hMmio;
    493492} BUSLOGIC;
    494493/** Pointer to the shared BusLogic device emulation state. */
     
    26222621
    26232622/**
    2624  * Memory mapped I/O Handler for read operations.
    2625  *
    2626  * @returns VBox status code.
    2627  *
    2628  * @param   pDevIns     The device instance.
    2629  * @param   pvUser      User argument.
    2630  * @param   GCPhysAddr  Physical address (in GC) where the read starts.
    2631  * @param   pv          Where to store the result.
    2632  * @param   cb          Number of bytes read.
    2633  */
    2634 PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
    2635 {
    2636     RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
     2623 * @callback_method_impl{FNIOMMMIONEWREAD}
     2624 */
     2625static DECLCALLBACK(VBOXSTRICTRC) buslogicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
     2626{
     2627    RT_NOREF(pDevIns, pvUser, off, pv, cb);
    26372628
    26382629    /* the linux driver does not make use of the MMIO area. */
    2639     AssertMsgFailed(("MMIO Read\n"));
     2630    ASSERT_GUEST_MSG_FAILED(("MMIO Read: %RGp LB %u\n", off, cb));
    26402631    return VINF_SUCCESS;
    26412632}
    26422633
    26432634/**
    2644  * Memory mapped I/O Handler for write operations.
    2645  *
    2646  * @returns VBox status code.
    2647  *
    2648  * @param   pDevIns     The device instance.
    2649  * @param   pvUser      User argument.
    2650  * @param   GCPhysAddr  Physical address (in GC) where the read starts.
    2651  * @param   pv          Where to fetch the result.
    2652  * @param   cb          Number of bytes to write.
    2653  */
    2654 PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
    2655 {
    2656     RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb);
     2635 * @callback_method_impl{FNIOMMMIONEWWRITE}
     2636 */
     2637static DECLCALLBACK(VBOXSTRICTRC) buslogicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
     2638{
     2639    RT_NOREF(pDevIns, pvUser, off, pv, cb);
    26572640
    26582641    /* the linux driver does not make use of the MMIO area. */
    2659     AssertMsgFailed(("MMIO Write\n"));
     2642    ASSERT_GUEST_MSG_FAILED(("MMIO Write: %RGp LB %u: %.*Rhxs\n", off, cb, cb, pv));
    26602643    return VINF_SUCCESS;
    26612644}
     
    29332916}
    29342917
    2935 
    2936 /**
    2937  * @callback_method_impl{FNPCIIOREGIONMAP}
    2938  */
    2939 static DECLCALLBACK(int) buslogicR3MmioMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
    2940                                            RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
    2941 {
    2942     PBUSLOGIC  pThis = PDMDEVINS_2_DATA(pDevIns, PBUSLOGIC);
    2943     int        rc    = VINF_SUCCESS;
    2944     RT_NOREF(pPciDev, iRegion);
    2945 
    2946     Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%RGp\n", __FUNCTION__, GCPhysAddress, cb));
    2947 
    2948     Assert(cb >= 32);
    2949     Assert(pPciDev == pDevIns->apPciDevs[0]);
    2950 
    2951     if (enmType == PCI_ADDRESS_SPACE_MEM)
    2952     {
    2953         /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
    2954         rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
    2955                                    IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
    2956                                    buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");
    2957         if (RT_FAILURE(rc))
    2958             return rc;
    2959 
    2960         if (pThis->fR0Enabled)
    2961         {
    2962             rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
    2963                                          "buslogicMMIOWrite", "buslogicMMIORead");
    2964             if (RT_FAILURE(rc))
    2965                 return rc;
    2966         }
    2967 
    2968         if (pThis->fGCEnabled)
    2969         {
    2970             rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
    2971                                          "buslogicMMIOWrite", "buslogicMMIORead");
    2972             if (RT_FAILURE(rc))
    2973                 return rc;
    2974         }
    2975 
    2976         pThis->MMIOBase = GCPhysAddress;
    2977     }
    2978     else
    2979         AssertMsgFailed(("Invalid enmType=%d\n", enmType));
    2980 
    2981     return rc;
    2982 }
    29832918
    29842919static int buslogicR3ReqComplete(PBUSLOGIC pThis, PBUSLOGICREQ pReq, int rcReq)
     
    37903725    else
    37913726        pHlp->pfnPrintf(pHlp, "PCI I/O=%04x ISA I/O=%RTiop MMIO=%RGp IRQ=%u ",
    3792                         PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortsPci), pThis->IOISABase, pThis->MMIOBase,
     3727                        PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortsPci), pThis->IOISABase,
     3728                        PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio),
    37933729                        PCIDevGetInterruptLine(pDevIns->apPciDevs[0]));
    37943730    pHlp->pfnPrintf(pHlp, "GC=%RTbool R0=%RTbool\n",
     
    42464182        AssertRCReturn(rc, rc);
    42474183
    4248         rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 32, PCI_ADDRESS_SPACE_MEM, buslogicR3MmioMap);
    4249         if (RT_FAILURE(rc))
    4250             return rc;
     4184        rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 1 /*iPciRegion*/, 32 /*cbRegion*/, PCI_ADDRESS_SPACE_MEM,
     4185                                            buslogicMMIOWrite, buslogicMMIORead, NULL /*pvUser*/,
     4186                                            IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
     4187                                            "BusLogic MMIO", &pThis->hMmio);
     4188        AssertRCReturn(rc, rc);
    42514189    }
    42524190
     
    44054343
    44064344    int rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsPci, buslogicIOPortWrite, buslogicIOPortRead, NULL /*pvUser*/);
     4345    AssertRCReturn(rc, rc);
     4346
     4347    rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, buslogicMMIOWrite, buslogicMMIORead, NULL /*pvUser*/);
    44074348    AssertRCReturn(rc, rc);
    44084349
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