VirtualBox

Changeset 81849 in vbox


Ignore:
Timestamp:
Nov 14, 2019 9:16:30 PM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
134643
Message:

DevATA: Be a little bit paranoid about indexing PCIATAState::aCts too. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Storage/DevATA.cpp

    r81848 r81849  
    50045004PDMBOTHCBDECL(int) ataIOPortWrite1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    50055005{
    5006     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    50075006    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    5008     PATACONTROLLER pCtl = &pThis->aCts[i];
     5007    PATACONTROLLER pCtl  = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    50095008    RT_NOREF1(Port);
    50105009
    5011     Assert(i < 2);
     5010    Assert((uintptr_t)pvUser < 2);
    50125011    Assert(Port == pCtl->IOPortBase1);
    50135012    Assert(cb == 2 || cb == 4); /* Writes to the data port may be 16-bit or 32-bit. */
     
    50745073PDMBOTHCBDECL(int) ataIOPortRead1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    50755074{
    5076     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    50775075    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    5078     PATACONTROLLER pCtl = &pThis->aCts[i];
     5076    PATACONTROLLER pCtl  = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    50795077    RT_NOREF1(Port);
    50805078
    5081     Assert(i < 2);
     5079    Assert((uintptr_t)pvUser < 2);
    50825080    Assert(Port == pCtl->IOPortBase1);
    50835081
     
    51625160                                         uint32_t *pcTransfers, unsigned cb)
    51635161{
    5164     uint32_t       i     = (uint32_t)(uintptr_t)pvUser;
    51655162    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    5166     PATACONTROLLER pCtl  = &pThis->aCts[i];
     5163    PATACONTROLLER pCtl  = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    51675164    RT_NOREF1(Port);
    51685165
    5169     Assert(i < 2);
     5166    Assert((uintptr_t)pvUser < 2);
    51705167    Assert(Port == pCtl->IOPortBase1);
    51715168    Assert(*pcTransfers > 0);
     
    52535250                                          uint32_t *pcTransfers, unsigned cb)
    52545251{
    5255     uint32_t       i     = (uint32_t)(uintptr_t)pvUser;
    52565252    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    5257     PATACONTROLLER pCtl  = &pThis->aCts[i];
     5253    PATACONTROLLER pCtl  = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    52585254    RT_NOREF1(Port);
    52595255
    5260     Assert(i < 2);
     5256    Assert((uintptr_t)pvUser < 2);
    52615257    Assert(Port == pCtl->IOPortBase1);
    52625258    Assert(*pcTransfers > 0);
     
    61516147PDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    61526148{
    6153     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    61546149    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6155     PATACONTROLLER pCtl = &pThis->aCts[i];
     6150    PATACONTROLLER pCtl  = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    61566151
    61576152    int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
     
    61846179PDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    61856180{
    6186     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    61876181    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6188     PATACONTROLLER pCtl = &pThis->aCts[i];
     6182    PATACONTROLLER pCtl  = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    61896183
    61906184    int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
     
    63566350PDMBOTHCBDECL(int) ataIOPortWriteEmptyBus(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    63576351{
    6358     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    63596352    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6360     PATACONTROLLER pCtl = &pThis->aCts[i];
     6353    PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    63616354#ifndef VBOX_LOG_ENABLED
    63626355    RT_NOREF(Port); RT_NOREF(cb); RT_NOREF(u32); RT_NOREF(pCtl);
    63636356#endif
    63646357
    6365     Assert(i < 2);
     6358    Assert((uintptr_t)pvUser < 2);
    63666359    Assert(!pCtl->aIfs[0].pDrvMedia && !pCtl->aIfs[1].pDrvMedia);
    63676360
     
    63786371PDMBOTHCBDECL(int) ataIOPortReadEmptyBus(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    63796372{
    6380     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    63816373    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6382     PATACONTROLLER pCtl = &pThis->aCts[i];
     6374    PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    63836375#ifndef VBOX_LOG_ENABLED
    63846376    RT_NOREF(Port); RT_NOREF(pCtl);
    63856377#endif
    63866378
    6387     Assert(i < 2);
     6379    Assert((uintptr_t)pvUser < 2);
    63886380    Assert(cb <= 4);
    63896381    Assert(!pCtl->aIfs[0].pDrvMedia && !pCtl->aIfs[1].pDrvMedia);
     
    64126404PDMBOTHCBDECL(int) ataIOPortWrite1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    64136405{
    6414     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    64156406    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6416     PATACONTROLLER pCtl = &pThis->aCts[i];
    6417 
    6418     Assert(i < 2);
     6407    PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
     6408
     6409    Assert((uintptr_t)pvUser < 2);
    64196410    Assert(Port != pCtl->IOPortBase1);
    64206411
     
    64436434PDMBOTHCBDECL(int) ataIOPortRead1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    64446435{
    6445     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    64466436    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6447     PATACONTROLLER pCtl = &pThis->aCts[i];
    6448 
    6449     Assert(i < 2);
     6437    PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
     6438
     6439    Assert((uintptr_t)pvUser < 2);
    64506440    Assert(Port != pCtl->IOPortBase1);
    64516441
     
    64816471PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    64826472{
    6483     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    64846473    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6485     PATACONTROLLER pCtl = &pThis->aCts[i];
     6474    PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    64866475    int rc;
    64876476
    6488     Assert(i < 2);
     6477    Assert((uintptr_t)pvUser < 2);
    64896478
    64906479    if (cb == 1)
     
    65126501PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    65136502{
    6514     uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    65156503    PCIATAState   *pThis = PDMDEVINS_2_DATA(pDevIns, PCIATAState *);
    6516     PATACONTROLLER pCtl = &pThis->aCts[i];
     6504    PATACONTROLLER pCtl = &pThis->aCts[(uintptr_t)pvUser % RT_ELEMENTS(pThis->aCts)];
    65176505    int            rc;
    65186506
    6519     Assert(i < 2);
     6507    Assert((uintptr_t)pvUser < 2);
    65206508
    65216509    if (cb == 1)
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