VirtualBox

Changeset 81938 in vbox for trunk/src/VBox/Devices


Ignore:
Timestamp:
Nov 18, 2019 12:14:05 PM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
134735
Message:

DevIoApic,PDM: Refactored the IOAPIC registration to be done directly for each context. Converted CFGM calls. Use default device prefix for statistics. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/PC/DevIoApic.cpp

    r81765 r81938  
    185185{
    186186    /** The device instance - R3 Ptr. */
    187     PPDMDEVINSR3            pDevInsR3;
     187    PPDMDEVINSR3                pDevInsR3;
    188188    /** The IOAPIC helpers - R3 Ptr. */
    189     PCPDMIOAPICHLPR3        pIoApicHlpR3;
     189    R3PTRTYPE(PCPDMIOAPICHLP)   pIoApicHlpR3;
    190190
    191191    /** The device instance - R0 Ptr. */
    192     PPDMDEVINSR0            pDevInsR0;
     192    PPDMDEVINSR0                pDevInsR0;
    193193    /** The IOAPIC helpers - R0 Ptr. */
    194     PCPDMIOAPICHLPR0        pIoApicHlpR0;
     194    R0PTRTYPE(PCPDMIOAPICHLP)   pIoApicHlpR0;
    195195
    196196    /** The device instance - RC Ptr. */
    197     PPDMDEVINSRC            pDevInsRC;
     197    PPDMDEVINSRC                pDevInsRC;
    198198    /** The IOAPIC helpers - RC Ptr. */
    199     PCPDMIOAPICHLPRC        pIoApicHlpRC;
     199    RCPTRTYPE(PCPDMIOAPICHLP)   pIoApicHlpRC;
    200200
    201201    /** The ID register. */
    … …  
    11361136
    11371137    pThis->pDevInsRC    = PDMDEVINS_2_RCPTR(pDevIns);
    1138     pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
     1138    pThis->pIoApicHlpRC += offDelta;
    11391139}
    11401140
    … …  
    11691169{
    11701170    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    1171     PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
     1171    PIOAPIC         pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
     1172    PCPDMDEVHLPR3   pHlp  = pDevIns->pHlpR3;
    11721173    LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
    11731174    Assert(iInstance == 0); RT_NOREF(iInstance);
    … …  
    11831184     * Validate and read the configuration.
    11841185     */
    1185     PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs|RZEnabled|ChipType", "");
     1186    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs|ChipType", "");
    11861187
    11871188    /* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
    11881189       upsets some guest which we haven't yet tested. */
    11891190    uint32_t cCpus;
    1190     int rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
     1191    int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
    11911192    if (RT_FAILURE(rc))
    11921193        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
    11931194    pThis->cCpus = (uint8_t)cCpus;
    11941195
    1195     bool fRZEnabled;
    1196     rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
    1197     if (RT_FAILURE(rc))
    1198         return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
    1199 
    12001196    char szChipType[16];
    1201     rc = CFGMR3QueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
     1197    rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
    12021198    if (RT_FAILURE(rc))
    12031199        return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
    … …  
    12351231    }
    12361232    else
    1237     {
    12381233        return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
    1239                                    N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"),
    1240                                    szChipType);
    1241     }
    1242     Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, fRZEnabled, szChipType));
     1234                                   N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
     1235    Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled | pDevIns->fRCEnabled, szChipType));
    12431236
    12441237    /*
    … …  
    12531246     */
    12541247    rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
    1255     if (RT_FAILURE(rc))
    1256         return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc);
     1248    AssertRCReturn(rc, rc);
    12571249# endif
    12581250
    … …  
    12611253     */
    12621254    PDMIOAPICREG IoApicReg;
    1263     RT_ZERO(IoApicReg);
    12641255    IoApicReg.u32Version   = PDM_IOAPICREG_VERSION;
    1265     IoApicReg.pfnSetIrqR3  = ioapicSetIrq;
    1266     IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
    1267     IoApicReg.pfnSetEoiR3  = ioapicSetEoi;
    1268     if (fRZEnabled)
    1269     {
    1270         IoApicReg.pszSetIrqRC  = "ioapicSetIrq";
    1271         IoApicReg.pszSetIrqR0  = "ioapicSetIrq";
    1272 
    1273         IoApicReg.pszSendMsiRC = "ioapicSendMsi";
    1274         IoApicReg.pszSendMsiR0 = "ioapicSendMsi";
    1275 
    1276         IoApicReg.pszSetEoiRC = "ioapicSetEoi";
    1277         IoApicReg.pszSetEoiR0 = "ioapicSetEoi";
    1278     }
    1279     rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
    1280     if (RT_FAILURE(rc))
    1281     {
    1282         AssertMsgFailed(("IOAPIC: PDMDevHlpIOAPICRegister failed! rc=%Rrc\n", rc));
    1283         return rc;
    1284     }
     1256    IoApicReg.pfnSetIrq    = ioapicSetIrq;
     1257    IoApicReg.pfnSendMsi   = ioapicSendMsi;
     1258    IoApicReg.pfnSetEoi    = ioapicSetEoi;
     1259    IoApicReg.u32TheEnd    = PDM_IOAPICREG_VERSION;
     1260    rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
     1261    AssertRCReturn(rc, rc);
    12851262
    12861263    /*
    … …  
    12901267                               IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
    12911268                               "I/O APIC");
    1292     if (RT_SUCCESS(rc))
     1269    AssertRCReturn(rc, rc);
     1270    if (pDevIns->fR0Enabled | pDevIns->fRCEnabled)
    12931271    {
    1294         if (fRZEnabled)
    1295         {
    1296             pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
    1297             rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
    1298                                          "ioapicMmioWrite", "ioapicMmioRead");
    1299             AssertRCReturn(rc, rc);
    1300 
    1301             pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
    1302             rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
    1303                                          "ioapicMmioWrite", "ioapicMmioRead");
    1304             AssertRCReturn(rc, rc);
    1305         }
    1306     }
    1307     else
    1308     {
    1309         LogRel(("IOAPIC: PDMDevHlpMMIORegister failed! rc=%Rrc\n", rc));
    1310         return rc;
     1272        rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
     1273                                     "ioapicMmioWrite", "ioapicMmioRead");
     1274        AssertRCReturn(rc, rc);
     1275
     1276        rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
     1277                                     "ioapicMmioWrite", "ioapicMmioRead");
     1278        AssertRCReturn(rc, rc);
    13111279    }
    13121280
    … …  
    13151283     */
    13161284    rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
    1317     if (RT_FAILURE(rc))
    1318     {
    1319         LogRel(("IOAPIC: PDMDevHlpSSMRegister failed! rc=%Rrc\n", rc));
    1320         return rc;
    1321     }
     1285    AssertRCReturn(rc, rc);
    13221286
    13231287    /*
    … …  
    13371301     * Statistics.
    13381302     */
    1339     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ,  STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
    1340     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
    1341     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ,    STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
    1342     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ,    STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
    1343 
    1344     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3,  STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
    1345     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
    1346     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3,    STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetIrqR3",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
    1347     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3,    STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
    1348 
    1349     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr,   STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr",   STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
    1350     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr,  STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr",  STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
    1351     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
    1352 
    1353     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention,    STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
    1354     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
    1355 
    1356     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
    1357     PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived,  STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
     1303    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ,  STAMTYPE_COUNTER, "RZ/MmioReadRZ",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
     1304    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
     1305    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ,    STAMTYPE_COUNTER, "RZ/SetIrqRZ",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
     1306    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ,    STAMTYPE_COUNTER, "RZ/SetEoiRZ",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
     1307
     1308    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3,  STAMTYPE_COUNTER, "R3/MmioReadR3",  STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
     1309    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
     1310    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3,    STAMTYPE_COUNTER, "R3/SetIrqR3",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
     1311    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3,    STAMTYPE_COUNTER, "R3/SetEoiR3",    STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
     1312
     1313    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr,   STAMTYPE_COUNTER, "RedundantEdgeIntr",   STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
     1314    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr,  STAMTYPE_COUNTER, "RedundantLevelIntr",  STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
     1315    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
     1316
     1317    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention,    STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
     1318    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
     1319
     1320    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
     1321    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived,  STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
    13581322# endif
    13591323
    … …  
    13671331}
    13681332
    1369 #endif /* IN_RING3 */
     1333#else /* !IN_RING3 */
     1334
     1335/**
     1336 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
     1337 */
     1338static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
     1339{
     1340    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     1341    PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
     1342
     1343    int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
     1344    AssertRCReturn(rc, rc);
     1345
     1346    PDMIOAPICREG IoApicReg;
     1347    IoApicReg.u32Version   = PDM_IOAPICREG_VERSION;
     1348    IoApicReg.pfnSetIrq    = ioapicSetIrq;
     1349    IoApicReg.pfnSendMsi   = ioapicSendMsi;
     1350    IoApicReg.pfnSetEoi    = ioapicSetEoi;
     1351    IoApicReg.u32TheEnd    = PDM_IOAPICREG_VERSION;
     1352    rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThis->CTX_SUFF(pIoApicHlp));
     1353    AssertRCReturn(rc, rc);
     1354
     1355    return VINF_SUCCESS;
     1356}
     1357
     1358#endif /* !IN_RING3 */
    13701359
    13711360/**
    … …  
    14141403#elif defined(IN_RING0)
    14151404    /* .pfnEarlyConstruct = */      NULL,
    1416     /* .pfnConstruct = */           NULL,
     1405    /* .pfnConstruct = */           ioapicRZConstruct,
    14171406    /* .pfnDestruct = */            NULL,
    14181407    /* .pfnFinalDestruct = */       NULL,
    … …  
    14271416    /* .pfnReserved7 = */           NULL,
    14281417#elif defined(IN_RC)
    1429     /* .pfnConstruct = */           NULL,
     1418    /* .pfnConstruct = */           ioapicRZConstruct,
    14301419    /* .pfnReserved0 = */           NULL,
    14311420    /* .pfnReserved1 = */           NULL,
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