VirtualBox

Changeset 81942 in vbox for trunk/src/VBox/Devices/PC


Ignore:
Timestamp:
Nov 18, 2019 2:10:03 PM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
134739
Message:

DevIoApic: Convert the MMIO handlers to new style. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/PC/DevIoApic.cpp

    r81939 r81942  
    235235#endif
    236236
     237    /** The MMIO region. */
     238    IOMMMIOHANDLE           hMmio;
     239
    237240#ifdef VBOX_WITH_STATISTICS
    238241    /** Number of MMIO reads in RZ. */
     
    451454{
    452455    uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
     456    AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
     457                    ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
     458                    UINT32_MAX);
    453459    uint32_t uValue;
    454460    if (!(uIndex & 1))
     
    465471 * Sets the redirection table entry.
    466472 *
     473 * @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
    467474 * @param   pThis       Pointer to the IOAPIC instance.
    468475 * @param   uIndex      The index value.
    469476 * @param   uValue      The value to set.
    470477 */
    471 static int ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
     478static VBOXSTRICTRC ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
    472479{
    473480    uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
    474     AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte,
    475                                                             RT_ELEMENTS(pThis->au64RedirTable)));
    476 
    477     int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
     481    AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
     482                    ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
     483                    VINF_SUCCESS);
     484
     485    VBOXSTRICTRC rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
    478486    if (rc == VINF_SUCCESS)
    479487    {
     
    563571 * Sets the data register.
    564572 *
    565  * @param pThis     Pointer to the IOAPIC instance.
    566  * @param uValue    The value to set.
    567  */
    568 static int ioapicSetData(PIOAPIC pThis, uint32_t uValue)
     573 * @returns Strict VBox status code.
     574 * @param   pThis   Pointer to the IOAPIC instance.
     575 * @param   uValue  The value to set.
     576 */
     577static VBOXSTRICTRC ioapicSetData(PIOAPIC pThis, uint32_t uValue)
    569578{
    570579    uint8_t const uIndex = pThis->u8Index;
     
    588597 * @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3}
    589598 */
    590 PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
     599static DECLCALLBACK(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
    591600{
    592601    PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
     
    634643 * @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3}
    635644 */
    636 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
    637 {
    638 #define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask)       do { \
     645static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
     646{
     647#define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \
    639648        pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
    640649        pThis->uIrr |= a_PinMask; \
     
    647656    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
    648657
    649     if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
     658    if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
    650659    {
    651660        int rc = IOAPIC_LOCK(pThis, VINF_SUCCESS);
     
    729738 * @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3}
    730739 */
    731 PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
     740static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
    732741{
    733742    PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
     
    768777
    769778/**
    770  * @callback_method_impl{FNIOMMMIOREAD}
    771  */
    772 PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
     779 * @callback_method_impl{FNIOMMMIONEWREAD}
     780 */
     781static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
    773782{
    774783    PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
     
    777786    RT_NOREF_PV(pvUser);
    778787
    779     int      rc      = VINF_SUCCESS;
    780     uint32_t *puValue = (uint32_t *)pv;
    781     uint32_t  offReg  = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
     788    VBOXSTRICTRC rc      = VINF_SUCCESS;
     789    uint32_t    *puValue = (uint32_t *)pv;
     790    uint32_t     offReg  = off & IOAPIC_MMIO_REG_MASK;
    782791    switch (offReg)
    783792    {
     
    791800
    792801        default:
    793             Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
     802            Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
    794803            rc = VINF_IOM_MMIO_UNUSED_FF;
    795804            break;
     
    802811
    803812/**
    804  * @callback_method_impl{FNIOMMMIOWRITE}
    805  */
    806 PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
     813 * @callback_method_impl{FNIOMMMIONEWWRITE}
     814 */
     815static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
    807816{
    808817    PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
     
    811820    STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
    812821
    813     Assert(!(GCPhysAddr & 3));
     822    Assert(!(off & 3));
    814823    Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
    815824
     825    VBOXSTRICTRC   rc     = VINF_SUCCESS;
    816826    uint32_t const uValue = *(uint32_t const *)pv;
    817     uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
    818 
    819     LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue));
    820     int rc = VINF_SUCCESS;
     827    uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
     828
     829    LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
    821830    switch (offReg)
    822831    {
     
    837846
    838847        default:
    839             Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
     848            Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
    840849            break;
    841850    }
     
    878887{
    879888    RT_NOREF(pDesc, pfMask);
    880      return ioapicSetData(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
     889     return VBOXSTRICTRC_VAL(ioapicSetData(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32));
    881890}
    882891
     
    12661275     * Register MMIO callbacks.
    12671276     */
    1268     rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis,
    1269                                IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
    1270                                "I/O APIC");
     1277    rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
     1278                                   IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
    12711279    AssertRCReturn(rc, rc);
    1272     if (pDevIns->fR0Enabled | pDevIns->fRCEnabled)
    1273     {
    1274         rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
    1275                                      "ioapicMmioWrite", "ioapicMmioRead");
    1276         AssertRCReturn(rc, rc);
    1277 
    1278         rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
    1279                                      "ioapicMmioWrite", "ioapicMmioRead");
    1280         AssertRCReturn(rc, rc);
    1281     }
    12821280
    12831281    /*
     
    13531351    IoApicReg.u32TheEnd    = PDM_IOAPICREG_VERSION;
    13541352    rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThis->CTX_SUFF(pIoApicHlp));
     1353    AssertRCReturn(rc, rc);
     1354
     1355    rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /*pvUser*/);
    13551356    AssertRCReturn(rc, rc);
    13561357
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