Changeset 81942 in vbox for trunk/src/VBox/Devices/PC
- Timestamp:
- Nov 18, 2019 2:10:03 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 134739
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevIoApic.cpp
r81939 r81942 235 235 #endif 236 236 237 /** The MMIO region. */ 238 IOMMMIOHANDLE hMmio; 239 237 240 #ifdef VBOX_WITH_STATISTICS 238 241 /** Number of MMIO reads in RZ. */ … … 451 454 { 452 455 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1; 456 AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable), 457 ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)), 458 UINT32_MAX); 453 459 uint32_t uValue; 454 460 if (!(uIndex & 1)) … … 465 471 * Sets the redirection table entry. 466 472 * 473 * @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS). 467 474 * @param pThis Pointer to the IOAPIC instance. 468 475 * @param uIndex The index value. 469 476 * @param uValue The value to set. 470 477 */ 471 static intioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)478 static VBOXSTRICTRC ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue) 472 479 { 473 480 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1; 474 AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte, 475 RT_ELEMENTS(pThis->au64RedirTable))); 476 477 int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE); 481 AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable), 482 ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)), 483 VINF_SUCCESS); 484 485 VBOXSTRICTRC rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE); 478 486 if (rc == VINF_SUCCESS) 479 487 { … … 563 571 * Sets the data register. 564 572 * 565 * @param pThis Pointer to the IOAPIC instance. 566 * @param uValue The value to set. 567 */ 568 static int ioapicSetData(PIOAPIC pThis, uint32_t uValue) 573 * @returns Strict VBox status code. 574 * @param pThis Pointer to the IOAPIC instance. 575 * @param uValue The value to set. 576 */ 577 static VBOXSTRICTRC ioapicSetData(PIOAPIC pThis, uint32_t uValue) 569 578 { 570 579 uint8_t const uIndex = pThis->u8Index; … … 588 597 * @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3} 589 598 */ 590 PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)599 static DECLCALLBACK(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector) 591 600 { 592 601 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); … … 634 643 * @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3} 635 644 */ 636 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)637 { 638 #define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) 645 static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc) 646 { 647 #define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \ 639 648 pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \ 640 649 pThis->uIrr |= a_PinMask; \ … … 647 656 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq)); 648 657 649 if (RT_LIKELY( iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))658 if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable))) 650 659 { 651 660 int rc = IOAPIC_LOCK(pThis, VINF_SUCCESS); … … 729 738 * @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3} 730 739 */ 731 PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)740 static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc) 732 741 { 733 742 PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC); … … 768 777 769 778 /** 770 * @callback_method_impl{FNIOMMMIO READ}771 */ 772 PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)779 * @callback_method_impl{FNIOMMMIONEWREAD} 780 */ 781 static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb) 773 782 { 774 783 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); … … 777 786 RT_NOREF_PV(pvUser); 778 787 779 intrc = VINF_SUCCESS;780 uint32_t *puValue = (uint32_t *)pv;781 uint32_t offReg = GCPhysAddr& IOAPIC_MMIO_REG_MASK;788 VBOXSTRICTRC rc = VINF_SUCCESS; 789 uint32_t *puValue = (uint32_t *)pv; 790 uint32_t offReg = off & IOAPIC_MMIO_REG_MASK; 782 791 switch (offReg) 783 792 { … … 791 800 792 801 default: 793 Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));802 Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg)); 794 803 rc = VINF_IOM_MMIO_UNUSED_FF; 795 804 break; … … 802 811 803 812 /** 804 * @callback_method_impl{FNIOMMMIO WRITE}805 */ 806 PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)813 * @callback_method_impl{FNIOMMMIONEWWRITE} 814 */ 815 static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb) 807 816 { 808 817 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); … … 811 820 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); 812 821 813 Assert(!( GCPhysAddr& 3));822 Assert(!(off & 3)); 814 823 Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */ 815 824 825 VBOXSTRICTRC rc = VINF_SUCCESS; 816 826 uint32_t const uValue = *(uint32_t const *)pv; 817 uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK; 818 819 LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue)); 820 int rc = VINF_SUCCESS; 827 uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK; 828 829 LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue)); 821 830 switch (offReg) 822 831 { … … 837 846 838 847 default: 839 Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));848 Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg)); 840 849 break; 841 850 } … … 878 887 { 879 888 RT_NOREF(pDesc, pfMask); 880 return ioapicSetData(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);889 return VBOXSTRICTRC_VAL(ioapicSetData(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32)); 881 890 } 882 891 … … 1266 1275 * Register MMIO callbacks. 1267 1276 */ 1268 rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis, 1269 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead, 1270 "I/O APIC"); 1277 rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead, 1278 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio); 1271 1279 AssertRCReturn(rc, rc); 1272 if (pDevIns->fR0Enabled | pDevIns->fRCEnabled)1273 {1274 rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,1275 "ioapicMmioWrite", "ioapicMmioRead");1276 AssertRCReturn(rc, rc);1277 1278 rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,1279 "ioapicMmioWrite", "ioapicMmioRead");1280 AssertRCReturn(rc, rc);1281 }1282 1280 1283 1281 /* … … 1353 1351 IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION; 1354 1352 rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThis->CTX_SUFF(pIoApicHlp)); 1353 AssertRCReturn(rc, rc); 1354 1355 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /*pvUser*/); 1355 1356 AssertRCReturn(rc, rc); 1356 1357
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