Changeset 81946 in vbox
- Timestamp:
- Nov 18, 2019 3:58:20 PM (5 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevIoApic.cpp
r81942 r81946 168 168 #define IOAPIC_WITH_PDM_CRITSECT 169 169 #ifdef IOAPIC_WITH_PDM_CRITSECT 170 # define IOAPIC_LOCK( pThis, rcBusy) (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), (rcBusy))171 # define IOAPIC_UNLOCK( pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))170 # define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy)) 171 # define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns)) 172 172 #else 173 # define IOAPIC_LOCK( pThis, rcBusy) PDMCritSectEnter(&(pThis)->CritSect, (rcBusy))174 # define IOAPIC_UNLOCK( pThis) PDMCritSectLeave(&(pThis)->CritSect)173 # define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy)) 174 # define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect) 175 175 #endif 176 176 … … 180 180 *********************************************************************************************************************************/ 181 181 /** 182 * The per-VMI/O APIC device state.182 * The shared I/O APIC device state. 183 183 */ 184 184 typedef struct IOAPIC 185 185 { 186 /** The device instance - R3 Ptr. */187 PPDMDEVINSR3 pDevInsR3;188 /** The IOAPIC helpers - R3 Ptr. */189 R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlpR3;190 191 /** The device instance - R0 Ptr. */192 PPDMDEVINSR0 pDevInsR0;193 /** The IOAPIC helpers - R0 Ptr. */194 R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlpR0;195 196 /** The device instance - RC Ptr. */197 PPDMDEVINSRC pDevInsRC;198 /** The IOAPIC helpers - RC Ptr. */199 RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlpRC;200 201 186 /** The ID register. */ 202 187 uint8_t volatile u8Id; … … 225 210 uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS]; 226 211 212 /** The internal IRR reflecting state of the interrupt lines. */ 213 uint32_t uIrr; 227 214 /** Alignment padding. */ 228 215 uint32_t u32Padding2; 229 /** The internal IRR reflecting state of the interrupt lines. */230 uint32_t uIrr;231 216 232 217 #ifndef IOAPIC_WITH_PDM_CRITSECT … … 276 261 #endif 277 262 } IOAPIC; 278 /** Pointer to IOAPIC data. */ 263 AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8); 264 /** Pointer to shared IOAPIC data. */ 279 265 typedef IOAPIC *PIOAPIC; 280 /** Pointer to a constIOAPIC data. */266 /** Pointer to const shared IOAPIC data. */ 281 267 typedef IOAPIC const *PCIOAPIC; 282 AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8); 268 269 270 /** 271 * The I/O APIC device state for ring-3. 272 */ 273 typedef struct IOAPICR3 274 { 275 /** The IOAPIC helpers. */ 276 R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp; 277 } IOAPICR3; 278 /** Pointer to the I/O APIC device state for ring-3. */ 279 typedef IOAPICR3 *PIOAPICR3; 280 281 282 /** 283 * The I/O APIC device state for ring-0. 284 */ 285 typedef struct IOAPICR0 286 { 287 /** The IOAPIC helpers. */ 288 R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp; 289 } IOAPICR0; 290 /** Pointer to the I/O APIC device state for ring-0. */ 291 typedef IOAPICR0 *PIOAPICR0; 292 293 294 /** 295 * The I/O APIC device state for raw-mode. 296 */ 297 typedef struct IOAPICRC 298 { 299 /** The IOAPIC helpers. */ 300 RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp; 301 } IOAPICRC; 302 /** Pointer to the I/O APIC device state for raw-mode. */ 303 typedef IOAPICRC *PIOAPICRC; 304 305 306 /** The I/O APIC device state for the current context. */ 307 typedef CTX_SUFF(IOAPIC) IOAPICCC; 308 /** Pointer to the I/O APIC device state for the current context. */ 309 typedef CTX_SUFF(PIOAPIC) PIOAPICCC; 310 283 311 284 312 #ifndef VBOX_DEVICE_STRUCT_TESTCASE … … 312 340 * Sets the ID register. 313 341 * 314 * @param pThis Pointer to the IOAPIC instance.342 * @param pThis The shared I/O APIC device state. 315 343 * @param uValue The value to set. 316 344 */ … … 326 354 * 327 355 * @returns The ID. 328 * @param pThis Pointer to the IOAPIC instance.356 * @param pThis The shared I/O APIC device state. 329 357 */ 330 358 DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis) … … 339 367 * Sets the index register. 340 368 * 341 * @param pThis Pointer to the IOAPIC instance.369 * @param pThis The shared I/O APIC device state. 342 370 * @param uValue The value to set. 343 371 */ … … 366 394 * (RTE). 367 395 * 368 * @param pThis The IOAPIC instance. 396 * @param pDevIns The device instance. 397 * @param pThis The shared I/O APIC device state. 398 * @param pThisCC The I/O APIC device state for the current context. 369 399 * @param idxRte The index of the RTE. 370 400 * … … 373 403 * function. 374 404 */ 375 static void ioapicSignalIntrForRte(P IOAPIC pThis, uint8_t idxRte)405 static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte) 376 406 { 377 407 #ifndef IOAPIC_WITH_PDM_CRITSECT … … 409 439 * Deliver to the local APIC via the system/3-wire-APIC bus. 410 440 */ 411 int rc = pThis ->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),412 413 414 415 416 417 418 441 int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns, 442 u8Dest, 443 u8DestMode, 444 u8DeliveryMode, 445 u8Vector, 446 u8Polarity, 447 u8TriggerMode, 448 u32TagSrc); 419 449 /* Can't reschedule to R3. */ 420 450 Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); … … 448 478 * 449 479 * @returns The redirection table entry. 450 * @param pThis Pointer to the IOAPIC instance.480 * @param pThis The shared I/O APIC device state. 451 481 * @param uIndex The index value. 452 482 */ … … 472 502 * 473 503 * @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS). 474 * @param pThis Pointer to the IOAPIC instance. 504 * @param pDevIns The device instance. 505 * @param pThis The shared I/O APIC device state. 506 * @param pThisCC The I/O APIC device state for the current context. 475 507 * @param uIndex The index value. 476 508 * @param uValue The value to set. 477 509 */ 478 static VBOXSTRICTRC ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue) 510 static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, 511 uint32_t uIndex, uint32_t uValue) 479 512 { 480 513 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1; … … 483 516 VINF_SUCCESS); 484 517 485 VBOXSTRICTRC rc = IOAPIC_LOCK(p This, VINF_IOM_R3_MMIO_WRITE);518 VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE); 486 519 if (rc == VINF_SUCCESS) 487 520 { … … 514 547 uint32_t const uPinMask = UINT32_C(1) << idxRte; 515 548 if (pThis->uIrr & uPinMask) 516 ioapicSignalIntrForRte(p This, idxRte);517 518 IOAPIC_UNLOCK(p This);549 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte); 550 551 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC); 519 552 LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue)); 520 553 } … … 530 563 * 531 564 * @returns The data value. 532 * @param pThis Pointer to the IOAPIC instance.565 * @param pThis The shared I/O APIC device state. 533 566 */ 534 567 static uint32_t ioapicGetData(PCIOAPIC pThis) … … 572 605 * 573 606 * @returns Strict VBox status code. 574 * @param pThis Pointer to the IOAPIC instance. 575 * @param uValue The value to set. 576 */ 577 static VBOXSTRICTRC ioapicSetData(PIOAPIC pThis, uint32_t uValue) 607 * @param pDevIns The device instance. 608 * @param pThis The shared I/O APIC device state. 609 * @param pThisCC The I/O APIC device state for the current context. 610 * @param uValue The value to set. 611 */ 612 static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue) 578 613 { 579 614 uint8_t const uIndex = pThis->u8Index; … … 583 618 if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 584 619 && uIndex <= pThis->u8LastRteRegIdx) 585 return ioapicSetRedirTableEntry(p This, uIndex, uValue);620 return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue); 586 621 587 622 if (uIndex == IOAPIC_INDIRECT_INDEX_ID) … … 599 634 static DECLCALLBACK(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector) 600 635 { 601 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 636 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 637 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 602 638 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi)); 603 639 LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector)); 604 640 605 641 bool fRemoteIrrCleared = false; 606 int rc = IOAPIC_LOCK(p This, VINF_IOM_R3_MMIO_WRITE);642 int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE); 607 643 if (rc == VINF_SUCCESS) 608 644 { … … 626 662 uint32_t const uPinMask = UINT32_C(1) << idxRte; 627 663 if (pThis->uIrr & uPinMask) 628 ioapicSignalIntrForRte(p This, idxRte);664 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte); 629 665 } 630 666 } 631 667 632 IOAPIC_UNLOCK(p This);668 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC); 633 669 AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector)); 634 670 } … … 648 684 pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \ 649 685 pThis->uIrr |= a_PinMask; \ 650 ioapicSignalIntrForRte(p This, (a_idxRte)); \686 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \ 651 687 } while (0) 652 688 653 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 689 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 690 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 654 691 LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc)); 655 692 … … 658 695 if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable))) 659 696 { 660 int rc = IOAPIC_LOCK(p This, VINF_SUCCESS);697 int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS); 661 698 AssertRC(rc); 662 699 … … 676 713 { 677 714 pThis->uIrr &= ~uPinMask; 678 IOAPIC_UNLOCK(p This);715 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC); 679 716 return; 680 717 } … … 729 766 } 730 767 731 IOAPIC_UNLOCK(p This);768 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC); 732 769 } 733 770 #undef IOAPIC_ASSERT_IRQ … … 740 777 static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc) 741 778 { 742 P CIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);779 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 743 780 LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue)); 744 781 … … 763 800 * Deliver to the local APIC via the system/3-wire-APIC bus. 764 801 */ 765 int rc = pThis ->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,766 767 768 769 770 771 772 802 int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns, 803 u8DestAddr, 804 u8DestMode, 805 u8DeliveryMode, 806 u8Vector, 807 0 /* u8Polarity - N/A */, 808 u8TriggerMode, 809 uTagSrc); 773 810 /* Can't reschedule to R3. */ 774 811 Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); NOREF(rc); … … 815 852 static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb) 816 853 { 817 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 854 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 855 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 818 856 RT_NOREF_PV(pvUser); 819 857 … … 835 873 836 874 case IOAPIC_DIRECT_OFF_DATA: 837 rc = ioapicSetData(p This, uValue);875 rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue); 838 876 break; 839 877 … … 886 924 static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 887 925 { 926 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser; 927 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 928 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 888 929 RT_NOREF(pDesc, pfMask); 889 return VBOXSTRICTRC_VAL(ioapicSetData(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32));930 return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32)); 890 931 } 891 932 … … 1117 1158 static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns) 1118 1159 { 1119 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1160 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1161 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 1120 1162 LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis)); 1121 1163 1122 1164 /* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */ 1123 IOAPIC_LOCK(p This, VERR_IGNORED);1165 IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED); 1124 1166 1125 1167 pThis->uIrr = 0; … … 1133 1175 } 1134 1176 1135 IOAPIC_UNLOCK(p This);1177 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC); 1136 1178 } 1137 1179 … … 1142 1184 static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta) 1143 1185 { 1144 RT_NOREF(offDelta); 1145 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1146 LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta)); 1147 1148 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 1149 pThis->pIoApicHlpRC += offDelta; 1186 PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC); 1187 LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta)); 1188 1189 pThisRC->pIoApicHlp += offDelta; 1150 1190 } 1151 1191 … … 1180 1220 { 1181 1221 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 1182 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1183 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 1222 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1223 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 1224 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; 1184 1225 LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance)); 1185 1226 Assert(iInstance == 0); RT_NOREF(iInstance); 1186 1187 /*1188 * Initialize the state data.1189 */1190 pThis->pDevInsR3 = pDevIns;1191 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);1192 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);1193 1227 1194 1228 /* … … 1269 1303 IoApicReg.pfnSetEoi = ioapicSetEoi; 1270 1304 IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION; 1271 rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThis ->pIoApicHlpR3);1305 rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp); 1272 1306 AssertRCReturn(rc, rc); 1273 1307 … … 1294 1328 * Register debugger register access. 1295 1329 */ 1296 rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);1330 rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); 1297 1331 AssertRCReturn(rc, rc); 1298 1332 … … 1339 1373 { 1340 1374 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 1341 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1375 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC); 1376 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 1342 1377 1343 1378 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns)); … … 1350 1385 IoApicReg.pfnSetEoi = ioapicSetEoi; 1351 1386 IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION; 1352 rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThis ->CTX_SUFF(pIoApicHlp));1387 rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp); 1353 1388 AssertRCReturn(rc, rc); 1354 1389 … … 1369 1404 /* .uReserved0 = */ 0, 1370 1405 /* .szName = */ "ioapic", 1371 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ ,1406 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE, 1372 1407 /* .fClass = */ PDM_DEVREG_CLASS_PIC, 1373 1408 /* .cMaxInstances = */ 1, 1374 1409 /* .uSharedVersion = */ 42, 1375 1410 /* .cbInstanceShared = */ sizeof(IOAPIC), 1376 /* .cbInstanceCC = */ 0,1377 /* .cbInstanceRC = */ 0,1411 /* .cbInstanceCC = */ sizeof(IOAPICCC), 1412 /* .cbInstanceRC = */ sizeof(IOAPICRC), 1378 1413 /* .cMaxPciDevices = */ 0, 1379 1414 /* .cMaxMsixVectors = */ 0,
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