Index: trunk/src/VBox/Devices/PC/DevDMA.cpp
===================================================================
--- trunk/src/VBox/Devices/PC/DevDMA.cpp	(revision 81984)
+++ trunk/src/VBox/Devices/PC/DevDMA.cpp	(revision 81985)
@@ -49,4 +49,5 @@
 #include <VBox/err.h>
 
+#include <VBox/AssertGuest.h>
 #include <VBox/log.h>
 #include <iprt/assert.h>
@@ -110,5 +111,6 @@
     uint8_t                             u8Mode;         /* Channel mode. */
     uint8_t                             abPadding[7];
-} DMAChannel;
+} DMAChannel, DMACHANNEL;
+typedef DMACHANNEL *PDMACHANNEL;
 
 /* State information for a DMA controller (DMA8 or DMA16). */
@@ -143,4 +145,5 @@
     PPDMDEVINSR3            pDevIns;    /* Device instance. */
     R3PTRTYPE(PCPDMDMACHLP) pHlp;       /* PDM DMA helpers. */
+    STAMPROFILE             StatRun;
 } DMAState, DMASTATE;
 /** Pointer to the shared DMA state information. */
@@ -260,13 +263,11 @@
     if (cb == 1)
     {
-        DMAControl  *dc = (DMAControl *)pvUser;
-        DMAChannel  *ch;
-        int         chidx, reg, is_count;
-
+        PDMACONTROLLER dc       = (PDMACONTROLLER)pvUser;
+        unsigned const reg      = (offPort >> dc->is16bit) & 0x0f;
+        unsigned const chidx    = reg >> 1;
+        unsigned const is_count = reg & 1;
+        PDMACHANNEL    ch       = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx);
         Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
-        reg      = (offPort >> dc->is16bit) & 0x0f;
-        chidx    = reg >> 1;
-        is_count = reg & 1;
-        ch       = &dc->ChState[chidx];
+
         if (dmaReadBytePtr(dc))
         {
@@ -307,14 +308,12 @@
     if (cb == 1)
     {
-        DMAControl  *dc = (DMAControl *)pvUser;
-        DMAChannel  *ch;
-        int         chidx, reg, val, dir;
-        int         bptr;
-
-        reg   = (offPort >> dc->is16bit) & 0x0f;
-        chidx = reg >> 1;
-        ch    = &dc->ChState[chidx];
-
-        dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
+        PDMACONTROLLER dc    = (PDMACONTROLLER)pvUser;
+        unsigned const reg   = (offPort >> dc->is16bit) & 0x0f;
+        unsigned const chidx = reg >> 1;
+        PDMACHANNEL    ch    = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx);
+        int const      dir   = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
+        int            val;
+        int            bptr;
+
         if (reg & 1)
             val = ch->u16BaseCount - ch->u16CurCount;
@@ -341,6 +340,6 @@
     if (cb == 1)
     {
-        DMAControl  *dc = (DMAControl *)pvUser;
-        unsigned     chidx = 0;
+        PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
+        unsigned       chidx = 0;
 
         unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
@@ -374,17 +373,9 @@
             break;
         case CTL_W_MODE:
-            {
-                int op, opmode;
-
-                chidx = u32 & 3;
-                op = (u32 >> 2) & 3;
-                opmode = (u32 >> 6) & 3;
-                Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
-                      chidx, op, IS_MODE_AI(u32) ? "" : "no ",
-                      IS_MODE_DEC(u32) ? "de" : "in", opmode));
-
-                dc->ChState[chidx].u8Mode = u32;
-                break;
-            }
+            chidx = u32 & 3;
+            dc->ChState[chidx].u8Mode = u32;
+            Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
+                  chidx, (u32 >> 2) & 3, IS_MODE_AI(u32) ? "" : "no ", IS_MODE_DEC(u32) ? "de" : "in", (u32 >> 6) & 3));
+            break;
         case CTL_W_CLRBPTR:
             dc->fHiByte = false;
@@ -400,5 +391,5 @@
             break;
         default:
-            Assert(0);
+            ASSERT_GUEST_MSG_FAILED(("reg=%u\n", reg));
             break;
         }
@@ -422,6 +413,6 @@
     if (cb == 1)
     {
-        DMAControl  *dc = (DMAControl *)pvUser;
-        uint8_t     val = 0;
+        PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
+        uint8_t        val = 0;
 
         unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
@@ -441,5 +432,5 @@
                 break;
             case CTL_R_MODE:
-                val = dc->ChState[dc->u8ModeCtr].u8Mode | 3;
+                val = RT_SAFE_SUBSCRIPT(dc->ChState, dc->u8ModeCtr).u8Mode | 3;
                 dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
                 break;
@@ -483,6 +474,6 @@
 {
     RT_NOREF(pDevIns);
-    DMAControl  *dc = (DMAControl *)pvUser;
-    int         reg;
+    PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
+    int            reg;
 
     if (cb == 1)
@@ -513,6 +504,6 @@
 {
     RT_NOREF(pDevIns);
-    DMAControl  *dc = (DMAControl *)pvUser;
-    int         reg;
+    PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
+    unsigned       reg;
 
     if (cb == 1)
@@ -553,8 +544,7 @@
     if (cb == 1)
     {
-        DMAControl  *dc = (DMAControl *)pvUser;
-        int         reg;
-
-        reg   = offPort & 7;
+        PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
+        unsigned const reg = offPort & 7;
+
         *pu32 = dc->au8PageHi[reg];
         Log2(("Read %#x to from high page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
@@ -573,9 +563,8 @@
     if (cb == 1)
     {
-        DMAControl  *dc = (DMAControl *)pvUser;
-        int         reg;
+        PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
+        unsigned const reg = offPort & 7;
 
         Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
-        reg = offPort & 7;
         dc->au8PageHi[reg] = u32;
         Log2(("Wrote %#x to high page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
@@ -602,7 +591,5 @@
     opmode = (ch->u8Mode >> 6) & 3;
 
-    Log3(("DMA address %screment, mode %d\n",
-          IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
-          ch->u8Mode >> 6));
+    Log3(("DMA address %screment, mode %d\n", IS_MODE_DEC(ch->u8Mode) ? "de" : "in", ch->u8Mode >> 6));
 
     /* Addresses and counts are shifted for 16-bit channels. */
@@ -638,8 +625,9 @@
     DMAControl  *dc;
     int         ctlidx, chidx, mask;
+    STAM_PROFILE_START(&pThis->StatRun, a);
     PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
 
     /* Run all controllers and channels. */
-    for (ctlidx = 0; ctlidx < 2; ++ctlidx)
+    for (ctlidx = 0; ctlidx < RT_ELEMENTS(pThis->DMAC); ++ctlidx)
     {
         dc = &pThis->DMAC[ctlidx];
@@ -658,4 +646,5 @@
 
     PDMCritSectLeave(pDevIns->pCritSectRoR3);
+    STAM_PROFILE_STOP(&pThis->StatRun, a);
     return 0;
 }
@@ -1043,4 +1032,9 @@
     AssertRCReturn(rc, rc);
 
+    /*
+     * Statistics.
+     */
+    PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRun, STAMTYPE_PROFILE, "DmaRun", STAMUNIT_TICKS_PER_CALL, "Profiling dmaRun().");
+
     return VINF_SUCCESS;
 }
@@ -1090,5 +1084,5 @@
     /* .uReserved0 = */             0,
     /* .szName = */                 "8237A",
-    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ,
+    /* .fFlags = */                 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
     /* .fClass = */                 PDM_DEVREG_CLASS_DMA,
     /* .cMaxInstances = */          1,
