Changeset 82009 in vbox
- Timestamp:
- Nov 19, 2019 11:04:49 PM (5 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/src/VBox/Devices/PC/DevACPI.cpp
r81996 r82009 477 477 uint32_t uPmTimeB; 478 478 uint32_t Alignment5; 479 480 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group. 481 * @{ */ 482 IOMIOPORTHANDLE hIoPortPm1aEn; 483 IOMIOPORTHANDLE hIoPortPm1aSts; 484 IOMIOPORTHANDLE hIoPortPm1aCtl; 485 IOMIOPORTHANDLE hIoPortPmTimer; 486 IOMIOPORTHANDLE hIoPortGpe0En; 487 IOMIOPORTHANDLE hIoPortGpe0Sts; 488 /** @} */ 489 479 490 } ACPIState, ACPISTATE; 480 491 /** Pointer to the shared ACPI device state. */ … … 766 777 * Internal Functions * 767 778 *********************************************************************************************************************************/ 768 RT_C_DECLS_BEGIN769 PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);770 RT_C_DECLS_END771 779 #ifdef IN_RING3 772 780 static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis); … … 866 874 * @returns Strict VBox status code. 867 875 */ 868 static intacpiR3DoPowerOff(PPDMDEVINS pDevIns)869 { 870 intrc = PDMDevHlpVMPowerOff(pDevIns);876 static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns) 877 { 878 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns); 871 879 AssertRC(rc); 872 880 return rc; … … 880 888 * @returns Strict VBox status code. 881 889 */ 882 static intacpiR3DoSleep(PPDMDEVINS pDevIns, ACPIState *pThis)890 static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, ACPIState *pThis) 883 891 { 884 892 /* We must set WAK_STS on resume (includes restore) so the guest knows that 885 893 we've woken up and can continue executing code. The guest is probably 886 894 reading the PMSTS register in a loop to check this. */ 887 intrc;895 VBOXSTRICTRC rc; 888 896 pThis->fSetWakeupOnResume = true; 889 897 if (pThis->fSuspendToSavedState) … … 1206 1214 * @callback_method_impl{FNIOMIOPORTOUT, Battery status index} 1207 1215 */ 1208 PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1209 { 1216 PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1217 { 1218 RT_NOREF(pvUser, offPort); 1210 1219 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2)); 1211 1220 if (cb != 4) 1212 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1213 1214 ACPIState *pThis = (ACPIState *)pvUser;1221 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1222 1223 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1215 1224 DEVACPI_LOCK_R3(pDevIns, pThis); 1216 1225 … … 1232 1241 * @callback_method_impl{FNIOMIOPORTIN, Battery status data} 1233 1242 */ 1234 PDMBOTHCBDECL(int) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1235 { 1243 PDMBOTHCBDECL(int) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1244 { 1245 RT_NOREF(pvUser, offPort); 1236 1246 if (cb != 4) 1237 1247 return VERR_IOM_IOPORT_UNUSED; 1238 1248 1239 ACPIState *pThis = (ACPIState *)pvUser;1249 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1240 1250 DEVACPI_LOCK_R3(pDevIns, pThis); 1241 1251 … … 1275 1285 1276 1286 default: 1277 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb,Port, pThis->uBatteryIndex);1287 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex); 1278 1288 *pu32 = UINT32_MAX; 1279 1289 break; … … 1287 1297 * @callback_method_impl{FNIOMIOPORTOUT, System info index} 1288 1298 */ 1289 PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1290 { 1299 PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1300 { 1301 RT_NOREF(pvUser, offPort); 1291 1302 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2)); 1292 1303 if (cb != 4) 1293 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1294 1295 ACPIState *pThis = (ACPIState *)pvUser;1304 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1305 1306 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1296 1307 DEVACPI_LOCK_R3(pDevIns, pThis); 1297 1308 … … 1319 1330 * @callback_method_impl{FNIOMIOPORTIN, System info data} 1320 1331 */ 1321 PDMBOTHCBDECL(int) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1322 { 1332 PDMBOTHCBDECL(int) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1333 { 1334 RT_NOREF(pvUser, offPort); 1323 1335 if (cb != 4) 1324 1336 return VERR_IOM_IOPORT_UNUSED; 1325 1337 1326 ACPIState *pThis = (ACPIState *)pvUser;1338 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1327 1339 DEVACPI_LOCK_R3(pDevIns, pThis); 1328 1340 … … 1503 1515 default: 1504 1516 *pu32 = UINT32_MAX; 1505 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb,Port, pThis->uBatteryIndex);1517 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex); 1506 1518 break; 1507 1519 } … … 1515 1527 * @callback_method_impl{FNIOMIOPORTOUT, System info data} 1516 1528 */ 1517 PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1518 { 1519 ACPIState *pThis = (ACPIState *)pvUser; 1529 PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1530 { 1531 RT_NOREF(pvUser, offPort); 1532 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1520 1533 if (cb != 4) 1521 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb,Port, u32, pThis->uSystemInfoIndex);1534 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex); 1522 1535 1523 1536 DEVACPI_LOCK_R3(pDevIns, pThis); 1524 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, pThis->uSystemInfoIndex));1537 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex)); 1525 1538 1526 1539 int rc = VINF_SUCCESS; … … 1549 1562 1550 1563 default: 1551 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb,Port, u32, pThis->uSystemInfoIndex);1564 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex); 1552 1565 break; 1553 1566 } … … 1558 1571 1559 1572 /** 1560 * @callback_method_impl{FNIOMIOPORT IN, PM1a Enable}1561 */ 1562 PDMBOTHCBDECL(int) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORTPort, uint32_t *pu32, unsigned cb)1563 { 1564 NOREF(pDevIns); NOREF(Port);1573 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable} 1574 */ 1575 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1576 { 1577 RT_NOREF(offPort, pvUser); 1565 1578 if (cb != 2) 1566 1579 return VERR_IOM_IOPORT_UNUSED; 1567 1580 1568 ACPIState *pThis = (ACPIState *)pvUser;1581 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1569 1582 DEVACPI_LOCK_R3(pDevIns, pThis); 1570 1583 … … 1577 1590 1578 1591 /** 1579 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Enable} 1580 */ 1581 PDMBOTHCBDECL(int) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1582 { 1592 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable} 1593 */ 1594 static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1595 { 1596 RT_NOREF(offPort, pvUser); 1583 1597 if (cb != 2 && cb != 4) 1584 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1585 1586 ACPIState *pThis = (ACPIState *)pvUser;1598 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1599 1600 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1587 1601 DEVACPI_LOCK_R3(pDevIns, pThis); 1588 1602 … … 1597 1611 1598 1612 /** 1599 * @callback_method_impl{FNIOMIOPORTIN, PM1a Status} 1600 */ 1601 PDMBOTHCBDECL(int) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1602 { 1613 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status} 1614 */ 1615 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1616 { 1617 RT_NOREF(offPort, pvUser); 1603 1618 if (cb != 2) 1604 1619 { 1605 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb,Port);1620 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort); 1606 1621 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc; 1607 1622 } 1608 1623 1609 ACPIState *pThis = (ACPIState *)pvUser;1624 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1610 1625 DEVACPI_LOCK_R3(pDevIns, pThis); 1611 1626 … … 1618 1633 1619 1634 /** 1620 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Status} 1621 */ 1622 PDMBOTHCBDECL(int) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1623 { 1635 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status} 1636 */ 1637 static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1638 { 1639 RT_NOREF(offPort, pvUser); 1624 1640 if (cb != 2 && cb != 4) 1625 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1626 1627 ACPIState *pThis = (ACPIState *)pvUser;1641 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1642 1643 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1628 1644 DEVACPI_LOCK_R3(pDevIns, pThis); 1629 1645 … … 1640 1656 1641 1657 /** 1642 * @callback_method_impl{FNIOMIOPORTIN, PM1a Control} 1643 */ 1644 PDMBOTHCBDECL(int) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1645 { 1658 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control} 1659 */ 1660 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1661 { 1662 RT_NOREF(offPort, pvUser); 1646 1663 if (cb != 2) 1647 1664 { 1648 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb,Port);1665 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort); 1649 1666 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc; 1650 1667 } 1651 1668 1652 ACPIState *pThis = (ACPIState *)pvUser;1669 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1653 1670 DEVACPI_LOCK_R3(pDevIns, pThis); 1654 1671 … … 1661 1678 1662 1679 /** 1663 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Control} 1664 */ 1665 PDMBOTHCBDECL(int) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1666 { 1680 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control} 1681 */ 1682 static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1683 { 1684 RT_NOREF(offPort, pvUser); 1667 1685 if (cb != 2 && cb != 4) 1668 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1669 1670 ACPIState *pThis = (ACPIState *)pvUser;1686 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1687 1688 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1671 1689 DEVACPI_LOCK_R3(pDevIns, pThis); 1672 1690 … … 1675 1693 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT); 1676 1694 1677 intrc = VINF_SUCCESS;1695 VBOXSTRICTRC rc = VINF_SUCCESS; 1678 1696 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK; 1679 1697 if (uSleepState != pThis->uSleepState) … … 1724 1742 1725 1743 /** 1726 * @callback_method_impl{FNIOMIOPORT IN, PMTMR}1744 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR} 1727 1745 * 1728 * @remarks Only I/O port currently implemented in all contexts. 1729 */ 1730 PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1731 { 1746 * @remarks The only I/O port currently implemented in all contexts. 1747 */ 1748 static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1749 { 1750 RT_NOREF(offPort, pvUser); 1732 1751 if (cb != 4) 1733 1752 return VERR_IOM_IOPORT_UNUSED; 1734 1735 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);1736 1753 1737 1754 /* … … 1740 1757 * as well as and to prevent uPmTimerVal from being updated during read. 1741 1758 */ 1742 1743 intrc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VINF_IOM_R3_IOPORT_READ);1759 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1760 VBOXSTRICTRC rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VINF_IOM_R3_IOPORT_READ); 1744 1761 if (rc == VINF_SUCCESS) 1745 1762 { … … 1775 1792 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer); 1776 1793 } 1777 NOREF(pvUser); NOREF(Port);1778 1794 return rc; 1779 1795 } … … 1781 1797 #ifdef IN_RING3 1782 1798 1783 static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 1784 { 1785 RT_NOREF(pszArgs); 1799 /** 1800 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Status} 1801 */ 1802 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1803 { 1804 RT_NOREF(offPort, pvUser); 1805 if (cb != 1) 1806 { 1807 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort); 1808 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc; 1809 } 1810 1786 1811 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1787 pHlp->pfnPrintf(pHlp,1788 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);1789 }1790 1791 /**1792 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Status}1793 */1794 PDMBOTHCBDECL(int) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)1795 {1796 if (cb != 1)1797 {1798 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);1799 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;1800 }1801 1802 ACPIState *pThis = (ACPIState *)pvUser;1803 1812 DEVACPI_LOCK_R3(pDevIns, pThis); 1804 1813 … … 1813 1822 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Status} 1814 1823 */ 1815 PDMBOTHCBDECL(int) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1816 { 1824 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1825 { 1826 RT_NOREF(offPort, pvUser); 1817 1827 if (cb != 1) 1818 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1819 1820 ACPIState *pThis = (ACPIState *)pvUser;1828 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1829 1830 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1821 1831 DEVACPI_LOCK_R3(pDevIns, pThis); 1822 1832 … … 1832 1842 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Enable} 1833 1843 */ 1834 PDMBOTHCBDECL(int) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1835 { 1844 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 1845 { 1846 RT_NOREF(offPort, pvUser); 1836 1847 if (cb != 1) 1837 1848 { 1838 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb,Port);1849 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort); 1839 1850 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc; 1840 1851 } 1841 1852 1842 ACPIState *pThis = (ACPIState *)pvUser;1853 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1843 1854 DEVACPI_LOCK_R3(pDevIns, pThis); 1844 1855 … … 1853 1864 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Enable} 1854 1865 */ 1855 PDMBOTHCBDECL(int) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1856 { 1866 static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1867 { 1868 RT_NOREF(offPort, pvUser); 1857 1869 if (cb != 1) 1858 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1859 1860 ACPIState *pThis = (ACPIState *)pvUser;1870 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1871 1872 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1861 1873 DEVACPI_LOCK_R3(pDevIns, pThis); 1862 1874 … … 1871 1883 * @callback_method_impl{FNIOMIOPORTOUT, SMI_CMD} 1872 1884 */ 1873 PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1874 { 1885 PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1886 { 1887 RT_NOREF(offPort, pvUser); 1875 1888 Log(("acpiR3SmiWrite %#x\n", u32)); 1876 1889 if (cb != 1) 1877 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1878 1879 ACPIState *pThis = (ACPIState *)pvUser;1890 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1891 1892 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1880 1893 DEVACPI_LOCK_R3(pDevIns, pThis); 1881 1894 … … 1894 1907 * @callback_method_impl{FNIOMIOPORTOUT, ACPI_RESET_BLK} 1895 1908 */ 1896 PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1897 { 1909 PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1910 { 1911 RT_NOREF(offPort, pvUser); 1898 1912 Log(("acpiR3ResetWrite: %#x\n", u32)); 1899 1913 NOREF(pvUser); 1900 1914 if (cb != 1) 1901 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1915 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1902 1916 1903 1917 /* No state locking required. */ … … 1919 1933 * @callback_method_impl{FNIOMIOPORTOUT, Debug hex value logger} 1920 1934 */ 1921 PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)1935 PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1922 1936 { 1923 1937 NOREF(pvUser); … … 1934 1948 break; 1935 1949 default: 1936 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1950 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1937 1951 } 1938 1952 return VINF_SUCCESS; … … 1942 1956 * @callback_method_impl{FNIOMIOPORTOUT, Debug char logger} 1943 1957 */ 1944 PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)1958 PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 1945 1959 { 1946 1960 NOREF(pvUser); … … 1951 1965 break; 1952 1966 default: 1953 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);1967 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 1954 1968 } 1955 1969 return VINF_SUCCESS; … … 1957 1971 1958 1972 # endif /* DEBUG_ACPI */ 1973 1974 /** 1975 * @callback_method_impl{FNDBGFHANDLERDEV} 1976 */ 1977 static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 1978 { 1979 RT_NOREF(pszArgs); 1980 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 1981 pHlp->pfnPrintf(pHlp, 1982 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB); 1983 } 1959 1984 1960 1985 /** … … 1991 2016 1992 2017 /** 1993 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to registerthe PM1a, PM2018 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM 1994 2019 * timer and GPE0 I/O ports. 1995 2020 * … … 1998 2023 * @param pThis The ACPI shared instance data. 1999 2024 */ 2000 static int acpiR3 RegisterPmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis)2025 static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, ACPIState *pThis) 2001 2026 { 2002 2027 if (pThis->uPmIoPortBase == 0) 2003 2028 return VINF_SUCCESS; 2004 2029 2005 #define R(offset, cnt, writer, reader, description) \ 2006 do { \ 2007 int rc = PDMDevHlpIOPortRegister(pDevIns, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \ 2008 NULL, NULL, description); \ 2009 if (RT_FAILURE(rc)) \ 2010 return rc; \ 2011 } while (0) 2012 #define L (GPE0_BLK_LEN / 2) 2013 2014 R(PM1a_EVT_OFFSET+2, 1, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, "ACPI PM1a Enable"); 2015 R(PM1a_EVT_OFFSET, 1, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, "ACPI PM1a Status"); 2016 R(PM1a_CTL_OFFSET, 1, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, "ACPI PM1a Control"); 2017 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer"); 2018 R(GPE0_OFFSET + L, L, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, "ACPI GPE0 Enable"); 2019 R(GPE0_OFFSET, L, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, "ACPI GPE0 Status"); 2020 #undef L 2021 #undef R 2022 2023 /* register RC stuff */ 2024 if (pDevIns->fRCEnabled) 2025 { 2026 int rc = PDMDevHlpIOPortRegisterRC(pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET), 2027 1, 0, NULL, "acpiPMTmrRead", 2028 NULL, NULL, "ACPI PM Timer"); 2029 AssertRCReturn(rc, rc); 2030 } 2031 2032 /* register R0 stuff */ 2033 if (pDevIns->fR0Enabled) 2034 { 2035 int rc = PDMDevHlpIOPortRegisterR0(pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET), 2036 1, 0, NULL, "acpiPMTmrRead", 2037 NULL, NULL, "ACPI PM Timer"); 2038 AssertRCReturn(rc, rc); 2039 } 2030 int rc; 2031 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET)); 2032 AssertRCReturn(rc, rc); 2033 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2)); 2034 AssertRCReturn(rc, rc); 2035 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET)); 2036 AssertRCReturn(rc, rc); 2037 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET)); 2038 AssertRCReturn(rc, rc); 2039 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET)); 2040 AssertRCReturn(rc, rc); 2041 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2)); 2040 2042 2041 2043 return VINF_SUCCESS; … … 2043 2045 2044 2046 /** 2045 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to un registerthe PM1a, PM2047 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM 2046 2048 * timer and GPE0 I/O ports. 2047 2049 * … … 2050 2052 * @param pThis The ACPI shared instance data. 2051 2053 */ 2052 static int acpiR3UnregisterPmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis) 2053 { 2054 if (pThis->uPmIoPortBase == 0) 2055 return VINF_SUCCESS; 2056 2057 #define U(offset, cnt) \ 2058 do { \ 2059 int rc = PDMDevHlpIOPortDeregister(pDevIns, acpiR3CalcPmPort(pThis, offset), cnt); \ 2060 AssertRCReturn(rc, rc); \ 2061 } while (0) 2062 #define L (GPE0_BLK_LEN / 2) 2063 2064 U(PM1a_EVT_OFFSET+2, 1); 2065 U(PM1a_EVT_OFFSET, 1); 2066 U(PM1a_CTL_OFFSET, 1); 2067 U(PM_TMR_OFFSET, 1); 2068 U(GPE0_OFFSET + L, L); 2069 U(GPE0_OFFSET, L); 2070 #undef L 2071 #undef U 2072 2054 static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, ACPIState *pThis) 2055 { 2056 if (pThis->uPmIoPortBase != 0) 2057 { 2058 int rc; 2059 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts); 2060 AssertRCReturn(rc, rc); 2061 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn); 2062 AssertRCReturn(rc, rc); 2063 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl); 2064 AssertRCReturn(rc, rc); 2065 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer); 2066 AssertRCReturn(rc, rc); 2067 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts); 2068 AssertRCReturn(rc, rc); 2069 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En); 2070 AssertRCReturn(rc, rc); 2071 } 2073 2072 return VINF_SUCCESS; 2074 2073 } … … 2089 2088 if (NewIoPortBase != pThis->uPmIoPortBase) 2090 2089 { 2091 int rc = acpiR3Un registerPmHandlers(pDevIns, pThis);2090 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis); 2092 2091 if (RT_FAILURE(rc)) 2093 2092 return rc; … … 2095 2094 pThis->uPmIoPortBase = NewIoPortBase; 2096 2095 2097 rc = acpiR3 RegisterPmHandlers(pDevIns, pThis);2096 rc = acpiR3MapPmIoPorts(pDevIns, pThis); 2098 2097 if (RT_FAILURE(rc)) 2099 2098 return rc; … … 2112 2111 * @callback_method_impl{FNIOMIOPORTOUT, SMBus} 2113 2112 */ 2114 PDMBOTHCBDECL(int) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 2115 { 2116 ACPIState *pThis = (ACPIState *)pvUser; 2117 2118 LogFunc(("Port=%#x u32=%#x cb=%u\n", Port, u32, cb)); 2119 uint8_t off = Port & 0x000f; 2113 PDMBOTHCBDECL(int) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 2114 { 2115 RT_NOREF(pvUser); 2116 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 2117 2118 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb)); 2119 uint8_t off = offPort & 0x000f; 2120 2120 if ( (cb != 1 && off <= SMBSHDWCMD_OFF) 2121 2121 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF))) 2122 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb,Port, u32);2122 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32); 2123 2123 2124 2124 DEVACPI_LOCK_R3(pDevIns, pThis); … … 2200 2200 * @callback_method_impl{FNIOMIOPORTIN, SMBus} 2201 2201 */ 2202 PDMBOTHCBDECL(int) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)2203 { 2204 RT_NOREF 1(pDevIns);2205 ACPIState *pThis = (ACPIState *)pvUser;2202 PDMBOTHCBDECL(int) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 2203 { 2204 RT_NOREF(pvUser); 2205 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 2206 2206 2207 2207 int rc = VINF_SUCCESS; 2208 LogFunc((" Port=%#x cb=%u\n",Port, cb));2209 uint8_t off = Port & 0x000f;2208 LogFunc(("offPort=%#x cb=%u\n", offPort, cb)); 2209 uint8_t off = offPort & 0x000f; 2210 2210 if ( (cb != 1 && off <= SMBSHDWCMD_OFF) 2211 2211 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF))) … … 2260 2260 2261 2261 DEVACPI_UNLOCK(pDevIns, pThis); 2262 LogFunc((" Port=%#x u32=%#x cb=%u rc=%Rrc\n",Port, *pu32, cb, rc));2262 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, rc)); 2263 2263 return rc; 2264 2264 } … … 2516 2516 2517 2517 /* 2518 * Un register PM handlers, will register withactual base after state2518 * Unmap PM I/O ports, will remap it with the actual base after state 2519 2519 * successfully loaded. 2520 2520 */ 2521 int rc = acpiR3Un registerPmHandlers(pDevIns, pThis);2521 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis); 2522 2522 if (RT_FAILURE(rc)) 2523 2523 return rc; … … 2557 2557 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat), 2558 2558 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH); 2559 rc = acpiR3 RegisterPmHandlers(pDevIns, pThis);2559 rc = acpiR3MapPmIoPorts(pDevIns, pThis); 2560 2560 if (RT_FAILURE(rc)) 2561 2561 return rc; … … 3978 3978 3979 3979 /* 3980 * Register I/O ports.3980 * Register the PM I/O ports. These can be unmapped and remapped. 3981 3981 */ 3982 rc = acpiR3RegisterPmHandlers(pDevIns, pThis); 3982 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/, 3983 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts); 3983 3984 AssertRCReturn(rc, rc); 3984 3985 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/, 3986 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn); 3987 AssertRCReturn(rc, rc); 3988 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/, 3989 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl); 3990 AssertRCReturn(rc, rc); 3991 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/, 3992 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer); 3993 AssertRCReturn(rc, rc); 3994 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/, 3995 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts); 3996 AssertRCReturn(rc, rc); 3997 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/, 3998 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En); 3999 AssertRCReturn(rc, rc); 4000 rc = acpiR3MapPmIoPorts(pDevIns, pThis); 4001 AssertRCReturn(rc, rc); 4002 4003 /* 4004 * Register the .. I/O ports. 4005 */ 3985 4006 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis); 3986 4007 AssertRCReturn(rc, rc); 3987 4008 3988 #define R(addr, cnt, writer, reader, description) \ 4009 /* 4010 * Register the .. I/O ports. 4011 */ 4012 #define R(a_uIoPort, a_cPorts, writer, reader, description) \ 3989 4013 do { \ 3990 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, pThis, writer, reader, NULL, NULL, description); \4014 rc = PDMDevHlpIOPortRegister(pDevIns, (a_uIoPort), (a_cPorts), pThis, writer, reader, NULL, NULL, description); \ 3991 4015 AssertRCReturn(rc, rc); \ 3992 4016 } while (0) … … 4096 4120 { 4097 4121 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 4098 //PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);4122 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE); 4099 4123 4100 4124 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns)); 4125 AssertRCReturn(rc, rc); 4126 4127 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */ 4128 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL); 4101 4129 AssertRCReturn(rc, rc); 4102 4130
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