Changeset 82031 in vbox

Timestamp:

Nov 20, 2019 4:11:16 PM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

134835

Message:

APIC: Converted the timer pointers to timer handles. This requires PPDMDEVINS to be accessible when called directly from the VMM, so adding pointers to the APIC specific GVM and VM structures. bugref:9218

Location:

trunk

Files:

• include/VBox/vmm/gvm.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/APICAll.cpp (modified) (21 diffs)
• src/VBox/VMM/VMMR3/APIC.cpp (modified) (8 diffs)
• src/VBox/VMM/include/APICInternal.h (modified) (5 diffs)
• src/VBox/VMM/testcase/tstVMStruct.h (modified) (1 diff)

trunk/include/VBox/vmm/gvm.h

@@ -213 +213 @@
     } iomr0;
 
+    union
+    {
+#if defined(VMM_INCLUDED_SRC_include_APICInternal_h) && defined(IN_RING0)
+        struct APICR0PERVM  s;
+#endif
+        uint8_t             padding[64];
+    } apicr0;
+
     /** Padding so aCpus starts on a page boundrary.  */
 #ifdef VBOX_WITH_NEM_R0
-    uint8_t         abPadding2[4096 - 64 - 256 - 512 - 256 - 64 - 1792 - 512 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
-#else
-    uint8_t         abPadding2[4096 - 64 - 256 - 512       - 64 - 1792 - 512 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
+    uint8_t         abPadding2[4096 - 64 - 256 - 512 - 256 - 64 - 1792 - 512 - 64 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
+#else
+    uint8_t         abPadding2[4096 - 64 - 256 - 512       - 64 - 1792 - 512 - 64 - sizeof(PGVMCPU) * VMM_MAX_CPU_COUNT];
 #endif
 

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -1384 +1384 @@
  *
  * @returns VBox status code.
+ * @param   pDevIns         The device instance.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   rcBusy          The busy return code for the timer critical section.
  * @param   puValue         Where to store the LVT timer CCR.
  */
-static VBOXSTRICTRC apicGetTimerCcr(PVMCPUCC pVCpu, int rcBusy, uint32_t *puValue)
+static VBOXSTRICTRC apicGetTimerCcr(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, int rcBusy, uint32_t *puValue)
 {
     VMCPU_ASSERT_EMT(pVCpu);
@@ -1411 +1412 @@
      * We also need to lock before reading the timer CCR, see apicR3TimerCallback().
      */
-    PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
-    PTMTIMER  pTimer   = pApicCpu->CTX_SUFF(pTimer);
-
-    int rc = TMTimerLock(pTimer, rcBusy);
+    PCAPICCPU       pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+    TMTIMERHANDLE   hTimer   = pApicCpu->hTimer;
+
+    int rc = PDMDevHlpTimerLock(pDevIns, hTimer, rcBusy);
     if (rc == VINF_SUCCESS)
     {
@@ -1421 +1422 @@
         if (uCurrentCount)
         {
-            uint64_t const cTicksElapsed = TMTimerGet(pApicCpu->CTX_SUFF(pTimer)) - pApicCpu->u64TimerInitial;
-            TMTimerUnlock(pTimer);
+            uint64_t const cTicksElapsed = PDMDevHlpTimerGet(pDevIns, hTimer) - pApicCpu->u64TimerInitial;
+            PDMDevHlpTimerUnlock(pDevIns, hTimer);
             uint8_t  const uTimerShift   = apicGetTimerShift(pXApicPage);
             uint64_t const uDelta        = cTicksElapsed >> uTimerShift;
@@ -1429 +1430 @@
         }
         else
-            TMTimerUnlock(pTimer);
+            PDMDevHlpTimerUnlock(pDevIns, hTimer);
     }
     return rc;
@@ -1439 +1440 @@
  *
  * @returns Strict VBox status code.
+ * @param   pDevIns         The device instance.
  * @param   pVCpu           The cross context virtual CPU structure.
  * @param   rcBusy          The busy return code for the timer critical section.
  * @param   uInitialCount   The timer ICR.
  */
-static VBOXSTRICTRC apicSetTimerIcr(PVMCPUCC pVCpu, int rcBusy, uint32_t uInitialCount)
+static VBOXSTRICTRC apicSetTimerIcr(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, int rcBusy, uint32_t uInitialCount)
 {
     VMCPU_ASSERT_EMT(pVCpu);
@@ -1450 +1452 @@
     PAPICCPU   pApicCpu   = VMCPU_TO_APICCPU(pVCpu);
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
-    PTMTIMER   pTimer     = pApicCpu->CTX_SUFF(pTimer);
 
     Log2(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
@@ -1465 +1466 @@
      * timer ICR. We rely on CCR being consistent in apicGetTimerCcr().
      */
-    int rc = TMTimerLock(pTimer, rcBusy);
+    TMTIMERHANDLE hTimer = pApicCpu->hTimer;
+    int rc = PDMDevHlpTimerLock(pDevIns, hTimer, rcBusy);
     if (rc == VINF_SUCCESS)
     {
@@ -1474 +1476 @@
         else
             apicStopTimer(pVCpu);
-        TMTimerUnlock(pTimer);
+        PDMDevHlpTimerUnlock(pDevIns, hTimer);
     }
     return rc;
@@ -1588 +1590 @@
  * Hints TM about the APIC timer frequency.
  *
+ * @param   pDevIns         The device instance.
  * @param   pApicCpu        The APIC CPU state.
  * @param   uInitialCount   The new initial count.
@@ -1593 +1596 @@
  * @thread  Any.
  */
-void apicHintTimerFreq(PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift)
+void apicHintTimerFreq(PPDMDEVINS pDevIns, PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift)
 {
     Assert(pApicCpu);
@@ -1604 +1607 @@
         {
             uint64_t cTicksPerPeriod = (uint64_t)uInitialCount << uTimerShift;
-            uHz = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer)) / cTicksPerPeriod;
+            uHz = PDMDevHlpTimerGetFreq(pDevIns, pApicCpu->hTimer) / cTicksPerPeriod;
         }
         else
             uHz = 0;
 
-        TMTimerSetFrequencyHint(pApicCpu->CTX_SUFF(pTimer), uHz);
+        PDMDevHlpTimerSetFrequencyHint(pDevIns, pApicCpu->hTimer, uHz);
         pApicCpu->uHintedTimerInitialCount = uInitialCount;
         pApicCpu->uHintedTimerShift = uTimerShift;
@@ -1698 +1701 @@
         {
             Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
-            rc = apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue);
+            rc = apicGetTimerCcr(pDevIns, pVCpu, VINF_IOM_R3_MMIO_READ, &uValue);
             break;
         }
@@ -1766 +1769 @@
         case XAPIC_OFF_TIMER_ICR:
         {
-            rcStrict = apicSetTimerIcr(pVCpu, VINF_IOM_R3_MMIO_WRITE, uValue);
+            rcStrict = apicSetTimerIcr(pDevIns, pVCpu, VINF_IOM_R3_MMIO_WRITE, uValue);
             break;
         }
@@ -1910 +1913 @@
             {
                 uint32_t uValue;
-                rcStrict = apicGetTimerCcr(pVCpu, VINF_CPUM_R3_MSR_READ, &uValue);
+                rcStrict = apicGetTimerCcr(VMCPU_TO_DEVINS(pVCpu), pVCpu, VINF_CPUM_R3_MSR_READ, &uValue);
                 *pu64Value = uValue;
                 break;
@@ -2011 +2014 @@
     { /* likely */ }
     else
-    {
         return apicMsrAccessError(pVCpu, u32Reg, pApic->enmMaxMode == PDMAPICMODE_NONE ?
-                                                 APICMSRACCESS_WRITE_DISALLOWED_CONFIG : APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
-    }
+                                  APICMSRACCESS_WRITE_DISALLOWED_CONFIG : APICMSRACCESS_WRITE_RSVD_OR_UNKNOWN);
 
 #ifndef IN_RING3
@@ -2088 +2089 @@
             case MSR_IA32_X2APIC_TIMER_ICR:
             {
-                rcStrict = apicSetTimerIcr(pVCpu, VINF_CPUM_R3_MSR_WRITE, u32Value);
+                rcStrict = apicSetTimerIcr(VMCPU_TO_DEVINS(pVCpu), pVCpu, VINF_CPUM_R3_MSR_WRITE, u32Value);
                 break;
             }
@@ -2611 +2612 @@
     {
         PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
-        *pu64Value = TMTimerGetFreq(pApicCpu->CTX_SUFF(pTimer));
+        *pu64Value = PDMDevHlpTimerGetFreq(VMCPU_TO_DEVINS(pVCpu), pApicCpu->hTimer);
         return VINF_SUCCESS;
     }
@@ -3159 +3160 @@
 {
     Assert(pVCpu);
-    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
-    Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
+    PAPICCPU   pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+    PPDMDEVINS pDevIns  = VMCPU_TO_DEVINS(pVCpu);
+    Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pApicCpu->hTimer));
     Assert(uInitialCount > 0);
 
@@ -3176 +3178 @@
      * tick.
      */
-    PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
-    TMTimerSetRelative(pTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
-    apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
+    PDMDevHlpTimerSetRelative(pDevIns, pApicCpu->hTimer, cTicksToNext, &pApicCpu->u64TimerInitial);
+    apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
 }
 
@@ -3191 +3192 @@
 {
     Assert(pVCpu);
-    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
-    Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
+    PAPICCPU   pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+    PPDMDEVINS pDevIns  = VMCPU_TO_DEVINS(pVCpu);
+    Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pApicCpu->hTimer));
 
     Log2(("APIC%u: apicStopTimer\n", pVCpu->idCpu));
 
-    PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);
-    TMTimerStop(pTimer);    /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
+    PDMDevHlpTimerStop(pDevIns, pApicCpu->hTimer); /* This will reset the hint, no need to explicitly call TMTimerSetFrequencyHint(). */
     pApicCpu->uHintedTimerInitialCount = 0;
     pApicCpu->uHintedTimerShift = 0;
@@ -3507 +3508 @@
     PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     PAPICDEV pThis = PDMDEVINS_2_DATA(pDevIns, PAPICDEV);
+    PVMCC    pVM   = PDMDevHlpGetVM(pDevIns);
+
+    pVM->apicr0.s.pDevInsR0 = pDevIns;
 
     int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, apicWriteMmio, apicReadMmio, NULL /*pvUser*/);

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -930 +930 @@
         pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
 
-    rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
+    rc = PDMDevHlpTimerLoad(pDevIns, pApicCpu->hTimer, pSSM);
     AssertRCReturn(rc, rc);
     Assert(pApicCpu->uHintedTimerInitialCount == 0);
     Assert(pApicCpu->uHintedTimerShift == 0);
-    if (TMTimerIsActive(pApicCpu->pTimerR3))
+    if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
     {
         uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
-        apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
+        apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
     }
 
@@ -981 +981 @@
         /* Save the timer. */
         pHlp->pfnSSMPutU64(pSSM, pApicCpu->u64TimerInitial);
-        TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
+        PDMDevHlpTimerSave(pDevIns, pApicCpu->hTimer, pSSM);
 
         /* Save the LINT0, LINT1 interrupt line states. */
@@ -1061 +1061 @@
             /* Load the timer. */
             rc = pHlp->pfnSSMGetU64(pSSM, &pApicCpu->u64TimerInitial);     AssertRCReturn(rc, rc);
-            rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);           AssertRCReturn(rc, rc);
+            rc = PDMDevHlpTimerLoad(pDevIns, pApicCpu->hTimer, pSSM);      AssertRCReturn(rc, rc);
             Assert(pApicCpu->uHintedTimerShift == 0);
             Assert(pApicCpu->uHintedTimerInitialCount == 0);
-            if (TMTimerIsActive(pApicCpu->pTimerR3))
+            if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
             {
                 PCXAPICPAGE    pXApicPage    = VMCPU_TO_CXAPICPAGE(pVCpu);
                 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
                 uint8_t const  uTimerShift   = apicGetTimerShift(pXApicPage);
-                apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
+                apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
             }
 
@@ -1116 +1116 @@
 static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
 {
-    PVMCPU pVCpu = (PVMCPU)pvUser;
-    Assert(TMTimerIsLockOwner(pTimer));
+    PVMCPU      pVCpu    = (PVMCPU)pvUser;
+    PAPICCPU    pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+    Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pApicCpu->hTimer));
     Assert(pVCpu);
     LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
@@ -1125 +1126 @@
     uint32_t const uLvtTimer  = pXApicPage->lvt_timer.all.u32LvtTimer;
 #ifdef VBOX_WITH_STATISTICS
-    PAPICCPU       pApicCpu   = VMCPU_TO_APICCPU(pVCpu);
     STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
 #endif
@@ -1183 +1183 @@
         PAPICCPU pApicCpu  = VMCPU_TO_APICCPU(pVCpuDest);
 
-        if (TMTimerIsActive(pApicCpu->pTimerR3))
-            TMTimerStop(pApicCpu->pTimerR3);
+        if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
+            PDMDevHlpTimerStop(pDevIns, pApicCpu->hTimer);
 
         apicResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
@@ -1411 +1411 @@
     pApicDev->pDevInsR3 = pDevIns;
 
+    pApic->pDevInsR3    = pDevIns;
     pApic->pApicDevR3   = pApicDev;
     pApic->pApicDevR0   = PDMINS_2_DATA_R0PTR(pDevIns);
@@ -1492 +1493 @@
         PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
         RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
-        rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
-                                    pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
+        rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
+                                  pApicCpu->szTimerDesc, &pApicCpu->hTimer);
         AssertRCReturn(rc, rc);
-        pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
     }
 

trunk/src/VBox/VMM/include/APICInternal.h

@@ -58 +58 @@
 #define VM_TO_APIC(a_pVM)                    (&(a_pVM)->apic.s)
 #define VM_TO_APICDEV(a_pVM)                 CTX_SUFF(VM_TO_APIC(a_pVM)->pApicDev)
+#ifdef IN_RING3
+# define VMCPU_TO_DEVINS(a_pVCpu)           ((a_pVCpu)->pVMR3->apic.s.pDevInsR3)
+#elif defined(IN_RING0)
+# define VMCPU_TO_DEVINS(a_pVCpu)           ((a_pVCpu)->pGVM->apicr0.s.pDevInsR0)
+#endif
 
 #define APICCPU_TO_XAPICPAGE(a_ApicCpu)      ((PXAPICPAGE)(CTX_SUFF((a_ApicCpu)->pvApicPage)))
@@ -1164 +1169 @@
 typedef APICDEV const *PCAPICDEV;
 
+
+/**
+ * The APIC GVM instance data.
+ */
+typedef struct APICR0PERVM
+{
+    /** The ring-0 device instance. */
+    PPDMDEVINSR0                pDevInsR0;
+} APICR0PERVM;
+
+
 /**
  * APIC VM Instance data.
@@ -1175 +1191 @@
     /** The APIC device - R3 ptr. */
     R3PTRTYPE(PAPICDEV)         pApicDevR3;
+    /** The ring-3 device instance. */
+    PPDMDEVINSR3                pDevInsR3;
     /** @} */
 
@@ -1283 +1301 @@
     /** @name The APIC timer.
      * @{ */
-    /** The timer - R0 ptr. */
-    PTMTIMERR0                  pTimerR0;
-    /** The timer - R3 ptr. */
-    PTMTIMERR3                  pTimerR3;
+    /** The timer. */
+    TMTIMERHANDLE               hTimer;
     /** The time stamp when the timer was initialized. */
     uint64_t                    u64TimerInitial;
@@ -1412 +1428 @@
 const char                   *apicGetDestShorthandName(XAPICDESTSHORTHAND enmDestShorthand);
 const char                   *apicGetTimerModeName(XAPICTIMERMODE enmTimerMode);
-void                          apicHintTimerFreq(PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift);
+void                          apicHintTimerFreq(PPDMDEVINS pDevIns, PAPICCPU pApicCpu, uint32_t uInitialCount, uint8_t uTimerShift);
 APICMODE                      apicGetMode(uint64_t uApicBaseMsr);
 

trunk/src/VBox/VMM/testcase/tstVMStruct.h

@@ -1408 +1408 @@
     GEN_CHECK_OFF(APICCPU, pvApicPibR3);
     GEN_CHECK_OFF(APICCPU, ApicPibLevel);
-    GEN_CHECK_OFF(APICCPU, pTimerR0);
-    GEN_CHECK_OFF(APICCPU, pTimerR3);
+    GEN_CHECK_OFF(APICCPU, hTimer);
     GEN_CHECK_OFF(APICCPU, TimerCritSect);