Changeset 82089 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Nov 21, 2019 10:18:59 PM (5 years ago)
- Location:
- trunk/src/VBox/Devices/Graphics
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r82088 r82089 336 336 #ifdef IN_RING3 337 337 # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS) 338 static FNPGMPHYSHANDLER vmsvgaR3F IFOAccessHandler;338 static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler; 339 339 # endif 340 340 # ifdef DEBUG_GMR_ACCESS 341 static FNPGMPHYSHANDLER vmsvgaR3G MRAccessHandler;341 static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler; 342 342 # endif 343 343 #endif … … 541 541 SSMFIELD_ENTRY_TERM() 542 542 }; 543 544 static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces); 545 static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass); 546 static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM); 547 548 VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen) 543 #endif /* IN_RING3 */ 544 545 546 /********************************************************************************************************************************* 547 * Internal Functions * 548 *********************************************************************************************************************************/ 549 #ifdef IN_RING3 550 static void vmsvgaR3SetTraces(PVGASTATE pThis, bool fTraces); 551 static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass); 552 static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM); 553 #endif /* IN_RING3 */ 554 555 556 557 #ifdef IN_RING3 558 VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATE pThis, uint32_t idScreen) 549 559 { 550 560 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State; … … 557 567 return NULL; 558 568 } 559 560 569 #endif /* IN_RING3 */ 561 570 … … 640 649 * @param u32Cmd FIFO command 641 650 */ 642 static const char *vmsvga FIFOCmdToString(uint32_t u32Cmd)651 static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd) 643 652 { 644 653 switch (u32Cmd) … … 715 724 716 725 /** @todo Test how it interacts with multiple screen objects. */ 717 VMSVGASCREENOBJECT *pScreen = vmsvga GetScreenObject(pThis, idScreen);726 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, idScreen); 718 727 uint32_t const uWidth = pScreen ? pScreen->cWidth : 0; 719 728 uint32_t const uHeight = pScreen ? pScreen->cHeight : 0; … … 1281 1290 * @param pThis VMSVGA State 1282 1291 */ 1283 static int vmsvga ChangeMode(PVGASTATE pThis)1292 static int vmsvgaR3ChangeMode(PVGASTATE pThis) 1284 1293 { 1285 1294 int rc; … … 1408 1417 } 1409 1418 1410 int vmsvga UpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)1419 int vmsvgaR3UpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h) 1411 1420 { 1412 1421 VBVACMDHDR cmd; … … 1433 1442 * @param fState The busy state. 1434 1443 */ 1435 DECLINLINE(void) vmsvga SafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)1444 DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState) 1436 1445 { 1437 1446 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState); … … 1457 1466 * @param pThis VMSVGA State 1458 1467 */ 1459 DECLINLINE(void) vmsvga UpdatePitch(PVGASTATE pThis)1468 DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis) 1460 1469 { 1461 1470 uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO); … … 1526 1535 } 1527 1536 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32)); 1528 /* Check if the guest uses legacy registers. See vmsvga ChangeMode */1537 /* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */ 1529 1538 switch (idxReg) 1530 1539 { … … 1587 1596 1588 1597 /* Disable or enable dirty page tracking according to the current fTraces value. */ 1589 vmsvga SetTraces(pThis, !!pThis->svga.fTraces);1598 vmsvgaR3SetTraces(pThis, !!pThis->svga.fTraces); 1590 1599 1591 1600 /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */ … … 1601 1610 1602 1611 /* Enable dirty page tracking again when going into legacy mode. */ 1603 vmsvga SetTraces(pThis, true);1612 vmsvgaR3SetTraces(pThis, true); 1604 1613 1605 1614 /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */ … … 1621 1630 #if defined(IN_RING3) || defined(IN_RING0) 1622 1631 pThis->svga.uWidth = u32; 1623 vmsvga UpdatePitch(pThis);1632 vmsvgaHCUpdatePitch(pThis); 1624 1633 if (pThis->svga.fEnabled) 1625 1634 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE); … … 1653 1662 #if defined(IN_RING3) || defined(IN_RING0) 1654 1663 pThis->svga.uBpp = u32; 1655 vmsvga UpdatePitch(pThis);1664 vmsvgaHCUpdatePitch(pThis); 1656 1665 if (pThis->svga.fEnabled) 1657 1666 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE); … … 1674 1683 if (!pThis->svga.fConfigured) 1675 1684 pThis->svga.fTraces = true; 1676 vmsvga SetTraces(pThis, !!pThis->svga.fTraces);1685 vmsvgaR3SetTraces(pThis, !!pThis->svga.fTraces); 1677 1686 #else 1678 1687 rc = VINF_IOM_R3_IOPORT_WRITE; … … 1689 1698 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO); 1690 1699 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN])) 1691 vmsvga SafeFifoBusyRegUpdate(pThis, true);1700 vmsvgaHCSafeFifoBusyRegUpdate(pThis, true); 1692 1701 1693 1702 /* Kick the FIFO thread to start processing commands again. */ … … 1783 1792 1784 1793 /* Free the old GMR if present. */ 1785 vmsvga GMRFree(pThis, idGMR);1794 vmsvgaR3GmrFree(pThis, idGMR); 1786 1795 1787 1796 /* Just undefine the GMR? */ … … 1864 1873 1865 1874 #ifdef IN_RING3 1866 vmsvga SetTraces(pThis, !!u32);1875 vmsvgaR3SetTraces(pThis, !!u32); 1867 1876 #else 1868 1877 rc = VINF_IOM_R3_IOPORT_WRITE; … … 2043 2052 * @param fWriteAccess Read or write access 2044 2053 */ 2045 static int vmsvga DebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)2054 static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess) 2046 2055 { 2047 2056 RT_NOREF(pVM); … … 2392 2401 */ 2393 2402 static DECLCALLBACK(VBOXSTRICTRC) 2394 vmsvgaR3F IFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,2403 vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, 2395 2404 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser) 2396 2405 { … … 2413 2422 */ 2414 2423 Assert(GCPhys >= pThis->svga.GCPhysFIFO); 2415 rc = vmsvga DebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);2424 rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE); 2416 2425 # elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) 2417 2426 /* … … 2449 2458 */ 2450 2459 static DECLCALLBACK(VBOXSTRICTRC) 2451 vmsvgaR3G MRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,2460 vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, 2452 2461 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser) 2453 2462 { … … 2457 2466 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin); 2458 2467 2459 Log(("vmsvgaR3G MRAccessHandler: GMR access to page %RGp\n", GCPhys));2468 Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys)); 2460 2469 2461 2470 for (uint32_t i = 0; i < pThis->svga.cGMR; ++i) … … 2476 2485 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys); 2477 2486 AssertRC(rc); 2478 goto end;2487 return VINF_PGM_HANDLER_DO_DEFAULT; 2479 2488 } 2480 2489 } 2481 2490 } 2482 2491 } 2483 end: 2492 2484 2493 return VINF_PGM_HANDLER_DO_DEFAULT; 2485 2494 } 2486 2495 2487 /* Callback handler for VMR3ReqCallWaitU */2488 static DECLCALLBACK(int) vmsvgaR egisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)2496 /** Callback handler for VMR3ReqCallWaitU */ 2497 static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId) 2489 2498 { 2490 2499 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 2503 2512 } 2504 2513 2505 /* Callback handler for VMR3ReqCallWaitU */2506 static DECLCALLBACK(int) vmsvga DeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)2514 /** Callback handler for VMR3ReqCallWaitU */ 2515 static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId) 2507 2516 { 2508 2517 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 2518 2527 } 2519 2528 2520 /* Callback handler for VMR3ReqCallWaitU */2521 static DECLCALLBACK(int) vmsvgaR esetGMRHandlers(PVGASTATE pThis)2529 /** Callback handler for VMR3ReqCallWaitU */ 2530 static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis) 2522 2531 { 2523 2532 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State; … … 2564 2573 { 2565 2574 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData)); 2566 # ifdef LOG_ENABLED2575 # ifdef LOG_ENABLED 2567 2576 if (LogIs2Enabled()) 2568 2577 { … … 2605 2614 } 2606 2615 } 2607 # endif2616 # endif 2608 2617 2609 2618 int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData); … … 2880 2889 { 2881 2890 case VMSVGA_FIFO_EXTCMD_RESET: 2882 Log(("vmsvga FIFOLoop: reset the fifo thread.\n"));2891 Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n")); 2883 2892 Assert(pThis->svga.pvFIFOExtCmdParam == NULL); 2884 2893 # ifdef VBOX_WITH_VMSVGA3D … … 2892 2901 2893 2902 case VMSVGA_FIFO_EXTCMD_TERMINATE: 2894 Log(("vmsvga FIFOLoop: terminate the fifo thread.\n"));2903 Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n")); 2895 2904 Assert(pThis->svga.pvFIFOExtCmdParam == NULL); 2896 2905 # ifdef VBOX_WITH_VMSVGA3D … … 2905 2914 case VMSVGA_FIFO_EXTCMD_SAVESTATE: 2906 2915 { 2907 Log(("vmsvga FIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));2916 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n")); 2908 2917 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam; 2909 2918 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM)); 2910 vmsvga SaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);2919 vmsvgaR3SaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM); 2911 2920 # ifdef VBOX_WITH_VMSVGA3D 2912 2921 if (pThis->svga.f3DEnabled) … … 2918 2927 case VMSVGA_FIFO_EXTCMD_LOADSTATE: 2919 2928 { 2920 Log(("vmsvga FIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));2929 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n")); 2921 2930 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam; 2922 2931 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState)); 2923 vmsvga LoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);2932 vmsvgaR3LoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass); 2924 2933 # ifdef VBOX_WITH_VMSVGA3D 2925 2934 if (pThis->svga.f3DEnabled) … … 2933 2942 # ifdef VBOX_WITH_VMSVGA3D 2934 2943 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam; 2935 Log(("vmsvga FIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));2944 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid)); 2936 2945 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid); 2937 2946 # endif … … 2967 2976 * milliseconds. 2968 2977 */ 2969 static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait) 2978 static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, 2979 uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait) 2970 2980 { 2971 2981 Assert(cMsWait >= RT_MS_1SEC * 5); … … 3058 3068 * @param offFifoMin The start byte offset of the command FIFO. 3059 3069 */ 3060 static void vmsvga FifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)3070 static void vmsvgaR3FifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin) 3061 3071 { 3062 3072 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO); 3063 3073 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin)) 3064 vmsvga SafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);3074 vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0); 3065 3075 3066 3076 /* Wake up any waiting EMTs. */ 3067 3077 if (pSVGAState->cBusyDelayedEmts > 0) 3068 3078 { 3069 # ifdef VMSVGA_USE_EMT_HALT_CODE3079 # ifdef VMSVGA_USE_EMT_HALT_CODE 3070 3080 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3); 3071 3081 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts); … … 3077 3087 VMR3NotifyCpuDeviceReady(pVM, idCpu); 3078 3088 } 3079 # else3089 # else 3080 3090 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts); 3081 3091 AssertRC(rc2); 3082 # endif3092 # endif 3083 3093 } 3084 3094 } … … 3105 3115 * statistics collection. 3106 3116 */ 3107 static void *vmsvga FIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,3108 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,3109 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,3110 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)3117 static void *vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO, 3118 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax, 3119 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead, 3120 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns) 3111 3121 { 3112 3122 Assert(pbBounceBuf); … … 3159 3169 { 3160 3170 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors); 3161 LogRelMax(16, ("vmsvga FIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",3171 LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n", 3162 3172 offNextCmd, offFifoMin, offFifoMax)); 3163 3173 cbAfter = offFifoMax - offCurrentCmd; … … 3173 3183 { 3174 3184 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors); 3175 LogRelMax(16, ("vmsvga FIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",3185 LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n", 3176 3186 offNextCmd, offFifoMin, offFifoMax)); 3177 3187 cbBefore = 0; … … 3248 3258 */ 3249 3259 static uint32_t 3250 vmsvga FIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,3251 uint32_t offFifoMin, uint32_t uCursorUpdateCount,3252 uint32_t *pxLast, uint32_t *pyLast, uint32_t *pfLastVisible)3260 vmsvgaR3FifoUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO, 3261 uint32_t offFifoMin, uint32_t uCursorUpdateCount, 3262 uint32_t *pxLast, uint32_t *pyLast, uint32_t *pfLastVisible) 3253 3263 { 3254 3264 /* … … 3296 3306 else if (*pfLastVisible != fVisible) 3297 3307 { 3298 LogRel2(("vmsvga FIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));3308 LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y)); 3299 3309 *pfLastVisible = fVisible; 3300 3310 pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL); … … 3321 3331 * @param uLastCursorCount The last cursor update counter value. 3322 3332 */ 3323 DECLINLINE(bool) vmsvga FIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)3333 DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount) 3324 3334 { 3325 3335 if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP]) … … 3339 3349 * @param pThis The VGA state. 3340 3350 */ 3341 void vmsvga FIFOWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis)3351 void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis) 3342 3352 { 3343 3353 /* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have … … 3345 3355 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3; 3346 3356 AssertReturnVoid(pFIFO); 3347 if ( vmsvga FIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))3357 if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount)) 3348 3358 && pThis->svga.fFIFOThreadSleeping) 3349 3359 { … … 3355 3365 3356 3366 3357 /* The async FIFO handling thread. */ 3358 static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread) 3367 /** 3368 * @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.} 3369 */ 3370 static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread) 3359 3371 { 3360 3372 PVGASTATE pThis = (PVGASTATE)pThread->pvUser; … … 3384 3396 /* 3385 3397 * Signal the semaphore to make sure we don't wait for 250ms after a 3386 * suspend & resume scenario (see vmsvga FIFOGetCmdPayload).3398 * suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload). 3387 3399 */ 3388 3400 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem); … … 3429 3441 * The FIFO loop. 3430 3442 */ 3431 LogFlow(("vmsvga FIFOLoop: started loop\n"));3443 LogFlow(("vmsvgaR3FifoLoop: started loop\n")); 3432 3444 bool fBadOrDisabledFifo = false; 3433 3445 while (pThread->enmState == PDMTHREADSTATE_RUNNING) … … 3446 3458 */ 3447 3459 if ( fBadOrDisabledFifo 3448 || !vmsvga FIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))3460 || !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount)) 3449 3461 { 3450 3462 ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true); … … 3459 3471 # endif 3460 3472 if ( !fBadOrDisabledFifo 3461 && vmsvga FIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))3473 && vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount)) 3462 3474 rc = VINF_SUCCESS; 3463 3475 else … … 3472 3484 if (pThread->enmState != PDMTHREADSTATE_RUNNING) 3473 3485 { 3474 LogFlow(("vmsvga FIFOLoop: thread state %x\n", pThread->enmState));3486 LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState)); 3475 3487 break; 3476 3488 } … … 3481 3493 if (rc == VERR_TIMEOUT) 3482 3494 { 3483 if (!vmsvga FIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))3495 if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount)) 3484 3496 { 3485 3497 cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep); … … 3488 3500 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout); 3489 3501 3490 Log(("vmsvga FIFOLoop: timeout\n"));3502 Log(("vmsvgaR3FifoLoop: timeout\n")); 3491 3503 } 3492 else if (vmsvga FIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))3504 else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount)) 3493 3505 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken); 3494 3506 cMsSleep = cMsMinSleep; 3495 3507 3496 Log(("vmsvga FIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));3497 Log(("vmsvga FIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));3498 Log(("vmsvga FIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));3508 Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY])); 3509 Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX])); 3510 Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP])); 3499 3511 3500 3512 /* … … 3513 3525 || !pThis->svga.fConfigured) 3514 3526 { 3515 vmsvga FifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);3527 vmsvgaR3FifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]); 3516 3528 fBadOrDisabledFifo = true; 3517 3529 cMsSleep = cMsMaxSleep; /* cheat */ … … 3538 3550 { 3539 3551 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors); 3540 LogRelMax(8, ("vmsvga FIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));3541 vmsvga FifoSetNotBusy(pThis, pSVGAState, offFifoMin);3552 LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax)); 3553 vmsvgaR3FifoSetNotBusy(pThis, pSVGAState, offFifoMin); 3542 3554 fBadOrDisabledFifo = true; 3543 3555 continue; … … 3547 3559 { 3548 3560 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors); 3549 LogRelMax(8, ("vmsvga FIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));3561 LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd)); 3550 3562 offCurrentCmd &= ~UINT32_C(3); 3551 3563 } … … 3562 3574 else 3563 3575 { 3564 uint32_t const uLastCursorCount = vmsvga FIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,3576 uint32_t const uLastCursorCount = vmsvgaR3FifoUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount, 3565 3577 &xLastCursor, &yLastCursor, &fLastCursorVisible); 3566 3578 ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount); … … 3569 3581 3570 3582 /** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK 3571 * Macro for shortening calls to vmsvga FIFOGetCmdPayload.3583 * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload. 3572 3584 * 3573 3585 * Will break out of the switch on failure. … … 3581 3593 # define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \ 3582 3594 if (1) { \ 3583 (a_PtrVar) = (a_Type *)vmsvga FIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \3584 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \3595 (a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \ 3596 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \ 3585 3597 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \ 3586 3598 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \ 3587 3599 } else do {} while (0) 3588 3600 /** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK 3589 * Macro for shortening calls to vmsvga FIFOGetCmdPayload for refetching the3601 * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the 3590 3602 * buffer after figuring out the actual command size. 3591 3603 * … … 3625 3637 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT)) 3626 3638 { 3627 vmsvga ChangeMode(pThis);3639 vmsvgaR3ChangeMode(pThis); 3628 3640 # ifdef VBOX_WITH_VMSVGA3D 3629 3641 if (pThis->svga.p3dState != NULL) … … 3641 3653 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)]; 3642 3654 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); 3643 LogFlow(("vmsvga FIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",3644 offCurrentCmd / sizeof(uint32_t), vmsvga FIFOCmdToString(enmCmdId), enmCmdId));3655 LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n", 3656 offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId)); 3645 3657 switch (enmCmdId) 3646 3658 { … … 3657 3669 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin)) 3658 3670 { 3659 Log(("vmsvga FIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));3671 Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence)); 3660 3672 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence; 3661 3673 3662 3674 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE) 3663 3675 { 3664 Log(("vmsvga FIFOLoop: any fence irq\n"));3676 Log(("vmsvgaR3FifoLoop: any fence irq\n")); 3665 3677 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE; 3666 3678 } … … 3670 3682 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence) 3671 3683 { 3672 Log(("vmsvga FIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));3684 Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence)); 3673 3685 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL; 3674 3686 } … … 3687 3699 else 3688 3700 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose); 3689 Log(("vmsvga FIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));3701 Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height)); 3690 3702 /** @todo Multiple screens? */ 3691 VMSVGASCREENOBJECT *pScreen = vmsvga GetScreenObject(pThis, 0);3703 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, 0); 3692 3704 AssertBreak(pScreen); 3693 vmsvga UpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);3705 vmsvgaR3UpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height); 3694 3706 break; 3695 3707 } … … 3702 3714 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor); 3703 3715 3704 Log(("vmsvga FIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",3716 Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n", 3705 3717 pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY, 3706 3718 pCursor->andMaskDepth, pCursor->xorMaskDepth)); … … 3732 3744 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor); 3733 3745 3734 Log(("vmsvga FIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));3746 Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY)); 3735 3747 3736 3748 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */ … … 3779 3791 RT_UNTRUSTED_VALIDATED_FENCE(); 3780 3792 uint32_t cmd = *(uint32_t *)(pEscape + 1); 3781 Log(("vmsvga FIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));3793 Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd)); 3782 3794 3783 3795 switch (cmd) … … 3813 3825 } 3814 3826 else 3815 Log(("vmsvga FIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));3827 Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size)); 3816 3828 3817 3829 break; … … 3822 3834 SVGAFifoCmdDefineGMR2 *pCmd; 3823 3835 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd)); 3824 Log(("vmsvga FIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));3836 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages)); 3825 3837 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2); 3826 3838 … … 3833 3845 { 3834 3846 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free); 3835 vmsvga GMRFree(pThis, pCmd->gmrId);3847 vmsvgaR3GmrFree(pThis, pCmd->gmrId); 3836 3848 } 3837 3849 else … … 3845 3857 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */ 3846 3858 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages) 3847 vmsvga GMRFree(pThis, pCmd->gmrId);3859 vmsvgaR3GmrFree(pThis, pCmd->gmrId); 3848 3860 3849 3861 pGMR->cMaxPages = pCmd->numPages; … … 3860 3872 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2); 3861 3873 3862 Log(("vmsvga FIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));3874 Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages)); 3863 3875 AssertBreak(pCmd->gmrId < pThis->svga.cGMR); 3864 3876 RT_UNTRUSTED_VALIDATED_FENCE(); … … 4005 4017 4006 4018 # ifdef DEBUG_GMR_ACCESS 4007 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR egisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);4019 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pThis->pDevInsR3, pCmd->gmrId); 4008 4020 # endif 4009 4021 break; … … 4076 4088 4077 4089 pThis->svga.fGFBRegisters = false; 4078 vmsvga ChangeMode(pThis);4090 vmsvgaR3ChangeMode(pThis); 4079 4091 break; 4080 4092 } … … 4086 4098 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen); 4087 4099 4088 Log(("vmsvga FIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));4100 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId)); 4089 4101 4090 4102 uint32_t const idScreen = pCmd->screenId; … … 4097 4109 pScreen->idScreen = idScreen; 4098 4110 4099 vmsvga ChangeMode(pThis);4111 vmsvgaR3ChangeMode(pThis); 4100 4112 break; 4101 4113 } … … 4107 4119 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb); 4108 4120 4109 Log(("vmsvga FIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));4121 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth)); 4110 4122 pSVGAState->GMRFB.ptr = pCmd->ptr; 4111 4123 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine; … … 4126 4138 RT_UNTRUSTED_VALIDATED_FENCE(); 4127 4139 4128 VMSVGASCREENOBJECT *pScreen = vmsvga GetScreenObject(pThis, pCmd->destScreenId);4140 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, pCmd->destScreenId); 4129 4141 AssertBreak(pScreen); 4130 4142 … … 4139 4151 screenRect.bottom = pScreen->cHeight; 4140 4152 SVGASignedRect clipRect = pCmd->destRect; 4141 vmsvga ClipRect(&screenRect, &clipRect);4153 vmsvgaR3ClipRect(&screenRect, &clipRect); 4142 4154 RT_UNTRUSTED_VALIDATED_FENCE(); 4143 4155 … … 4153 4165 4154 4166 /* Copy the defined by GMRFB image to the screen 0 VRAM area. 4155 * Prepare parameters for vmsvga GMRTransfer.4167 * Prepare parameters for vmsvgaR3GmrTransfer. 4156 4168 */ 4157 4169 AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */ 4158 4170 4159 4171 /* Destination: host buffer which describes the screen 0 VRAM. 4160 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvga GMRTransfer.4172 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer. 4161 4173 */ 4162 4174 uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM; … … 4170 4182 int32_t const cbHstPitch = cbScanline; 4171 4183 4172 /* Source: GMRFB. vmsvga GMRTransfer ensures that no memory outside the GMR is read. */4184 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */ 4173 4185 SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr; 4174 4186 uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8 … … 4176 4188 int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine; 4177 4189 4178 rc = vmsvga GMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,4190 rc = vmsvgaR3GmrTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, 4179 4191 pbHstBuf, cbHstBuf, offHst, cbHstPitch, 4180 4192 gstPtr, offGst, cbGstPitch, 4181 4193 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height); 4182 4194 AssertRC(rc); 4183 vmsvga UpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);4195 vmsvgaR3UpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height); 4184 4196 break; 4185 4197 } … … 4198 4210 RT_UNTRUSTED_VALIDATED_FENCE(); 4199 4211 4200 VMSVGASCREENOBJECT *pScreen = vmsvga GetScreenObject(pThis, pCmd->srcScreenId);4212 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, pCmd->srcScreenId); 4201 4213 AssertBreak(pScreen); 4202 4214 … … 4211 4223 screenRect.bottom = pScreen->cHeight; 4212 4224 SVGASignedRect clipRect = pCmd->srcRect; 4213 vmsvga ClipRect(&screenRect, &clipRect);4225 vmsvgaR3ClipRect(&screenRect, &clipRect); 4214 4226 RT_UNTRUSTED_VALIDATED_FENCE(); 4215 4227 … … 4225 4237 4226 4238 /* Copy the defined by GMRFB image to the screen 0 VRAM area. 4227 * Prepare parameters for vmsvga GMRTransfer.4239 * Prepare parameters for vmsvgaR3GmrTransfer. 4228 4240 */ 4229 4241 AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */ 4230 4242 4231 4243 /* Source: host buffer which describes the screen 0 VRAM. 4232 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvga GMRTransfer.4244 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer. 4233 4245 */ 4234 4246 uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM; … … 4242 4254 int32_t const cbHstPitch = cbScanline; 4243 4255 4244 /* Destination: GMRFB. vmsvga GMRTransfer ensures that no memory outside the GMR is read. */4256 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */ 4245 4257 SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr; 4246 4258 uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8 … … 4248 4260 int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine; 4249 4261 4250 rc = vmsvga GMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,4251 pbHstBuf, cbHstBuf, offHst, cbHstPitch,4252 gstPtr, offGst, cbGstPitch,4253 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);4262 rc = vmsvgaR3GmrTransfer(pThis, SVGA3D_READ_HOST_VRAM, 4263 pbHstBuf, cbHstBuf, offHst, cbHstPitch, 4264 gstPtr, offGst, cbGstPitch, 4265 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height); 4254 4266 AssertRC(rc); 4255 4267 break; … … 4262 4274 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill); 4263 4275 4264 Log(("vmsvga FIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));4276 Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b)); 4265 4277 pSVGAState->colorAnnotation = pCmd->color; 4266 4278 break; … … 4273 4285 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy); 4274 4286 4275 Log(("vmsvga FIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));4287 Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n")); 4276 4288 AssertFailed(); 4277 4289 break; … … 4324 4336 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1)); 4325 4337 # ifdef DEBUG_GMR_ACCESS 4326 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR esetGMRHandlers, 1, pThis);4338 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis); 4327 4339 # endif 4328 4340 break; … … 4722 4734 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS) 4723 4735 { 4724 Log(("vmsvga FIFOLoop: fifo progress irq\n"));4736 Log(("vmsvgaR3FifoLoop: fifo progress irq\n")); 4725 4737 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS; 4726 4738 } … … 4729 4741 if (pThis->svga.u32IrqMask & u32IrqStatus) 4730 4742 { 4731 Log(("vmsvga FIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));4743 Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus)); 4732 4744 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus); 4733 4745 PDMDevHlpPCISetIrq(pDevIns, 0, 1); … … 4741 4753 if (fDone) 4742 4754 { 4743 Log(("vmsvga FIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));4744 vmsvga FifoSetNotBusy(pThis, pSVGAState, offFifoMin);4755 Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd)); 4756 vmsvgaR3FifoSetNotBusy(pThis, pSVGAState, offFifoMin); 4745 4757 } 4746 4758 } … … 4760 4772 * @param idGMR GMR id 4761 4773 */ 4762 void vmsvga GMRFree(PVGASTATE pThis, uint32_t idGMR)4774 void vmsvgaR3GmrFree(PVGASTATE pThis, uint32_t idGMR) 4763 4775 { 4764 4776 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State; … … 4770 4782 { 4771 4783 # ifdef DEBUG_GMR_ACCESS 4772 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvga DeregisterGMR, 2, pThis->pDevInsR3, idGMR);4784 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pThis->pDevInsR3, idGMR); 4773 4785 # endif 4774 4786 … … 4800 4812 * @param cHeight Number of scanllines to copy 4801 4813 */ 4802 int vmsvga GMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,4803 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,4804 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,4805 uint32_t cbWidth, uint32_t cHeight)4814 int vmsvgaR3GmrTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, 4815 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch, 4816 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch, 4817 uint32_t cbWidth, uint32_t cHeight) 4806 4818 { 4807 4819 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State; … … 5042 5054 * @param pBox Coordinates to be clipped. 5043 5055 */ 5044 void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc, 5045 const SVGA3dSize *pSizeDest, 5046 SVGA3dCopyBox *pBox) 5056 void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox) 5047 5057 { 5048 5058 /* Src x, w */ … … 5089 5099 * @param pBox Coordinates to be clipped. 5090 5100 */ 5091 void vmsvgaClipBox(const SVGA3dSize *pSize, 5092 SVGA3dBox *pBox) 5101 void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox) 5093 5102 { 5094 5103 /* x, w */ … … 5117 5126 * @param pRect Rectangle to be clipped. 5118 5127 */ 5119 void vmsvgaClipRect(SVGASignedRect const *pBound, 5120 SVGASignedRect *pRect) 5128 void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect) 5121 5129 { 5122 5130 int32_t left; … … 5175 5183 5176 5184 /** 5177 * Unblock the FIFO I/O thread so it can respond to a state change. 5178 * 5179 * @returns VBox status code. 5180 * @param pDevIns The VGA device instance. 5181 * @param pThread The send thread. 5185 * @callback_method_impl{PFNPDMTHREADWAKEUPDEV, 5186 * Unblock the FIFO I/O thread so it can respond to a state change.} 5182 5187 */ 5183 static DECLCALLBACK(int) vmsvga FIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)5188 static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread) 5184 5189 { 5185 5190 RT_NOREF(pDevIns); 5186 5191 PVGASTATE pThis = (PVGASTATE)pThread->pvUser; 5187 Log(("vmsvga FIFOLoopWakeUp\n"));5192 Log(("vmsvgaR3FifoLoopWakeUp\n")); 5188 5193 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem); 5189 5194 } … … 5195 5200 * @param fTraces Enable/disable traces 5196 5201 */ 5197 static void vmsvga SetTraces(PVGASTATE pThis, bool fTraces)5202 static void vmsvgaR3SetTraces(PVGASTATE pThis, bool fTraces) 5198 5203 { 5199 5204 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled) … … 5201 5206 { 5202 5207 //Assert(pThis->svga.fTraces); 5203 Log(("vmsvga SetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));5208 Log(("vmsvgaR3SetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n")); 5204 5209 return; 5205 5210 } … … 5210 5215 unsigned cbFrameBuffer = pThis->vram_size; 5211 5216 5212 Log(("vmsvga SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));5217 Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0)); 5213 5218 /** @todo How does this work with screens? */ 5214 5219 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED) 5215 5220 { 5216 # ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */5221 # ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */ 5217 5222 Assert(pThis->svga.cbScanline); 5218 # endif5223 # endif 5219 5224 /* Hardware enabled; return real framebuffer size .*/ 5220 5225 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline; … … 5224 5229 if (!pThis->svga.fVRAMTracking) 5225 5230 { 5226 Log(("vmsvga SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));5231 Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size)); 5227 5232 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer); 5228 5233 pThis->svga.fVRAMTracking = true; … … 5233 5238 if (pThis->svga.fVRAMTracking) 5234 5239 { 5235 Log(("vmsvga SetTraces: disable frame buffer dirty page tracking\n"));5240 Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n")); 5236 5241 vgaR3UnregisterVRAMHandler(pThis); 5237 5242 pThis->svga.fVRAMTracking = false; … … 5309 5314 * are processed. 5310 5315 */ 5311 void vmsvga 3dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)5316 void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid) 5312 5317 { 5313 5318 vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid, … … 5459 5464 } 5460 5465 5461 /** Portion of VMSVGA state which must be loaded oin the FIFO thread. 5466 /** 5467 * Portion of VMSVGA state which must be loaded oin the FIFO thread. 5462 5468 */ 5463 static int vmsvga LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)5469 static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 5464 5470 { 5465 5471 RT_NOREF(uPass); … … 5520 5526 * @copydoc FNSSMDEVLOADEXEC 5521 5527 */ 5522 int vmsvga LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)5528 int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 5523 5529 { 5524 5530 RT_NOREF(uPass); … … 5626 5632 * Reinit the video mode after the state has been loaded. 5627 5633 */ 5628 int vmsvga LoadDone(PPDMDEVINS pDevIns)5634 int vmsvgaR3LoadDone(PPDMDEVINS pDevIns) 5629 5635 { 5630 5636 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 5654 5660 * Portion of SVGA state which must be saved in the FIFO thread. 5655 5661 */ 5656 static int vmsvga SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)5662 static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM) 5657 5663 { 5658 5664 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State; … … 5684 5690 * @copydoc FNSSMDEVSAVEEXEC 5685 5691 */ 5686 int vmsvga SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)5692 int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 5687 5693 { 5688 5694 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 5745 5751 static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState) 5746 5752 { 5747 # ifndef VMSVGA_USE_EMT_HALT_CODE5753 # ifndef VMSVGA_USE_EMT_HALT_CODE 5748 5754 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI) 5749 5755 { … … 5751 5757 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT; 5752 5758 } 5753 # endif5759 # endif 5754 5760 5755 5761 if (pSVGAState->Cursor.fActive) … … 5786 5792 AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY); 5787 5793 5788 # ifndef VMSVGA_USE_EMT_HALT_CODE5794 # ifndef VMSVGA_USE_EMT_HALT_CODE 5789 5795 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */ 5790 5796 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts); 5791 5797 AssertRCReturn(rc, rc); 5792 # endif5798 # endif 5793 5799 5794 5800 return rc; … … 5801 5807 * @param pThis The VGA instance. 5802 5808 */ 5803 static void vmsvga InitCaps(PVGASTATE pThis)5809 static void vmsvgaR3InitCaps(PVGASTATE pThis) 5804 5810 { 5805 5811 /* Register caps. */ … … 5930 5936 * @param pThis The VGA instance. 5931 5937 */ 5932 static void vmsvga InitFifo3DCaps(PVGASTATE pThis)5938 static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis) 5933 5939 { 5934 5940 /** @todo Probably query the capabilities once and cache in a memory buffer. */ … … 5983 5989 * @param pDevIns The device instance. 5984 5990 */ 5985 int vmsvgaR eset(PPDMDEVINS pDevIns)5991 int vmsvgaR3Reset(PPDMDEVINS pDevIns) 5986 5992 { 5987 5993 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 5992 5998 return VINF_SUCCESS; 5993 5999 5994 Log(("vmsvgaR eset\n"));6000 Log(("vmsvgaR3Reset\n")); 5995 6001 5996 6002 /* Reset the FIFO processing as well as the 3d state (if we have one). */ … … 6008 6014 6009 6015 /* Initialize FIFO and register capabilities. */ 6010 vmsvga InitCaps(pThis);6016 vmsvgaR3InitCaps(pThis); 6011 6017 6012 6018 # ifdef VBOX_WITH_VMSVGA3D 6013 6019 if (pThis->svga.f3DEnabled) 6014 vmsvga InitFifo3DCaps(pThis);6020 vmsvgaR3InitFifo3DCaps(pThis); 6015 6021 # endif 6016 6022 … … 6035 6041 * @param pDevIns The device instance. 6036 6042 */ 6037 int vmsvga Destruct(PPDMDEVINS pDevIns)6043 int vmsvgaR3Destruct(PPDMDEVINS pDevIns) 6038 6044 { 6039 6045 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 6091 6097 * @param pDevIns The device instance. 6092 6098 */ 6093 int vmsvga Init(PPDMDEVINS pDevIns)6099 int vmsvgaR3Init(PPDMDEVINS pDevIns) 6094 6100 { 6095 6101 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); … … 6123 6129 6124 6130 /* Initialize FIFO and register capabilities. */ 6125 vmsvga InitCaps(pThis);6131 vmsvgaR3InitCaps(pThis); 6126 6132 6127 6133 # ifdef VBOX_WITH_VMSVGA3D … … 6157 6163 /* Register the GMR access handler type. */ 6158 6164 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE, 6159 vmsvgaR3G MRAccessHandler,6165 vmsvgaR3GmrAccessHandler, 6160 6166 NULL, NULL, NULL, 6161 6167 NULL, NULL, NULL, … … 6174 6180 PGMPHYSHANDLERKIND_WRITE, 6175 6181 # endif 6176 vmsvgaR3F IFOAccessHandler,6182 vmsvgaR3FifoAccessHandler, 6177 6183 NULL, NULL, NULL, 6178 6184 NULL, NULL, NULL, … … 6182 6188 6183 6189 /* Create the async IO thread. */ 6184 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvga FIFOLoop, vmsvgaFIFOLoopWakeUp, 0,6185 6190 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0, 6191 RTTHREADTYPE_IO, "VMSVGA FIFO"); 6186 6192 if (RT_FAILURE(rc)) 6187 6193 { … … 6193 6199 * Statistics. 6194 6200 */ 6195 # define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \6201 # define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \ 6196 6202 PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc) 6197 # define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \6203 # define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \ 6198 6204 PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc) 6199 # ifdef VBOX_WITH_STATISTICS6205 # ifdef VBOX_WITH_STATISTICS 6200 6206 REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES."); 6201 6207 REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK."); 6202 6208 REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA."); 6203 # endif6209 # endif 6204 6210 REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE"); 6205 6211 REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY"); … … 6356 6362 REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread."); 6357 6363 6358 # undef REG_CNT6359 # undef REG_PRF6364 # undef REG_CNT 6365 # undef REG_PRF 6360 6366 6361 6367 /* … … 6397 6403 { 6398 6404 /* Initialize FIFO 3D capabilities. */ 6399 vmsvga InitFifo3DCaps(pThis);6405 vmsvgaR3InitFifo3DCaps(pThis); 6400 6406 } 6401 6407 } -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h
r82088 r82089 369 369 uint32_t x, uint32_t y, uint32_t cx, uint32_t cy); 370 370 371 int vmsvga Init(PPDMDEVINS pDevIns);372 int vmsvgaR eset(PPDMDEVINS pDevIns);373 int vmsvga Destruct(PPDMDEVINS pDevIns);374 int vmsvga LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);375 int vmsvga LoadDone(PPDMDEVINS pDevIns);376 int vmsvga SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);371 int vmsvgaR3Init(PPDMDEVINS pDevIns); 372 int vmsvgaR3Reset(PPDMDEVINS pDevIns); 373 int vmsvgaR3Destruct(PPDMDEVINS pDevIns); 374 int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass); 375 int vmsvgaR3LoadDone(PPDMDEVINS pDevIns); 376 int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM); 377 377 DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns); 378 378 DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns); 379 void vmsvga FIFOWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis);379 void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis); 380 380 381 381 #ifdef IN_RING3 382 VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen); 383 int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h); 384 #endif 385 386 void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR); 387 int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, 388 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch, 389 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch, 390 uint32_t cbWidth, uint32_t cHeight); 391 392 void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc, 393 const SVGA3dSize *pSizeDest, 394 SVGA3dCopyBox *pBox); 395 void vmsvgaClipBox(const SVGA3dSize *pSize, 396 SVGA3dBox *pBox); 397 void vmsvgaClipRect(SVGASignedRect const *pBound, 398 SVGASignedRect *pRect); 382 VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATE pThis, uint32_t idScreen); 383 int vmsvgaR3UpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h); 384 #endif 385 386 void vmsvgaR3GmrFree(PVGASTATE pThis, uint32_t idGMR); 387 int vmsvgaR3GmrTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, 388 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch, 389 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch, 390 uint32_t cbWidth, uint32_t cHeight); 391 392 void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox); 393 void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox); 394 void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect); 399 395 400 396 #endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h */ -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-info.cpp
r82053 r82089 2099 2099 { 2100 2100 if (fVerbose) 2101 vmsvga 3dSurfaceUpdateHeapBuffersOnFifoThread(pDevIns, pThis, sid);2101 vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(pDevIns, pThis, sid); 2102 2102 vmsvga3dInfoSurfaceWorkerOne(pHlp, pSurface, fVerbose, cxAscii, fInvY); 2103 2103 if (pszBitmapPath && *pszBitmapPath) … … 2114 2114 */ 2115 2115 if (fVerbose) 2116 vmsvga 3dSurfaceUpdateHeapBuffersOnFifoThread(pDevIns, pThis, UINT32_MAX);2116 vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(pDevIns, pThis, UINT32_MAX); 2117 2117 uint32_t cSurfaces = pState->cSurfaces; 2118 2118 pHlp->pfnPrintf(pHlp, "cSurfaces=%d\n", cSurfaces); -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-ogl.cpp
r82003 r82089 2766 2766 uint32_t const offGst = u32GuestBlockX * pSurface->cbBlock + u32GuestBlockY * cbGuestPitch; 2767 2767 2768 rc = vmsvga GMRTransfer(pThis,2769 transfer,2770 pDoubleBuffer,2771 pMipLevel->cbSurface,2772 offHst,2773 cbSurfacePitch,2774 GuestPtr,2775 offGst,2776 cbGuestPitch,2777 cBlocksX * pSurface->cbBlock,2778 cBlocksY);2768 rc = vmsvgaR3GmrTransfer(pThis, 2769 transfer, 2770 pDoubleBuffer, 2771 pMipLevel->cbSurface, 2772 offHst, 2773 cbSurfacePitch, 2774 GuestPtr, 2775 offGst, 2776 cbGuestPitch, 2777 cBlocksX * pSurface->cbBlock, 2778 cBlocksY); 2779 2779 AssertRC(rc); 2780 2780 … … 2913 2913 uint32_t const cbWidth = pBox->w * pSurface->cbBlock; 2914 2914 2915 rc = vmsvga GMRTransfer(pThis,2916 transfer,2917 pbData,2918 pMipLevel->cbSurface,2919 offHst,2920 pMipLevel->cbSurfacePitch,2921 GuestPtr,2922 pBox->srcx * pSurface->cbBlock,2923 cbGuestPitch,2924 cbWidth,2925 pBox->h);2915 rc = vmsvgaR3GmrTransfer(pThis, 2916 transfer, 2917 pbData, 2918 pMipLevel->cbSurface, 2919 offHst, 2920 pMipLevel->cbSurfacePitch, 2921 GuestPtr, 2922 pBox->srcx * pSurface->cbBlock, 2923 cbGuestPitch, 2924 cbWidth, 2925 pBox->h); 2926 2926 AssertRC(rc); 2927 2927 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win.cpp
r81980 r82089 1548 1548 { 1549 1549 SVGA3dCopyBox clipBox = pBox[i]; 1550 vmsvga ClipCopyBox(&pMipmapLevelSrc->mipmapSize, &pMipmapLevelDest->mipmapSize, &clipBox);1550 vmsvgaR3ClipCopyBox(&pMipmapLevelSrc->mipmapSize, &pMipmapLevelDest->mipmapSize, &clipBox); 1551 1551 if ( !clipBox.w 1552 1552 || !clipBox.h … … 1703 1703 1704 1704 SVGA3dCopyBox clipBox = pBox[i]; 1705 vmsvga ClipCopyBox(&pMipmapLevelSrc->mipmapSize, &pMipmapLevelDest->mipmapSize, &clipBox);1705 vmsvgaR3ClipCopyBox(&pMipmapLevelSrc->mipmapSize, &pMipmapLevelDest->mipmapSize, &clipBox); 1706 1706 if ( !clipBox.w 1707 1707 || !clipBox.h … … 2384 2384 AssertMsgReturn(cBlocksX && cBlocksY, ("Empty box %dx%d\n", pBox->w, pBox->h), VERR_INTERNAL_ERROR); 2385 2385 2386 /* vmsvga GMRTransfer verifies uGuestOffset.2386 /* vmsvgaR3GmrTransfer verifies uGuestOffset. 2387 2387 * srcx(u32GuestBlockX) and srcy(u32GuestBlockY) have been verified in vmsvga3dSurfaceDMA 2388 2388 * to not cause 32 bit overflow when multiplied by cbBlock and cbGuestPitch. … … 2405 2405 Rect.left, Rect.top, Rect.right, Rect.bottom)); 2406 2406 2407 /* Prepare parameters for vmsvga GMRTransfer, which needs the host buffer address, size2407 /* Prepare parameters for vmsvgaR3GmrTransfer, which needs the host buffer address, size 2408 2408 * and offset of the first scanline. 2409 2409 */ … … 2414 2414 uint32_t const offLockedBuf = (uint32_t)((uintptr_t)LockedRect.pBits - (uintptr_t)pu8LockedBuf); 2415 2415 2416 rc = vmsvga GMRTransfer(pThis,2417 transfer,2418 pu8LockedBuf,2419 cbLockedBuf,2420 offLockedBuf,2421 LockedRect.Pitch,2422 GuestPtr,2423 (uint32_t)uGuestOffset,2424 cbGuestPitch,2425 cBlocksX * pSurface->cbBlock,2426 cBlocksY);2416 rc = vmsvgaR3GmrTransfer(pThis, 2417 transfer, 2418 pu8LockedBuf, 2419 cbLockedBuf, 2420 offLockedBuf, 2421 LockedRect.Pitch, 2422 GuestPtr, 2423 (uint32_t)uGuestOffset, 2424 cbGuestPitch, 2425 cBlocksX * pSurface->cbBlock, 2426 cBlocksY); 2427 2427 AssertRC(rc); 2428 2428 … … 2472 2472 Assert(pBox->y == 0 && pBox->h == 1 && pBox->z == 0 && pBox->d == 1); 2473 2473 2474 /* vmsvga GMRTransfer verifies input parameters except for the host buffer addres and size.2474 /* vmsvgaR3GmrTransfer verifies input parameters except for the host buffer addres and size. 2475 2475 * srcx has been verified in vmsvga3dSurfaceDMA to not cause 32 bit overflow when multiplied by cbBlock. 2476 2476 */ … … 2481 2481 2482 2482 /* Copy data between the guest and the host buffer. */ 2483 rc = vmsvga GMRTransfer(pThis,2484 transfer,2485 (uint8_t *)pMipLevel->pSurfaceData,2486 pMipLevel->cbSurface,2487 offHst,2488 pMipLevel->cbSurfacePitch,2489 GuestPtr,2490 offGst,2491 cbGuestPitch,2492 cbWidth,2493 1); /* Buffers are 1-dimensional */2483 rc = vmsvgaR3GmrTransfer(pThis, 2484 transfer, 2485 (uint8_t *)pMipLevel->pSurfaceData, 2486 pMipLevel->cbSurface, 2487 offHst, 2488 pMipLevel->cbSurfacePitch, 2489 GuestPtr, 2490 offGst, 2491 cbGuestPitch, 2492 cbWidth, 2493 1); /* Buffers are 1-dimensional */ 2494 2494 AssertRC(rc); 2495 2495 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.cpp
r81771 r82089 459 459 SVGA3dBox clipSrcBox = *pSrcBox; 460 460 SVGA3dBox clipDstBox = *pDstBox; 461 vmsvga ClipBox(&pSrcMipmapLevel->mipmapSize, &clipSrcBox);462 vmsvga ClipBox(&pDstMipmapLevel->mipmapSize, &clipDstBox);461 vmsvgaR3ClipBox(&pSrcMipmapLevel->mipmapSize, &clipSrcBox); 462 vmsvgaR3ClipBox(&pDstMipmapLevel->mipmapSize, &clipDstBox); 463 463 464 464 return vmsvga3dBackSurfaceStretchBlt(pThis, pState, … … 539 539 hostBox.h = paBoxes[i].h; 540 540 hostBox.d = paBoxes[i].d; 541 vmsvga ClipBox(&pMipLevel->mipmapSize, &hostBox);541 vmsvgaR3ClipBox(&pMipLevel->mipmapSize, &hostBox); 542 542 543 543 if ( !hostBox.w … … 551 551 552 552 /* Adjust the guest, i.e. "src", point. 553 * Do not try to verify them here because vmsvga GMRTransfer takes care of this.553 * Do not try to verify them here because vmsvgaR3GmrTransfer takes care of this. 554 554 */ 555 555 uint32_t const srcx = paBoxes[i].srcx + (hostBox.x - paBoxes[i].x); … … 600 600 else 601 601 { 602 /* vmsvga GMRTransfer will verify the value, just check it is sane. */602 /* vmsvgaR3GmrTransfer will verify the value, just check it is sane. */ 603 603 AssertReturn(cbGuestPitch <= SVGA3D_MAX_SURFACE_MEM_SIZE, VERR_INVALID_PARAMETER); 604 604 RT_UNTRUSTED_VALIDATED_FENCE(); … … 606 606 607 607 /* srcx, srcy and srcz values are used to calculate the guest offset. 608 * The offset will be verified by vmsvga GMRTransfer, so just check for overflows here.608 * The offset will be verified by vmsvgaR3GmrTransfer, so just check for overflows here. 609 609 */ 610 610 AssertReturn(srcz < UINT32_MAX / pMipLevel->mipmapSize.height / cbGuestPitch, VERR_INVALID_PARAMETER); … … 628 628 for (uint32_t z = 0; z < hostBox.d; ++z) 629 629 { 630 rc = vmsvga GMRTransfer(pThis,631 transfer,632 (uint8_t *)pMipLevel->pSurfaceData,633 pMipLevel->cbSurface,634 uHostOffset,635 (int32_t)pMipLevel->cbSurfacePitch,636 guest.ptr,637 (uint32_t)uGuestOffset,638 cbGuestPitch,639 cBlocksX * pSurface->cbBlock,640 cBlocksY);630 rc = vmsvgaR3GmrTransfer(pThis, 631 transfer, 632 (uint8_t *)pMipLevel->pSurfaceData, 633 pMipLevel->cbSurface, 634 uHostOffset, 635 (int32_t)pMipLevel->cbSurfacePitch, 636 guest.ptr, 637 (uint32_t)uGuestOffset, 638 cbGuestPitch, 639 cBlocksX * pSurface->cbBlock, 640 cBlocksY); 641 641 AssertRC(rc); 642 642 … … 684 684 queryResult.result32 = u32Result; 685 685 686 int rc = vmsvga GMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,687 (uint8_t *)&queryResult, sizeof(queryResult), 0, sizeof(queryResult),688 guestResult, 0, sizeof(queryResult), sizeof(queryResult), 1);686 int rc = vmsvgaR3GmrTransfer(pThis, SVGA3D_READ_HOST_VRAM, 687 (uint8_t *)&queryResult, sizeof(queryResult), 0, sizeof(queryResult), 688 guestResult, 0, sizeof(queryResult), sizeof(queryResult), 1); 689 689 AssertRC(rc); 690 690 return rc; … … 820 820 } 821 821 822 VMSVGASCREENOBJECT *pScreen = vmsvga GetScreenObject(pThis, idDstScreen);822 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, idDstScreen); 823 823 AssertReturn(pScreen, VERR_INTERNAL_ERROR); 824 824 … … 863 863 864 864 /* Update the guest image, which is at box.src. */ 865 vmsvga UpdateScreen(pThis, pScreen, box.srcx, box.srcy, box.w, box.h);865 vmsvgaR3UpdateScreen(pThis, pScreen, box.srcx, box.srcy, box.w, box.h); 866 866 } 867 867 else … … 888 888 889 889 /* Update the guest image, which is at box.src. */ 890 vmsvga UpdateScreen(pThis, pScreen, box.srcx, box.srcy, box.w, box.h);890 vmsvgaR3UpdateScreen(pThis, pScreen, box.srcx, box.srcy, box.w, box.h); 891 891 } 892 892 } … … 906 906 907 907 /** @todo Detect screen from coords? Or split rect to screens? */ 908 VMSVGASCREENOBJECT *pScreen = vmsvga GetScreenObject(pThis, 0);908 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThis, 0); 909 909 AssertReturn(pScreen, VERR_INTERNAL_ERROR); 910 910 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.h
r82053 r82089 52 52 53 53 /* DevVGA-SVGA.cpp: */ 54 void vmsvga 3dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid);54 void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid); 55 55 56 56 -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r82088 r82089 5536 5536 */ 5537 5537 if (pThis->svga.fFIFOThreadSleeping && pThis->svga.fEnabled && pThis->svga.fConfigured) 5538 vmsvga FIFOWatchdogTimer(pDevIns, pThis);5538 vmsvgaR3FifoWatchdogTimer(pDevIns, pThis); 5539 5539 # endif 5540 5540 } … … 5841 5841 if (pThis->fVMSVGAEnabled) 5842 5842 { 5843 rc = vmsvga SaveExec(pDevIns, pSSM);5843 rc = vmsvgaR3SaveExec(pDevIns, pSSM); 5844 5844 AssertRCReturn(rc, rc); 5845 5845 } … … 5931 5931 if (pThis->fVMSVGAEnabled) 5932 5932 { 5933 rc = vmsvga LoadExec(pDevIns, pSSM, uVersion, uPass);5933 rc = vmsvgaR3LoadExec(pDevIns, pSSM, uVersion, uPass); 5934 5934 AssertRCReturn(rc, rc); 5935 5935 } … … 5963 5963 if (pThis->fVMSVGAEnabled) 5964 5964 { 5965 rc = vmsvga LoadDone(pDevIns);5965 rc = vmsvgaR3LoadDone(pDevIns); 5966 5966 AssertRCReturn(rc, rc); 5967 5967 } … … 5998 5998 # ifdef VBOX_WITH_VMSVGA 5999 5999 if (pThis->fVMSVGAEnabled) 6000 vmsvgaR eset(pDevIns);6000 vmsvgaR3Reset(pDevIns); 6001 6001 # endif 6002 6002 … … 6235 6235 # ifdef VBOX_WITH_VMSVGA 6236 6236 if (pThis->fVMSVGAEnabled) 6237 vmsvga Destruct(pDevIns);6237 vmsvgaR3Destruct(pDevIns); 6238 6238 # endif 6239 6239 … … 7198 7198 if ( rc == VINF_SUCCESS 7199 7199 && pThis->fVMSVGAEnabled) 7200 rc = vmsvga Init(pDevIns);7200 rc = vmsvgaR3Init(pDevIns); 7201 7201 # endif 7202 7202
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