Changeset 82293 in vbox
- Timestamp:
- Nov 29, 2019 10:22:31 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 135117
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (55 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r82255 r82293 513 513 /** The timer for pumping data thru the attached LUN drivers - R0Ptr. */ 514 514 PTMTIMERR0 pTimerR0[AC97_MAX_STREAMS]; 515 #ifdef VBOX_WITH_STATISTICS516 STAMPROFILE StatTimer;517 STAMPROFILE StatIn;518 STAMPROFILE StatOut;519 STAMCOUNTER StatBytesRead;520 STAMCOUNTER StatBytesWritten;521 #endif522 515 /** List of associated LUN drivers (AC97DRIVER). */ 523 516 RTLISTANCHORR3 lstDrv; … … 532 525 uint8_t silence[128]; 533 526 int32_t bup_flag; 534 /** Base port of the I/O space region. */535 RTIOPORT IOPortBase[2];536 527 /** Codec model. */ 537 528 uint32_t uCodecModel; 538 #if HC_ARCH_BITS == 64539 uint32_t uPadding2;540 #endif541 529 /** The base interface for LUN\#0. */ 542 530 PDMIBASE IBase; 543 531 AC97STATEDBGINFO Dbg; 532 533 /** PCI region \#0: NAM I/O ports. */ 534 IOMIOPORTHANDLE hIoPortsNam; 535 /** PCI region \#0: NANM I/O ports. */ 536 IOMIOPORTHANDLE hIoPortsNabm; 537 538 #ifdef VBOX_WITH_STATISTICS 539 STAMPROFILE StatTimer; 540 STAMPROFILE StatIn; 541 STAMPROFILE StatOut; 542 STAMCOUNTER StatBytesRead; 543 STAMCOUNTER StatBytesWritten; 544 #endif 544 545 } AC97STATE; 545 546 AssertCompileMemberAlignment(AC97STATE, aStreams, 8); … … 2258 2259 } 2259 2260 2260 const bool 2261 uint8_tuCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK;2262 uint8_tuCtlAttRight = uVal & AC97_BARS_VOL_MASK;2261 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1; 2262 uint8_t uCtlAttLeft = (uVal >> 8) & AC97_BARS_VOL_MASK; 2263 uint8_t uCtlAttRight = uVal & AC97_BARS_VOL_MASK; 2263 2264 2264 2265 /* For the master and headphone volume, 0 corresponds to 0dB attenuation. For the other … … 2346 2347 * zero being 0dB gain and 15 being +22.5dB gain. 2347 2348 */ 2348 const bool 2349 uint8_tuCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK;2350 uint8_tuCtlGainRight = uVal & AC97_BARS_GAIN_MASK;2349 const bool fCtlMuted = (uVal >> AC97_BARS_VOL_MUTE_SHIFT) & 1; 2350 uint8_t uCtlGainLeft = (uVal >> 8) & AC97_BARS_GAIN_MASK; 2351 uint8_t uCtlGainRight = uVal & AC97_BARS_GAIN_MASK; 2351 2352 2352 2353 Assert(uCtlGainLeft <= 255 / AC97_DB_FACTOR); … … 2933 2934 2934 2935 /** 2935 * Port I/O Handler for IN operations. 2936 * 2937 * @returns VINF_SUCCESS or VINF_EM_*. 2938 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned. 2939 * 2940 * @param pDevIns The device instance. 2941 * @param pvUser User argument. 2942 * @param uPort Port number used for the IN operation. 2943 * @param pu32Val Where to store the result. This is always a 32-bit 2944 * variable regardless of what @a cbVal might say. 2945 * @param cbVal Number of bytes read. 2946 */ 2947 PDMBOTHCBDECL(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32Val, unsigned cbVal) 2936 * @callback_method_impl{FNIOMIOPORTNEWOUT} 2937 */ 2938 static DECLCALLBACK(VBOXSTRICTRC) 2939 ichac97IoPortNabmRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 2948 2940 { 2949 2941 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE); … … 2953 2945 2954 2946 /* Get the index of the NABMBAR port. */ 2955 const uint32_t uPortIdx = uPort - pThis->IOPortBase[1];2956 2957 2947 PAC97STREAM pStream = NULL; 2958 2948 PAC97BMREGS pRegs = NULL; 2959 2960 if (AC97_PORT2IDX(uPortIdx) < AC97_MAX_STREAMS) 2961 { 2962 pStream = &pThis->aStreams[AC97_PORT2IDX(uPortIdx)]; 2949 if (AC97_PORT2IDX(offPort) < AC97_MAX_STREAMS) 2950 { 2951 pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)]; 2963 2952 AssertPtr(pStream); 2964 2953 pRegs = &pStream->Regs; 2965 2954 } 2966 2955 2967 intrc = VINF_SUCCESS;2968 2969 switch (cb Val)2956 VBOXSTRICTRC rc = VINF_SUCCESS; 2957 2958 switch (cb) 2970 2959 { 2971 2960 case 1: 2972 2961 { 2973 switch ( uPortIdx)2962 switch (offPort) 2974 2963 { 2975 2964 case AC97_CAS: 2976 2965 /* Codec Access Semaphore Register */ 2977 2966 Log3Func(("CAS %d\n", pThis->cas)); 2978 *pu32 Val= pThis->cas;2967 *pu32 = pThis->cas; 2979 2968 pThis->cas = 1; 2980 2969 break; … … 2983 2972 case MC_CIV: 2984 2973 /* Current Index Value Register */ 2985 *pu32 Val= pRegs->civ;2986 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));2974 *pu32 = pRegs->civ; 2975 Log3Func(("CIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 2987 2976 break; 2988 2977 case PI_LVI: … … 2990 2979 case MC_LVI: 2991 2980 /* Last Valid Index Register */ 2992 *pu32 Val= pRegs->lvi;2993 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));2981 *pu32 = pRegs->lvi; 2982 Log3Func(("LVI[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 2994 2983 break; 2995 2984 case PI_PIV: … … 2997 2986 case MC_PIV: 2998 2987 /* Prefetched Index Value Register */ 2999 *pu32 Val= pRegs->piv;3000 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));2988 *pu32 = pRegs->piv; 2989 Log3Func(("PIV[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 3001 2990 break; 3002 2991 case PI_CR: … … 3004 2993 case MC_CR: 3005 2994 /* Control Register */ 3006 *pu32 Val= pRegs->cr;3007 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));2995 *pu32 = pRegs->cr; 2996 Log3Func(("CR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 3008 2997 break; 3009 2998 case PI_SR: … … 3011 3000 case MC_SR: 3012 3001 /* Status Register (lower part) */ 3013 *pu32 Val= RT_LO_U8(pRegs->sr);3014 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));3002 *pu32 = RT_LO_U8(pRegs->sr); 3003 Log3Func(("SRb[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 3015 3004 break; 3016 3005 default: 3017 *pu32 Val= UINT32_MAX;3018 LogFunc(("U nabm readb %#x -> %#x\n", uPort, *pu32Val));3006 *pu32 = UINT32_MAX; 3007 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX)); 3019 3008 break; 3020 3009 } … … 3024 3013 case 2: 3025 3014 { 3026 switch ( uPortIdx)3015 switch (offPort) 3027 3016 { 3028 3017 case PI_SR: … … 3030 3019 case MC_SR: 3031 3020 /* Status Register */ 3032 *pu32 Val= pRegs->sr;3033 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));3021 *pu32 = pRegs->sr; 3022 Log3Func(("SR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 3034 3023 break; 3035 3024 case PI_PICB: … … 3037 3026 case MC_PICB: 3038 3027 /* Position in Current Buffer */ 3039 *pu32 Val= pRegs->picb;3040 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));3028 *pu32 = pRegs->picb; 3029 Log3Func(("PICB[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 3041 3030 break; 3042 3031 default: 3043 *pu32 Val= UINT32_MAX;3044 LogFunc(("U nabm readw %#x -> %#x\n", uPort, *pu32Val));3032 *pu32 = UINT32_MAX; 3033 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX)); 3045 3034 break; 3046 3035 } … … 3050 3039 case 4: 3051 3040 { 3052 switch ( uPortIdx)3041 switch (offPort) 3053 3042 { 3054 3043 case PI_BDBAR: … … 3056 3045 case MC_BDBAR: 3057 3046 /* Buffer Descriptor Base Address Register */ 3058 *pu32 Val= pRegs->bdbar;3059 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX( uPortIdx), *pu32Val));3047 *pu32 = pRegs->bdbar; 3048 Log3Func(("BMADDR[%d] -> %#x\n", AC97_PORT2IDX(offPort), *pu32)); 3060 3049 break; 3061 3050 case PI_CIV: … … 3065 3054 * Last Valid Index Register + 3066 3055 * Status Register */ 3067 *pu32 Val= pRegs->civ | (pRegs->lvi << 8) | (pRegs->sr << 16); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */3056 *pu32 = pRegs->civ | (pRegs->lvi << 8) | (pRegs->sr << 16); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */ 3068 3057 Log3Func(("CIV LVI SR[%d] -> %#x, %#x, %#x\n", 3069 AC97_PORT2IDX( uPortIdx), pRegs->civ, pRegs->lvi, pRegs->sr));3058 AC97_PORT2IDX(offPort), pRegs->civ, pRegs->lvi, pRegs->sr)); 3070 3059 break; 3071 3060 case PI_PICB: … … 3075 3064 * Prefetched Index Value Register + 3076 3065 * Control Register */ 3077 *pu32 Val= pRegs->picb | (pRegs->piv << 16) | (pRegs->cr << 24); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */3066 *pu32 = pRegs->picb | (pRegs->piv << 16) | (pRegs->cr << 24); /** @todo r=andy Use RT_MAKE_U32_FROM_U8. */ 3078 3067 Log3Func(("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", 3079 AC97_PORT2IDX( uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr));3068 AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr)); 3080 3069 break; 3081 3070 case AC97_GLOB_CNT: 3082 3071 /* Global Control */ 3083 *pu32 Val= pThis->glob_cnt;3084 Log3Func(("glob_cnt -> %#x\n", *pu32 Val));3072 *pu32 = pThis->glob_cnt; 3073 Log3Func(("glob_cnt -> %#x\n", *pu32)); 3085 3074 break; 3086 3075 case AC97_GLOB_STA: 3087 3076 /* Global Status */ 3088 *pu32 Val= pThis->glob_sta | AC97_GS_S0CR;3089 Log3Func(("glob_sta -> %#x\n", *pu32 Val));3077 *pu32 = pThis->glob_sta | AC97_GS_S0CR; 3078 Log3Func(("glob_sta -> %#x\n", *pu32)); 3090 3079 break; 3091 3080 default: 3092 *pu32 Val= UINT32_MAX;3093 LogFunc(("U nabm readl %#x -> %#x\n", uPort, *pu32Val));3081 *pu32 = UINT32_MAX; 3082 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX)); 3094 3083 break; 3095 3084 } … … 3110 3099 3111 3100 /** 3112 * Port I/O Handler for OUT operations. 3113 * 3114 * @returns VINF_SUCCESS or VINF_EM_*. 3115 * 3116 * @param pDevIns The device instance. 3117 * @param pvUser User argument. 3118 * @param uPort Port number used for the OUT operation. 3119 * @param u32Val The value to output. 3120 * @param cbVal The value size in bytes. 3121 */ 3122 PDMBOTHCBDECL(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32Val, unsigned cbVal) 3123 { 3124 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE); 3101 * @callback_method_impl{FNIOMIOPORTNEWOUT} 3102 */ 3103 static DECLCALLBACK(VBOXSTRICTRC) 3104 ichac97IoPortNabmWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 3105 { 3106 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE); 3125 3107 RT_NOREF(pvUser); 3126 3127 /* Get the index of the NABMBAR register. */3128 const uint32_t uPortIdx = uPort - pThis->IOPortBase[1];3129 3108 3130 3109 PAC97STREAM pStream = NULL; 3131 3110 PAC97BMREGS pRegs = NULL; 3132 3133 if (AC97_PORT2IDX(uPortIdx) < AC97_MAX_STREAMS) 3134 { 3135 pStream = &pThis->aStreams[AC97_PORT2IDX(uPortIdx)]; 3111 if (AC97_PORT2IDX(offPort) < AC97_MAX_STREAMS) 3112 { 3113 pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)]; 3136 3114 AssertPtr(pStream); 3137 3115 pRegs = &pStream->Regs; … … 3140 3118 } 3141 3119 3142 intrc = VINF_SUCCESS;3143 switch (cb Val)3120 VBOXSTRICTRC rc = VINF_SUCCESS; 3121 switch (cb) 3144 3122 { 3145 3123 case 1: 3146 3124 { 3147 switch ( uPortIdx)3125 switch (offPort) 3148 3126 { 3149 3127 /* … … 3167 3145 #endif 3168 3146 } 3169 pRegs->lvi = u32 Val% AC97_MAX_BDLE;3170 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32 Val));3147 pRegs->lvi = u32 % AC97_MAX_BDLE; 3148 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32)); 3171 3149 break; 3172 3150 } … … 3182 3160 AssertPtr(pRegs); 3183 3161 #ifdef IN_RING3 3184 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32 Val, pRegs->cr));3185 if (u32 Val& AC97_CR_RR) /* Busmaster reset. */3162 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr)); 3163 if (u32 & AC97_CR_RR) /* Busmaster reset. */ 3186 3164 { 3187 3165 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD)); … … 3197 3175 else 3198 3176 { 3199 pRegs->cr = u32 Val& AC97_CR_VALID_MASK;3177 pRegs->cr = u32 & AC97_CR_VALID_MASK; 3200 3178 3201 3179 if (!(pRegs->cr & AC97_CR_RPBM)) … … 3243 3221 case MC_SR: 3244 3222 { 3245 ichac97StreamWriteSR(pThis, pStream, u32 Val);3223 ichac97StreamWriteSR(pThis, pStream, u32); 3246 3224 break; 3247 3225 } 3248 3226 3249 3227 default: 3250 LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));3228 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32)); 3251 3229 break; 3252 3230 } … … 3256 3234 case 2: 3257 3235 { 3258 switch ( uPortIdx)3236 switch (offPort) 3259 3237 { 3260 3238 case PI_SR: 3261 3239 case PO_SR: 3262 3240 case MC_SR: 3263 ichac97StreamWriteSR(pThis, pStream, u32 Val);3241 ichac97StreamWriteSR(pThis, pStream, u32); 3264 3242 break; 3265 3243 default: 3266 LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));3244 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32)); 3267 3245 break; 3268 3246 } … … 3272 3250 case 4: 3273 3251 { 3274 switch ( uPortIdx)3252 switch (offPort) 3275 3253 { 3276 3254 case PI_BDBAR: … … 3280 3258 AssertPtr(pRegs); 3281 3259 /* Buffer Descriptor list Base Address Register */ 3282 pRegs->bdbar = u32 Val& ~3;3283 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX( uPortIdx), u32Val, pRegs->bdbar));3260 pRegs->bdbar = u32 & ~3; 3261 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar)); 3284 3262 break; 3285 3263 case AC97_GLOB_CNT: 3286 3264 /* Global Control */ 3287 if (u32 Val& AC97_GC_WR)3265 if (u32 & AC97_GC_WR) 3288 3266 ichac97WarmReset(pThis); 3289 if (u32 Val& AC97_GC_CR)3267 if (u32 & AC97_GC_CR) 3290 3268 ichac97ColdReset(pThis); 3291 if (!(u32 Val& (AC97_GC_WR | AC97_GC_CR)))3292 pThis->glob_cnt = u32 Val& AC97_GC_VALID_MASK;3293 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32 Val, pThis->glob_cnt));3269 if (!(u32 & (AC97_GC_WR | AC97_GC_CR))) 3270 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK; 3271 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt)); 3294 3272 break; 3295 3273 case AC97_GLOB_STA: 3296 3274 /* Global Status */ 3297 pThis->glob_sta &= ~(u32 Val& AC97_GS_WCLEAR_MASK);3298 pThis->glob_sta |= (u32 Val& ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK;3299 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32 Val, pThis->glob_sta));3275 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK); 3276 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK; 3277 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta)); 3300 3278 break; 3301 3279 default: 3302 LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));3280 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32)); 3303 3281 break; 3304 3282 } … … 3307 3285 3308 3286 default: 3309 LogRel2(("AC97: Warning: Unimplemented NABMWrite (%u byte) portIdx=%#x <- %#x\n", cbVal, uPortIdx, u32Val));3287 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb)); 3310 3288 break; 3311 3289 } … … 3318 3296 3319 3297 /** 3320 * Port I/O Handler for IN operations. 3321 * 3322 * @returns VINF_SUCCESS or VINF_EM_*. 3323 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned. 3324 * 3325 * @param pDevIns The device instance. 3326 * @param pvUser User argument. 3327 * @param uPort Port number used for the IN operation. 3328 * @param pu32Val Where to store the result. This is always a 32-bit 3329 * variable regardless of what @a cbVal might say. 3330 * @param cbVal Number of bytes read. 3331 */ 3332 PDMBOTHCBDECL(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32Val, unsigned cbVal) 3298 * @callback_method_impl{FNIOMIOPORTNEWIN} 3299 */ 3300 static DECLCALLBACK(VBOXSTRICTRC) 3301 ichac97IoPortNamRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb) 3333 3302 { 3334 3303 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE); … … 3337 3306 DEVAC97_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ); 3338 3307 3339 int rc = VINF_SUCCESS; 3340 3341 uint32_t index = uPort - pThis->IOPortBase[0]; 3342 Assert(index < 256); 3343 3344 switch (cbVal) 3308 VBOXSTRICTRC rc = VINF_SUCCESS; 3309 3310 Assert(offPort < 256); 3311 3312 switch (cb) 3345 3313 { 3346 3314 case 1: 3347 3315 { 3348 LogRel2(("AC97: Warning: Unimplemented read ( %u byte) port=%#x, idx=%RU32\n", cbVal, uPort, index));3316 LogRel2(("AC97: Warning: Unimplemented read (1 byte) offPort=%#x\n", offPort)); 3349 3317 pThis->cas = 0; 3350 *pu32 Val= UINT32_MAX;3318 *pu32 = UINT32_MAX; 3351 3319 break; 3352 3320 } … … 3355 3323 { 3356 3324 pThis->cas = 0; 3357 *pu32 Val = ichac97MixerGet(pThis, index);3325 *pu32 = ichac97MixerGet(pThis, offPort); 3358 3326 break; 3359 3327 } … … 3361 3329 case 4: 3362 3330 { 3363 LogRel2(("AC97: Warning: Unimplemented read ( %u byte) port=%#x, idx=%RU32\n", cbVal, uPort, index));3331 LogRel2(("AC97: Warning: Unimplemented read (4 bytes) offPort=%#x\n", offPort)); 3364 3332 pThis->cas = 0; 3365 *pu32 Val= UINT32_MAX;3333 *pu32 = UINT32_MAX; 3366 3334 break; 3367 3335 } … … 3375 3343 3376 3344 DEVAC97_UNLOCK(pThis); 3377 3378 3345 return rc; 3379 3346 } 3380 3347 3381 3348 /** 3382 * Port I/O Handler for OUT operations. 3383 * 3384 * @returns VINF_SUCCESS or VINF_EM_*. 3385 * 3386 * @param pDevIns The device instance. 3387 * @param pvUser User argument. 3388 * @param uPort Port number used for the OUT operation. 3389 * @param u32Val The value to output. 3390 * @param cbVal The value size in bytes. 3391 * @remarks Caller enters the device critical section. 3392 */ 3393 PDMBOTHCBDECL(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32Val, unsigned cbVal) 3349 * @callback_method_impl{FNIOMIOPORTNEWOUT} 3350 */ 3351 static DECLCALLBACK(VBOXSTRICTRC) 3352 ichac97IoPortNamWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb) 3394 3353 { 3395 3354 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE); … … 3398 3357 DEVAC97_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE); 3399 3358 3400 uint32_t uPortIdx = uPort - pThis->IOPortBase[0]; 3401 3402 int rc = VINF_SUCCESS; 3403 switch (cbVal) 3359 VBOXSTRICTRC rc = VINF_SUCCESS; 3360 switch (cb) 3404 3361 { 3405 3362 case 1: 3406 3363 { 3407 LogRel2(("AC97: Warning: Unimplemented NAMWrite ( %u byte) port=%#x, idx=0x%x <- %#x\n", cbVal, uPort, uPortIdx, u32Val));3364 LogRel2(("AC97: Warning: Unimplemented NAMWrite (1 byte) offPort=%#x <- %#x\n", offPort, u32)); 3408 3365 pThis->cas = 0; 3409 3366 break; … … 3413 3370 { 3414 3371 pThis->cas = 0; 3415 switch ( uPortIdx)3372 switch (offPort) 3416 3373 { 3417 3374 case AC97_Reset: … … 3423 3380 break; 3424 3381 case AC97_Powerdown_Ctrl_Stat: 3425 u32 Val&= ~0xf;3426 u32 Val |= ichac97MixerGet(pThis, uPortIdx) & 0xf;3427 ichac97MixerSet(pThis, uPortIdx, u32Val);3382 u32 &= ~0xf; 3383 u32 |= ichac97MixerGet(pThis, offPort) & 0xf; 3384 ichac97MixerSet(pThis, offPort, u32); 3428 3385 break; 3429 3386 case AC97_Master_Volume_Mute: … … 3434 3391 } 3435 3392 #ifdef IN_RING3 3436 ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32Val);3393 ichac97R3MixerSetVolume(pThis, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32); 3437 3394 #else 3438 3395 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3446 3403 /* Register controls PCM (front) outputs. */ 3447 3404 #ifdef IN_RING3 3448 ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32Val);3405 ichac97R3MixerSetVolume(pThis, offPort, PDMAUDIOMIXERCTL_VOLUME_MASTER, u32); 3449 3406 #else 3450 3407 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3455 3412 case AC97_PCM_Out_Volume_Mute: 3456 3413 #ifdef IN_RING3 3457 ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_FRONT, u32Val);3414 ichac97R3MixerSetVolume(pThis, offPort, PDMAUDIOMIXERCTL_FRONT, u32); 3458 3415 #else 3459 3416 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3462 3419 case AC97_Line_In_Volume_Mute: 3463 3420 #ifdef IN_RING3 3464 ichac97R3MixerSetVolume(pThis, uPortIdx, PDMAUDIOMIXERCTL_LINE_IN, u32Val);3421 ichac97R3MixerSetVolume(pThis, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32); 3465 3422 #else 3466 3423 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3469 3426 case AC97_Record_Select: 3470 3427 #ifdef IN_RING3 3471 ichac97R3MixerRecordSelect(pThis, u32 Val);3428 ichac97R3MixerRecordSelect(pThis, u32); 3472 3429 #else 3473 3430 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3478 3435 /* Newer Ubuntu guests rely on that when controlling gain and muting 3479 3436 * the recording (capturing) levels. */ 3480 ichac97R3MixerSetGain(pThis, uPortIdx, PDMAUDIOMIXERCTL_LINE_IN, u32Val);3437 ichac97R3MixerSetGain(pThis, offPort, PDMAUDIOMIXERCTL_LINE_IN, u32); 3481 3438 #else 3482 3439 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3486 3443 #ifdef IN_RING3 3487 3444 /* Ditto; see note above. */ 3488 ichac97R3MixerSetGain(pThis, uPortIdx, PDMAUDIOMIXERCTL_MIC_IN, u32Val);3445 ichac97R3MixerSetGain(pThis, offPort, PDMAUDIOMIXERCTL_MIC_IN, u32); 3489 3446 #else 3490 3447 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3493 3450 case AC97_Vendor_ID1: 3494 3451 case AC97_Vendor_ID2: 3495 LogFunc(("Attempt to write vendor ID to %#x\n", u32 Val));3452 LogFunc(("Attempt to write vendor ID to %#x\n", u32)); 3496 3453 break; 3497 3454 case AC97_Extended_Audio_ID: 3498 LogFunc(("Attempt to write extended audio ID to %#x\n", u32 Val));3455 LogFunc(("Attempt to write extended audio ID to %#x\n", u32)); 3499 3456 break; 3500 3457 case AC97_Extended_Audio_Ctrl_Stat: … … 3503 3460 * Handle VRA bits. 3504 3461 */ 3505 if (!(u32 Val& AC97_EACS_VRA)) /* Check if VRA bit is not set. */3462 if (!(u32 & AC97_EACS_VRA)) /* Check if VRA bit is not set. */ 3506 3463 { 3507 3464 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); /* Set default (48000 Hz). */ … … 3517 3474 * Handle VRM bits. 3518 3475 */ 3519 if (!(u32 Val& AC97_EACS_VRM)) /* Check if VRM bit is not set. */3476 if (!(u32 & AC97_EACS_VRM)) /* Check if VRM bit is not set. */ 3520 3477 { 3521 3478 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 0xbb80); /* Set default (48000 Hz). */ … … 3525 3482 LogRel2(("AC97: Variable rate microphone audio (VRM) is not supported\n")); 3526 3483 3527 LogRel2(("AC97: Setting extended audio control to %#x\n", u32 Val));3528 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32 Val);3484 LogRel2(("AC97: Setting extended audio control to %#x\n", u32)); 3485 ichac97MixerSet(pThis, AC97_Extended_Audio_Ctrl_Stat, u32); 3529 3486 #else /* !IN_RING3 */ 3530 3487 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3535 3492 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA) 3536 3493 { 3537 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32 Val));3538 ichac97MixerSet(pThis, uPortIdx, u32Val);3494 LogRel2(("AC97: Setting front DAC rate to 0x%x\n", u32)); 3495 ichac97MixerSet(pThis, offPort, u32); 3539 3496 ichac97R3StreamReOpen(pThis, &pThis->aStreams[AC97SOUNDSOURCE_PO_INDEX], true /* fForce */); 3540 3497 } 3541 3498 else 3542 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32 Val));3499 LogRel2(("AC97: Setting front DAC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32)); 3543 3500 #else 3544 3501 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3549 3506 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM) 3550 3507 { 3551 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32 Val));3552 ichac97MixerSet(pThis, uPortIdx, u32Val);3508 LogRel2(("AC97: Setting microphone ADC rate to 0x%x\n", u32)); 3509 ichac97MixerSet(pThis, offPort, u32); 3553 3510 ichac97R3StreamReOpen(pThis, &pThis->aStreams[AC97SOUNDSOURCE_MC_INDEX], true /* fForce */); 3554 3511 } 3555 3512 else 3556 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", 3557 u32Val)); 3513 LogRel2(("AC97: Setting microphone ADC rate (0x%x) when VRM is not set is forbidden, ignoring\n", u32)); 3558 3514 #else 3559 3515 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3564 3520 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA) 3565 3521 { 3566 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32 Val));3567 ichac97MixerSet(pThis, uPortIdx, u32Val);3522 LogRel2(("AC97: Setting line-in ADC rate to 0x%x\n", u32)); 3523 ichac97MixerSet(pThis, offPort, u32); 3568 3524 ichac97R3StreamReOpen(pThis, &pThis->aStreams[AC97SOUNDSOURCE_PI_INDEX], true /* fForce */); 3569 3525 } 3570 3526 else 3571 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32 Val));3527 LogRel2(("AC97: Setting line-in ADC rate (0x%x) when VRA is not set is forbidden, ignoring\n", u32)); 3572 3528 #else 3573 3529 rc = VINF_IOM_R3_IOPORT_WRITE; … … 3575 3531 break; 3576 3532 default: 3577 LogRel2(("AC97: Warning: Unimplemented NAMWrite ( %u byte) port=%#x, idx=0x%x <- %#x\n", cbVal, uPort, uPortIdx, u32Val));3578 ichac97MixerSet(pThis, uPortIdx, u32Val);3533 LogRel2(("AC97: Warning: Unimplemented NAMWrite (2 bytes) offPort=%#x <- %#x\n", offPort, u32)); 3534 ichac97MixerSet(pThis, offPort, u32); 3579 3535 break; 3580 3536 } … … 3584 3540 case 4: 3585 3541 { 3586 LogRel2(("AC97: Warning: Unimplemented NAMWrite (%u byte) port=%#x, idx=0x%x <- %#x\n", cbVal, uPort, uPortIdx, u32Val));3542 LogRel2(("AC97: Warning: Unimplemented 4 byte NAMWrite: offPort=%#x <- %#x\n", offPort, u32)); 3587 3543 pThis->cas = 0; 3588 3544 break; … … 3590 3546 3591 3547 default: 3592 AssertMsgFailed(("Unhandled NAMWrite port=%#x, cbVal=%u u32Val=%#x\n", uPort, cbVal, u32Val));3548 AssertMsgFailed(("Unhandled NAMWrite offPort=%#x, cb=%u u32=%#x\n", offPort, cb, u32)); 3593 3549 break; 3594 3550 } 3595 3551 3596 3552 DEVAC97_UNLOCK(pThis); 3597 3598 3553 return rc; 3599 3554 } 3600 3555 3601 3556 #ifdef IN_RING3 3602 3603 /**3604 * @callback_method_impl{FNPCIIOREGIONMAP}3605 */3606 static DECLCALLBACK(int) ichac97R3IOPortMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,3607 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)3608 {3609 PAC97STATE pThis = PDMDEVINS_2_DATA(pDevIns, PAC97STATE);3610 RTIOPORT Port = (RTIOPORT)GCPhysAddress;3611 RT_NOREF(pPciDev, cb, enmType);3612 3613 Assert(enmType == PCI_ADDRESS_SPACE_IO);3614 Assert(cb >= 0x20);3615 AssertReturn(iRegion <= 1, VERR_INVALID_PARAMETER); /* We support 2 regions max. at the moment. */3616 Assert(pPciDev == pDevIns->apPciDevs[0]);3617 3618 3619 int rc;3620 if (iRegion == 0)3621 {3622 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, NULL, ichac97IOPortNAMWrite, ichac97IOPortNAMRead,3623 NULL, NULL, "ICHAC97 NAM");3624 AssertRCReturn(rc, rc);3625 if (pThis->fRZEnabled)3626 {3627 rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port, 256, NIL_RTR0PTR, "ichac97IOPortNAMWrite", "ichac97IOPortNAMRead",3628 NULL, NULL, "ICHAC97 NAM");3629 AssertRCReturn(rc, rc);3630 rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 256, NIL_RTRCPTR, "ichac97IOPortNAMWrite", "ichac97IOPortNAMRead",3631 NULL, NULL, "ICHAC97 NAM");3632 AssertRCReturn(rc, rc);3633 }3634 }3635 else3636 {3637 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, NULL, ichac97IOPortNABMWrite, ichac97IOPortNABMRead,3638 NULL, NULL, "ICHAC97 NABM");3639 AssertRCReturn(rc, rc);3640 if (pThis->fRZEnabled)3641 {3642 rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port, 64, NIL_RTR0PTR, "ichac97IOPortNABMWrite", "ichac97IOPortNABMRead",3643 NULL, NULL, "ICHAC97 NABM");3644 AssertRCReturn(rc, rc);3645 rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 64, NIL_RTRCPTR, "ichac97IOPortNABMWrite", "ichac97IOPortNABMRead",3646 NULL, NULL, "ICHAC97 NABM");3647 AssertRCReturn(rc, rc);3648 3649 }3650 }3651 3652 pThis->IOPortBase[iRegion] = Port;3653 return VINF_SUCCESS;3654 }3655 3656 3557 3657 3558 /** … … 4265 4166 4266 4167 /* 4267 * Register the PCI device, it's I/O regions, the timer and the 4268 * saved state item. 4168 * Register the PCI device and associated I/O regions. 4269 4169 */ 4270 4170 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev); … … 4272 4172 return rc; 4273 4173 4274 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97R3IOPortMap); 4275 if (RT_FAILURE(rc)) 4276 return rc; 4277 4278 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97R3IOPortMap); 4279 if (RT_FAILURE(rc)) 4280 return rc; 4281 4174 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 0 /*iPciRegion*/, 256 /*cPorts*/, 4175 ichac97IoPortNamWrite, ichac97IoPortNamRead, NULL /*pvUser*/, 4176 "ICHAC97 NAM", NULL /*paExtDescs*/, &pThis->hIoPortsNam); 4177 AssertRCReturn(rc, rc); 4178 4179 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/, 4180 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/, 4181 "ICHAC97 NABM", NULL /*paExtDescs*/, &pThis->hIoPortsNabm); 4182 AssertRCReturn(rc, rc); 4183 4184 /* 4185 * Saved state. 4186 */ 4282 4187 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97R3SaveExec, ichac97R3LoadExec); 4283 4188 if (RT_FAILURE(rc))
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