Changeset 82359 in vbox for trunk/src/VBox/Devices/Audio
- Timestamp:
- Dec 3, 2019 10:35:02 PM (5 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r82358 r82359 59 59 #define AC97_FIFO_MAX 256 60 60 61 #define AC97_SR_FIFOE RT_BIT(4)/**< rwc, FIFO error. */62 #define AC97_SR_BCIS RT_BIT(3)/**< rwc, Buffer completion interrupt status. */63 #define AC97_SR_LVBCI RT_BIT(2)/**< rwc, Last valid buffer completion interrupt. */64 #define AC97_SR_CELV RT_BIT(1)/**< ro, Current equals last valid. */65 #define AC97_SR_DCH RT_BIT(0)/**< ro, Controller halted. */66 #define AC97_SR_VALID_MASK (RT_BIT(5) - 1)67 #define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)68 #define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)69 #define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)70 71 #define AC97_CR_IOCE RT_BIT(4)/**< rw, Interrupt On Completion Enable. */72 #define AC97_CR_FEIE RT_BIT(3)/**< rw FIFO Error Interrupt Enable. */73 #define AC97_CR_LVBIE RT_BIT(2)/**< rw Last Valid Buffer Interrupt Enable. */74 #define AC97_CR_RR RT_BIT(1)/**< rw Reset Registers. */75 #define AC97_CR_RPBM RT_BIT(0)/**< rw Run/Pause Bus Master. */76 #define AC97_CR_VALID_MASK (RT_BIT(5) - 1)61 #define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */ 62 #define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */ 63 #define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */ 64 #define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */ 65 #define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */ 66 #define AC97_SR_VALID_MASK (RT_BIT(5) - 1) 67 #define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI) 68 #define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV) 69 #define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI) 70 71 #define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */ 72 #define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */ 73 #define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */ 74 #define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */ 75 #define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */ 76 #define AC97_CR_VALID_MASK (RT_BIT(5) - 1) 77 77 #define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE) 78 78 79 #define AC97_GC_WR 4/**< rw Warm reset. */80 #define AC97_GC_CR 2/**< rw Cold reset. */81 #define AC97_GC_VALID_MASK (RT_BIT(6) - 1)82 83 #define AC97_GS_MD3 RT_BIT(17)/**< rw */84 #define AC97_GS_AD3 RT_BIT(16)/**< rw */85 #define AC97_GS_RCS RT_BIT(15)/**< rwc */86 #define AC97_GS_B3S12 RT_BIT(14)/**< ro */87 #define AC97_GS_B2S12 RT_BIT(13)/**< ro */88 #define AC97_GS_B1S12 RT_BIT(12)/**< ro */89 #define AC97_GS_S1R1 RT_BIT(11)/**< rwc */90 #define AC97_GS_S0R1 RT_BIT(10)/**< rwc */91 #define AC97_GS_S1CR RT_BIT(9)/**< ro */92 #define AC97_GS_S0CR RT_BIT(8)/**< ro */93 #define AC97_GS_MINT RT_BIT(7)/**< ro */94 #define AC97_GS_POINT RT_BIT(6)/**< ro */95 #define AC97_GS_PIINT RT_BIT(5)/**< ro */96 #define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3))97 #define AC97_GS_MOINT RT_BIT(2)/**< ro */98 #define AC97_GS_MIINT RT_BIT(1)/**< ro */99 #define AC97_GS_GSCI RT_BIT(0)/**< rwc */100 #define AC97_GS_RO_MASK ( AC97_GS_B3S12 \101 | AC97_GS_B2S12 \102 | AC97_GS_B1S12 \103 | AC97_GS_S1CR \104 | AC97_GS_S0CR \105 | AC97_GS_MINT \106 | AC97_GS_POINT \107 | AC97_GS_PIINT \108 | AC97_GS_RSRVD \109 | AC97_GS_MOINT \110 | AC97_GS_MIINT)111 #define AC97_GS_VALID_MASK (RT_BIT(18) - 1)112 #define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI)79 #define AC97_GC_WR 4 /**< rw Warm reset. */ 80 #define AC97_GC_CR 2 /**< rw Cold reset. */ 81 #define AC97_GC_VALID_MASK (RT_BIT(6) - 1) 82 83 #define AC97_GS_MD3 RT_BIT(17) /**< rw */ 84 #define AC97_GS_AD3 RT_BIT(16) /**< rw */ 85 #define AC97_GS_RCS RT_BIT(15) /**< rwc */ 86 #define AC97_GS_B3S12 RT_BIT(14) /**< ro */ 87 #define AC97_GS_B2S12 RT_BIT(13) /**< ro */ 88 #define AC97_GS_B1S12 RT_BIT(12) /**< ro */ 89 #define AC97_GS_S1R1 RT_BIT(11) /**< rwc */ 90 #define AC97_GS_S0R1 RT_BIT(10) /**< rwc */ 91 #define AC97_GS_S1CR RT_BIT(9) /**< ro */ 92 #define AC97_GS_S0CR RT_BIT(8) /**< ro */ 93 #define AC97_GS_MINT RT_BIT(7) /**< ro */ 94 #define AC97_GS_POINT RT_BIT(6) /**< ro */ 95 #define AC97_GS_PIINT RT_BIT(5) /**< ro */ 96 #define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3)) 97 #define AC97_GS_MOINT RT_BIT(2) /**< ro */ 98 #define AC97_GS_MIINT RT_BIT(1) /**< ro */ 99 #define AC97_GS_GSCI RT_BIT(0) /**< rwc */ 100 #define AC97_GS_RO_MASK ( AC97_GS_B3S12 \ 101 | AC97_GS_B2S12 \ 102 | AC97_GS_B1S12 \ 103 | AC97_GS_S1CR \ 104 | AC97_GS_S0CR \ 105 | AC97_GS_MINT \ 106 | AC97_GS_POINT \ 107 | AC97_GS_PIINT \ 108 | AC97_GS_RSRVD \ 109 | AC97_GS_MOINT \ 110 | AC97_GS_MIINT) 111 #define AC97_GS_VALID_MASK (RT_BIT(18) - 1) 112 #define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI) 113 113 114 114 /** @name Buffer Descriptor (BD). … … 124 124 /** @name Extended Audio ID Register (EAID). 125 125 * @{ */ 126 #define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */127 #define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */128 #define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */129 #define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */126 #define AC97_EAID_VRA RT_BIT(0) /**< Variable Rate Audio. */ 127 #define AC97_EAID_VRM RT_BIT(3) /**< Variable Rate Mic Audio. */ 128 #define AC97_EAID_REV0 RT_BIT(10) /**< AC'97 revision compliance. */ 129 #define AC97_EAID_REV1 RT_BIT(11) /**< AC'97 revision compliance. */ 130 130 /** @} */ 131 131 132 132 /** @name Extended Audio Control and Status Register (EACS). 133 133 * @{ */ 134 #define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */135 #define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */134 #define AC97_EACS_VRA RT_BIT(0) /**< Variable Rate Audio (4.2.1.1). */ 135 #define AC97_EACS_VRM RT_BIT(3) /**< Variable Rate Mic Audio (4.2.1.1). */ 136 136 /** @} */ 137 137 138 138 /** @name Baseline Audio Register Set (BARS). 139 139 * @{ */ 140 #define AC97_BARS_VOL_MASK 0x1f/**< Volume mask for the Baseline Audio Register Set (5.7.2). */141 #define AC97_BARS_GAIN_MASK 0x0f/**< Gain mask for the Baseline Audio Register Set. */142 #define AC97_BARS_VOL_MUTE_SHIFT 15/**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */140 #define AC97_BARS_VOL_MASK 0x1f /**< Volume mask for the Baseline Audio Register Set (5.7.2). */ 141 #define AC97_BARS_GAIN_MASK 0x0f /**< Gain mask for the Baseline Audio Register Set. */ 142 #define AC97_BARS_VOL_MUTE_SHIFT 15 /**< Mute bit shift for the Baseline Audio Register Set (5.7.2). */ 143 143 /** @} */ 144 144 145 145 /** AC'97 uses 1.5dB steps, we use 0.375dB steps: 1 AC'97 step equals 4 PDM steps. */ 146 #define AC97_DB_FACTOR 146 #define AC97_DB_FACTOR 4 147 147 148 148 #define AC97_REC_MASK 7 … … 163 163 AC97_Reset = 0x00, 164 164 AC97_Master_Volume_Mute = 0x02, 165 AC97_Headphone_Volume_Mute = 0x04, /** Also known as AUX, see table 16, section 5.7. */165 AC97_Headphone_Volume_Mute = 0x04, /**< Also known as AUX, see table 16, section 5.7. */ 166 166 AC97_Master_Volume_Mono_Mute = 0x06, 167 167 AC97_Master_Tone_RL = 0x08, 168 AC97_PC_BEEP_Volume_Mute = 0x0 A,169 AC97_Phone_Volume_Mute = 0x0 C,170 AC97_Mic_Volume_Mute = 0x0 E,168 AC97_PC_BEEP_Volume_Mute = 0x0a, 169 AC97_Phone_Volume_Mute = 0x0c, 170 AC97_Mic_Volume_Mute = 0x0e, 171 171 AC97_Line_In_Volume_Mute = 0x10, 172 172 AC97_CD_Volume_Mute = 0x12, … … 174 174 AC97_Aux_Volume_Mute = 0x16, 175 175 AC97_PCM_Out_Volume_Mute = 0x18, 176 AC97_Record_Select = 0x1 A,177 AC97_Record_Gain_Mute = 0x1 C,178 AC97_Record_Gain_Mic_Mute = 0x1 E,176 AC97_Record_Select = 0x1a, 177 AC97_Record_Gain_Mute = 0x1c, 178 AC97_Record_Gain_Mic_Mute = 0x1e, 179 179 AC97_General_Purpose = 0x20, 180 180 AC97_3D_Control = 0x22, … … 182 182 AC97_Powerdown_Ctrl_Stat = 0x26, 183 183 AC97_Extended_Audio_ID = 0x28, 184 AC97_Extended_Audio_Ctrl_Stat = 0x2 A,185 AC97_PCM_Front_DAC_Rate = 0x2 C,186 AC97_PCM_Surround_DAC_Rate = 0x2 E,184 AC97_Extended_Audio_Ctrl_Stat = 0x2a, 185 AC97_PCM_Front_DAC_Rate = 0x2c, 186 AC97_PCM_Surround_DAC_Rate = 0x2e, 187 187 AC97_PCM_LFE_DAC_Rate = 0x30, 188 188 AC97_PCM_LR_ADC_Rate = 0x32, … … 199 199 typedef enum 200 200 { 201 AC97_CODEC_STAC9700 = 0, /**< SigmaTel STAC9700 */201 AC97_CODEC_STAC9700 = 1, /**< SigmaTel STAC9700 */ 202 202 AC97_CODEC_AD1980, /**< Analog Devices AD1980 */ 203 203 AC97_CODEC_AD1981B /**< Analog Devices AD1981B */
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