Changeset 82377 in vbox for trunk/src/VBox/Devices/Audio
- Timestamp:
- Dec 4, 2019 11:51:50 AM (5 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (15 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r82374 r82377 273 273 /** @name Misc NABM BAR registers. 274 274 * @{ */ 275 /** NABMBAR: Global Control Register. */ 275 /** NABMBAR: Global Control Register. 276 * @note This is kind of in the MIC IN area. */ 276 277 #define AC97_GLOB_CNT 0x2c 277 278 /** NABMBAR: Global Status. */ … … 562 563 IOMIOPORTHANDLE hIoPortsNabm; 563 564 565 STAMCOUNTER StatUnimplementedNabmReads; 566 STAMCOUNTER StatUnimplementedNabmWrites; 564 567 #ifdef VBOX_WITH_STATISTICS 565 568 STAMPROFILE StatTimer; … … 571 574 } AC97STATE; 572 575 AssertCompileMemberAlignment(AC97STATE, aStreams, 8); 576 AssertCompileMemberAlignment(AC97STATE, StatUnimplementedNabmReads, 8); 573 577 #ifdef VBOX_WITH_STATISTICS 574 578 AssertCompileMemberAlignment(AC97STATE, StatTimer, 8); … … 695 699 #endif /* IN_RING3 */ 696 700 701 702 /********************************************************************************************************************************* 703 * Global Variables * 704 *********************************************************************************************************************************/ 705 #ifdef IN_RING3 706 /** NABM I/O port descriptions. */ 707 static const IOMIOPORTDESC g_aNabmPorts[] = 708 { 709 { "PCM IN - BDBAR", "PCM IN - BDBAR", NULL, NULL }, 710 { "", NULL, NULL, NULL }, 711 { "", NULL, NULL, NULL }, 712 { "", NULL, NULL, NULL }, 713 { "PCM IN - CIV", "PCM IN - CIV", NULL, NULL }, 714 { "PCM IN - LVI", "PCM IN - LIV", NULL, NULL }, 715 { "PCM IN - SR", "PCM IN - SR", NULL, NULL }, 716 { "", NULL, NULL, NULL }, 717 { "PCM IN - PICB", "PCM IN - PICB", NULL, NULL }, 718 { "", NULL, NULL, NULL }, 719 { "PCM IN - PIV", "PCM IN - PIV", NULL, NULL }, 720 { "PCM IN - CR", "PCM IN - CR", NULL, NULL }, 721 { "", NULL, NULL, NULL }, 722 { "", NULL, NULL, NULL }, 723 { "", NULL, NULL, NULL }, 724 { "", NULL, NULL, NULL }, 725 726 { "PCM OUT - BDBAR", "PCM OUT - BDBAR", NULL, NULL }, 727 { "", NULL, NULL, NULL }, 728 { "", NULL, NULL, NULL }, 729 { "", NULL, NULL, NULL }, 730 { "PCM OUT - CIV", "PCM OUT - CIV", NULL, NULL }, 731 { "PCM OUT - LVI", "PCM OUT - LIV", NULL, NULL }, 732 { "PCM OUT - SR", "PCM OUT - SR", NULL, NULL }, 733 { "", NULL, NULL, NULL }, 734 { "PCM OUT - PICB", "PCM OUT - PICB", NULL, NULL }, 735 { "", NULL, NULL, NULL }, 736 { "PCM OUT - PIV", "PCM OUT - PIV", NULL, NULL }, 737 { "PCM OUT - CR", "PCM IN - CR", NULL, NULL }, 738 { "", NULL, NULL, NULL }, 739 { "", NULL, NULL, NULL }, 740 { "", NULL, NULL, NULL }, 741 { "", NULL, NULL, NULL }, 742 743 { "MIC IN - BDBAR", "MIC IN - BDBAR", NULL, NULL }, 744 { "", NULL, NULL, NULL }, 745 { "", NULL, NULL, NULL }, 746 { "", NULL, NULL, NULL }, 747 { "MIC IN - CIV", "MIC IN - CIV", NULL, NULL }, 748 { "MIC IN - LVI", "MIC IN - LIV", NULL, NULL }, 749 { "MIC IN - SR", "MIC IN - SR", NULL, NULL }, 750 { "", NULL, NULL, NULL }, 751 { "MIC IN - PICB", "MIC IN - PICB", NULL, NULL }, 752 { "", NULL, NULL, NULL }, 753 { "MIC IN - PIV", "MIC IN - PIV", NULL, NULL }, 754 { "MIC IN - CR", "MIC IN - CR", NULL, NULL }, 755 { "GLOB CNT", "GLOB CNT", NULL, NULL }, 756 { "", NULL, NULL, NULL }, 757 { "", NULL, NULL, NULL }, 758 { "", NULL, NULL, NULL }, 759 760 { "GLOB STA", "GLOB STA", NULL, NULL }, 761 { "", NULL, NULL, NULL }, 762 { "", NULL, NULL, NULL }, 763 { "", NULL, NULL, NULL }, 764 { "CAS", "CAS", NULL, NULL }, 765 { NULL, NULL, NULL, NULL }, 766 }; 767 768 #define AC97SOUNDSOURCE_PI_INDEX 0 /**< PCM in */ 769 #define AC97SOUNDSOURCE_PO_INDEX 1 /**< PCM out */ 770 #define AC97SOUNDSOURCE_MC_INDEX 2 /**< Mic in */ 771 #define AC97SOUNDSOURCE_MAX 3 /**< Max sound sources. */ 772 /** @} */ 773 774 /** Port number (offset into NABM BAR) to stream index. */ 775 #define AC97_PORT2IDX(a_idx) ( ((a_idx) >> 4) & 3 ) 776 /** Port number (offset into NABM BAR) to stream index, but no masking. */ 777 #define AC97_PORT2IDX_UNMASKED(a_idx) ( ((a_idx) >> 4) ) 778 779 /** @name Stream offsets 780 * @{ */ 781 #define AC97_NABM_OFF_BDBAR 0x0 /**< Buffer Descriptor Base Address */ 782 #define AC97_NABM_OFF_CIV 0x4 /**< Current Index Value */ 783 #define AC97_NABM_OFF_LVI 0x5 /**< Last Valid Index */ 784 #define AC97_NABM_OFF_SR 0x6 /**< Status Register */ 785 #define AC97_NABM_OFF_PICB 0x8 /**< Position in Current Buffer */ 786 #define AC97_NABM_OFF_PIV 0xa /**< Prefetched Index Value */ 787 #define AC97_NABM_OFF_CR 0xb /**< Control Register */ 788 #define AC97_NABM_OFF_MASK 0xf /**< Mask for getting the the per-stream register. */ 789 790 #endif 791 792 793 697 794 static void ichac97WarmReset(PAC97STATE pThis) 698 795 { … … 704 801 NOREF(pThis); 705 802 } 803 706 804 707 805 #ifdef IN_RING3 … … 2891 2989 2892 2990 /* Get the index of the NABMBAR port. */ 2893 if (AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS) 2991 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS 2992 && offPort != AC97_GLOB_CNT) 2894 2993 { 2895 2994 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)]; … … 2929 3028 *pu32 = UINT32_MAX; 2930 3029 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX)); 3030 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads); 2931 3031 break; 2932 3032 } … … 2949 3049 *pu32 = UINT32_MAX; 2950 3050 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX)); 3051 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads); 2951 3052 break; 2952 3053 } … … 2977 3078 AC97_PORT2IDX(offPort), *pu32, pRegs->picb, pRegs->piv, pRegs->cr)); 2978 3079 break; 3080 2979 3081 default: 2980 3082 *pu32 = UINT32_MAX; 2981 3083 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX)); 3084 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads); 2982 3085 break; 2983 3086 } … … 3006 3109 *pu32 = UINT32_MAX; 3007 3110 LogFunc(("U nabm readb %#x -> %#x\n", offPort, UINT32_MAX)); 3111 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads); 3008 3112 break; 3009 3113 } … … 3013 3117 *pu32 = UINT32_MAX; 3014 3118 LogFunc(("U nabm readw %#x -> %#x\n", offPort, UINT32_MAX)); 3119 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads); 3015 3120 break; 3016 3121 … … 3031 3136 *pu32 = UINT32_MAX; 3032 3137 LogFunc(("U nabm readl %#x -> %#x\n", offPort, UINT32_MAX)); 3138 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmReads); 3033 3139 break; 3034 3140 } … … 3058 3164 RT_NOREF(pvUser); 3059 3165 3166 VBOXSTRICTRC rc = VINF_SUCCESS; 3167 if ( AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS 3168 && offPort != AC97_GLOB_CNT) 3169 { 3060 3170 #ifdef IN_RING3 3061 PAC97STREAMR3 pStreamCC = NULL;3171 PAC97STREAMR3 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)]; 3062 3172 #endif 3063 PAC97STREAM pStream = NULL; 3064 PAC97BMREGS pRegs = NULL; 3065 if (AC97_PORT2IDX_UNMASKED(offPort) < AC97_MAX_STREAMS) 3066 { 3173 PAC97STREAM pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)]; 3174 PAC97BMREGS pRegs = &pStream->Regs; 3175 3176 DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE); 3177 switch (cb) 3178 { 3179 case 1: 3180 switch (offPort & AC97_NABM_OFF_MASK) 3181 { 3182 /* 3183 * Last Valid Index. 3184 */ 3185 case AC97_NABM_OFF_LVI: 3186 if ( (pRegs->cr & AC97_CR_RPBM) 3187 && (pRegs->sr & AC97_SR_DCH)) 3188 { 3067 3189 #ifdef IN_RING3 3068 pStreamCC = &pThisCC->aStreams[AC97_PORT2IDX(offPort)]; 3190 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV); 3191 pRegs->civ = pRegs->piv; 3192 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE; 3193 #else 3194 rc = VINF_IOM_R3_IOPORT_WRITE; 3069 3195 #endif 3070 pStream = &pThis->aStreams[AC97_PORT2IDX(offPort)]; 3071 pRegs = &pStream->Regs; 3072 3073 DEVAC97_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_IOPORT_WRITE); 3074 } 3075 3076 VBOXSTRICTRC rc = VINF_SUCCESS; 3077 switch (cb) 3078 { 3079 case 1: 3080 { 3081 switch (offPort) 3082 { 3083 /* 3084 * Last Valid Index. 3085 */ 3086 case PI_LVI: 3087 case PO_LVI: 3088 case MC_LVI: 3089 { 3090 AssertPtr(pStream); 3091 AssertPtr(pRegs); 3092 if ( (pRegs->cr & AC97_CR_RPBM) 3093 && (pRegs->sr & AC97_SR_DCH)) 3094 { 3196 } 3197 pRegs->lvi = u32 % AC97_MAX_BDLE; 3198 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32)); 3199 break; 3200 3201 /* 3202 * Control Registers. 3203 */ 3204 case AC97_NABM_OFF_CR: 3095 3205 #ifdef IN_RING3 3096 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV); 3097 pRegs->civ = pRegs->piv; 3098 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE; 3099 #else 3100 rc = VINF_IOM_R3_IOPORT_WRITE; 3101 #endif 3102 } 3103 pRegs->lvi = u32 % AC97_MAX_BDLE; 3104 Log3Func(("[SD%RU8] LVI <- %#x\n", pStream->u8SD, u32)); 3105 break; 3106 } 3107 3108 /* 3109 * Control Registers. 3110 */ 3111 case PI_CR: 3112 case PO_CR: 3113 case MC_CR: 3114 { 3115 AssertPtr(pStream); 3116 AssertPtr(pRegs); 3117 #ifdef IN_RING3 3118 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr)); 3119 if (u32 & AC97_CR_RR) /* Busmaster reset. */ 3120 { 3121 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD)); 3122 3123 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */ 3124 Assert((pRegs->cr & AC97_CR_RPBM) == 0); 3125 3126 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */); 3127 ichac97R3StreamReset(pThis, pStream, pStreamCC); 3128 3129 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */ 3130 } 3131 else 3132 { 3133 pRegs->cr = u32 & AC97_CR_VALID_MASK; 3134 3135 if (!(pRegs->cr & AC97_CR_RPBM)) 3206 Log3Func(("[SD%RU8] CR <- %#x (cr %#x)\n", pStream->u8SD, u32, pRegs->cr)); 3207 if (u32 & AC97_CR_RR) /* Busmaster reset. */ 3136 3208 { 3137 Log3Func(("[SD%RU8] Disable\n", pStream->u8SD)); 3209 Log3Func(("[SD%RU8] Reset\n", pStream->u8SD)); 3210 3211 /* Make sure that Run/Pause Bus Master bit (RPBM) is cleared (0). */ 3212 Assert((pRegs->cr & AC97_CR_RPBM) == 0); 3138 3213 3139 3214 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */); 3140 3141 pRegs->sr |= AC97_SR_DCH; 3215 ichac97R3StreamReset(pThis, pStream, pStreamCC); 3216 3217 ichac97StreamUpdateSR(pDevIns, pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */ 3142 3218 } 3143 3219 else 3144 3220 { 3145 Log3Func(("[SD%RU8] Enable\n", pStream->u8SD)); 3146 3147 pRegs->civ = pRegs->piv; 3148 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE; 3149 3150 pRegs->sr &= ~AC97_SR_DCH; 3151 3152 /* Fetch the initial BDLE descriptor. */ 3153 ichac97R3StreamFetchBDLE(pDevIns, pStream); 3221 pRegs->cr = u32 & AC97_CR_VALID_MASK; 3222 3223 if (!(pRegs->cr & AC97_CR_RPBM)) 3224 { 3225 Log3Func(("[SD%RU8] Disable\n", pStream->u8SD)); 3226 3227 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, false /* fEnable */); 3228 3229 pRegs->sr |= AC97_SR_DCH; 3230 } 3231 else 3232 { 3233 Log3Func(("[SD%RU8] Enable\n", pStream->u8SD)); 3234 3235 pRegs->civ = pRegs->piv; 3236 pRegs->piv = (pRegs->piv + 1) % AC97_MAX_BDLE; 3237 3238 pRegs->sr &= ~AC97_SR_DCH; 3239 3240 /* Fetch the initial BDLE descriptor. */ 3241 ichac97R3StreamFetchBDLE(pDevIns, pStream); 3154 3242 # ifdef LOG_ENABLED 3155 ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1);3243 ichac97R3BDLEDumpAll(pDevIns, pStream->Regs.bdbar, pStream->Regs.lvi + 1); 3156 3244 # endif 3157 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, true /* fEnable */); 3158 3159 /* Arm the timer for this stream. */ 3160 /** @todo r=bird: This function returns bool, not VBox status! */ 3161 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks); 3245 ichac97R3StreamEnable(pThis, pThisCC, pStream, pStreamCC, true /* fEnable */); 3246 3247 /* Arm the timer for this stream. */ 3248 /** @todo r=bird: This function returns bool, not VBox status! */ 3249 ichac97R3TimerSet(pDevIns, pStream, pStreamCC->State.cTransferTicks); 3250 } 3162 3251 } 3163 }3164 3252 #else /* !IN_RING3 */ 3165 rc = VINF_IOM_R3_IOPORT_WRITE;3253 rc = VINF_IOM_R3_IOPORT_WRITE; 3166 3254 #endif 3167 break; 3255 break; 3256 3257 /* 3258 * Status Registers. 3259 */ 3260 case AC97_NABM_OFF_SR: 3261 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32); 3262 break; 3263 3264 default: 3265 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32)); 3266 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites); 3267 break; 3168 3268 } 3169 3170 /* 3171 * Status Registers. 3172 */ 3173 case PI_SR: 3174 case PO_SR: 3175 case MC_SR: 3269 break; 3270 3271 case 2: 3272 switch (offPort & AC97_NABM_OFF_MASK) 3176 3273 { 3177 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32); 3178 break; 3274 case AC97_NABM_OFF_SR: 3275 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32); 3276 break; 3277 default: 3278 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32)); 3279 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites); 3280 break; 3179 3281 } 3180 3181 default: 3182 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32)); 3183 break; 3184 } 3185 break; 3186 } 3187 3188 case 2: 3189 { 3190 switch (offPort) 3191 { 3192 case PI_SR: 3193 case PO_SR: 3194 case MC_SR: 3195 ichac97StreamWriteSR(pDevIns, pThis, pStream, u32); 3196 break; 3197 default: 3198 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32)); 3199 break; 3200 } 3201 break; 3202 } 3203 3204 case 4: 3205 { 3206 switch (offPort) 3207 { 3208 case PI_BDBAR: 3209 case PO_BDBAR: 3210 case MC_BDBAR: 3211 AssertPtr(pStream); 3212 AssertPtr(pRegs); 3213 /* Buffer Descriptor list Base Address Register */ 3214 pRegs->bdbar = u32 & ~3; 3215 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar)); 3216 break; 3217 case AC97_GLOB_CNT: 3218 /* Global Control */ 3219 if (u32 & AC97_GC_WR) 3220 ichac97WarmReset(pThis); 3221 if (u32 & AC97_GC_CR) 3222 ichac97ColdReset(pThis); 3223 if (!(u32 & (AC97_GC_WR | AC97_GC_CR))) 3224 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK; 3225 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt)); 3226 break; 3227 case AC97_GLOB_STA: 3228 /* Global Status */ 3229 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK); 3230 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK; 3231 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta)); 3232 break; 3233 default: 3234 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32)); 3235 break; 3236 } 3237 break; 3238 } 3239 3240 default: 3241 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb)); 3242 break; 3243 } 3244 3245 if (pStream) 3282 break; 3283 3284 case 4: 3285 switch (offPort & AC97_NABM_OFF_MASK) 3286 { 3287 case AC97_NABM_OFF_BDBAR: 3288 /* Buffer Descriptor list Base Address Register */ 3289 pRegs->bdbar = u32 & ~3; 3290 Log3Func(("[SD%RU8] BDBAR <- %#x (bdbar %#x)\n", AC97_PORT2IDX(offPort), u32, pRegs->bdbar)); 3291 break; 3292 default: 3293 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32)); 3294 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites); 3295 break; 3296 } 3297 break; 3298 3299 default: 3300 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb)); 3301 break; 3302 } 3246 3303 DEVAC97_UNLOCK_BOTH(pDevIns, pThis, pStream); 3304 } 3305 else 3306 { 3307 switch (cb) 3308 { 3309 case 1: 3310 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 1\n", offPort, u32)); 3311 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites); 3312 break; 3313 3314 case 2: 3315 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 2\n", offPort, u32)); 3316 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites); 3317 break; 3318 3319 case 4: 3320 switch (offPort) 3321 { 3322 case AC97_GLOB_CNT: 3323 /* Global Control */ 3324 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE); 3325 if (u32 & AC97_GC_WR) 3326 ichac97WarmReset(pThis); 3327 if (u32 & AC97_GC_CR) 3328 ichac97ColdReset(pThis); 3329 if (!(u32 & (AC97_GC_WR | AC97_GC_CR))) 3330 pThis->glob_cnt = u32 & AC97_GC_VALID_MASK; 3331 Log3Func(("glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt)); 3332 DEVAC97_UNLOCK(pDevIns, pThis); 3333 break; 3334 case AC97_GLOB_STA: 3335 /* Global Status */ 3336 DEVAC97_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE); 3337 pThis->glob_sta &= ~(u32 & AC97_GS_WCLEAR_MASK); 3338 pThis->glob_sta |= (u32 & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK; 3339 Log3Func(("glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta)); 3340 DEVAC97_UNLOCK(pDevIns, pThis); 3341 break; 3342 default: 3343 LogRel2(("AC97: Warning: Unimplemented NABMWrite offPort=%#x <- %#x LB 4\n", offPort, u32)); 3344 STAM_REL_COUNTER_INC(&pThis->StatUnimplementedNabmWrites); 3345 break; 3346 } 3347 break; 3348 3349 default: 3350 AssertMsgFailed(("offPort=%#x <- %#x LB %u\n", offPort, u32, cb)); 3351 break; 3352 } 3353 } 3247 3354 3248 3355 return rc; … … 4122 4229 rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, 1 /*iPciRegion*/, 64 /*cPorts*/, 4123 4230 ichac97IoPortNabmWrite, ichac97IoPortNabmRead, NULL /*pvUser*/, 4124 "ICHAC97 NABM", NULL /*paExtDescs*/, &pThis->hIoPortsNabm);4231 "ICHAC97 NABM", g_aNabmPorts, &pThis->hIoPortsNabm); 4125 4232 AssertRCReturn(rc, rc); 4126 4233 … … 4303 4410 * Register statistics. 4304 4411 */ 4412 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmReads, STAMTYPE_COUNTER, "UnimplementedNabmReads", STAMUNIT_OCCURENCES, "Unimplemented NABM register reads."); 4413 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUnimplementedNabmWrites, STAMTYPE_COUNTER, "UnimplementedNabmWrites", STAMUNIT_OCCURENCES, "Unimplemented NABM register writes."); 4305 4414 # ifdef VBOX_WITH_STATISTICS 4306 4415 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling ichac97Timer.");
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