Index: trunk/src/VBox/Devices/Audio/AudioMixer.cpp
===================================================================
--- trunk/src/VBox/Devices/Audio/AudioMixer.cpp	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/AudioMixer.cpp	(revision 82406)
@@ -522,5 +522,5 @@
         && !(pSink->fStatus & AUDMIXSINK_STS_PENDING_DISABLE))
     {
-        rc = audioMixerStreamCtlInternal(pStream, PDMAUDIOSTREAMCMD_ENABLE, AUDMIXSTRMCTL_FLAG_NONE);
+        rc = audioMixerStreamCtlInternal(pStream, PDMAUDIOSTREAMCMD_ENABLE, AUDMIXSTRMCTL_F_NONE);
     }
 
@@ -729,5 +729,5 @@
             if (pStream == pSink->In.pStreamRecSource)
             {
-                int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_FLAG_NONE);
+                int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_F_NONE);
                 if (rc2 == VERR_NOT_SUPPORTED)
                     rc2 = VINF_SUCCESS;
@@ -743,5 +743,5 @@
         RTListForEach(&pSink->lstStreams, pStream, AUDMIXSTREAM, Node)
         {
-            int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_FLAG_NONE);
+            int rc2 = audioMixerStreamCtlInternal(pStream, enmCmdStream, AUDMIXSTRMCTL_F_NONE);
             if (rc2 == VERR_NOT_SUPPORTED)
                 rc2 = VINF_SUCCESS;
Index: trunk/src/VBox/Devices/Audio/AudioMixer.h
===================================================================
--- trunk/src/VBox/Devices/Audio/AudioMixer.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/AudioMixer.h	(revision 82406)
@@ -30,6 +30,11 @@
 #include <VBox/vmm/pdmaudioifs.h>
 
-/**
- * Structure for maintaining an audio mixer instance.
+
+/** Pointer to an audio mixer sink. */
+typedef struct AUDMIXSINK *PAUDMIXSINK;
+
+
+/**
+ * Audio mixer instance.
  */
 typedef struct AUDIOMIXER
@@ -45,5 +50,7 @@
     /** Number of used audio sinks. */
     uint8_t                 cSinks;
-} AUDIOMIXER, *PAUDIOMIXER;
+} AUDIOMIXER;
+/** Pointer to an audio mixer instance. */
+typedef AUDIOMIXER *PAUDIOMIXER;
 
 /** Defines an audio mixer stream's flags. */
@@ -51,7 +58,7 @@
 
 /** No flags specified. */
-#define AUDMIXSTREAM_FLAG_NONE                  0
+#define AUDMIXSTREAM_F_NONE                     0
 /** The mixing stream is flagged as being enabled (active). */
-#define AUDMIXSTREAM_FLAG_ENABLED               RT_BIT(0)
+#define AUDMIXSTREAM_F_ENABLED                  RT_BIT(0)
 
 /** Defines an audio mixer stream's internal status. */
@@ -68,9 +75,6 @@
 
 
-/** Prototype needed for AUDMIXSTREAM struct definition. */
-typedef struct AUDMIXSINK *PAUDMIXSINK;
-
-/**
- * Structure for maintaining an audio mixer stream.
+/**
+ * Audio mixer stream.
  */
 typedef struct AUDMIXSTREAM
@@ -84,5 +88,5 @@
     /** Sink this stream is attached to. */
     PAUDMIXSINK             pSink;
-    /** Stream flags of type AUDMIXSTREAM_FLAG_. */
+    /** Stream flags of type AUDMIXSTREAM_F_. */
     uint32_t                fFlags;
     /** Stream status of type AUDMIXSTREAM_STATUS_. */
@@ -153,5 +157,6 @@
 
 /**
- * Structure for keeping audio input sink specifics.
+ * Audio input sink specifics.
+ *
  * Do not use directly. Instead, use AUDMIXSINK.
  */
@@ -163,5 +168,6 @@
 
 /**
- * Structure for keeping audio output sink specifics.
+ * Audio output sink specifics.
+ *
  * Do not use directly. Instead, use AUDMIXSINK.
  */
@@ -171,5 +177,5 @@
 
 /**
- * Structure for maintaining an audio mixer sink.
+ * Audio mixer sink.
  */
 typedef struct AUDMIXSINK
@@ -220,5 +226,5 @@
     } Dbg;
 #endif
-} AUDMIXSINK, *PAUDMIXSINK;
+} AUDMIXSINK;
 
 /**
@@ -238,5 +244,5 @@
 
 /** No flags specified. */
-#define AUDMIXSTRMCTL_FLAG_NONE         0
+#define AUDMIXSTRMCTL_F_NONE            0
 
 int AudioMixerCreate(const char *pszName, uint32_t uFlags, PAUDIOMIXER *ppMixer);
Index: trunk/src/VBox/Devices/Audio/DevHDA.cpp
===================================================================
--- trunk/src/VBox/Devices/Audio/DevHDA.cpp	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/DevHDA.cpp	(revision 82406)
@@ -346,7 +346,7 @@
 
 /** No register description (RD) flags defined. */
-#define HDA_RD_FLAG_NONE           0
+#define HDA_RD_F_NONE           0
 /** Writes to SD are allowed while RUN bit is set. */
-#define HDA_RD_FLAG_SD_WRITE_RUN   RT_BIT(0)
+#define HDA_RD_F_SD_WRITE_RUN   RT_BIT(0)
 
 /** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
@@ -355,24 +355,24 @@
     /* -------       -------  ----------  ----------  ------------------------- --------------  -----------------  -----------------------------  ----------- */ \
     /* Offset 0x80 (SD0) */ \
-    { offset,        0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL  , HDA_REG_IDX_STRM(name, CTL)  , #name " Stream Descriptor Control" }, \
+    { offset,        0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_F_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL  , HDA_REG_IDX_STRM(name, CTL)  , #name " Stream Descriptor Control" }, \
     /* Offset 0x83 (SD0) */ \
-    { offset + 0x3,  0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8  , hdaRegWriteSDSTS  , HDA_REG_IDX_STRM(name, STS)  , #name " Status" }, \
+    { offset + 0x3,  0x00001, 0x0000003C, 0x0000001C, HDA_RD_F_SD_WRITE_RUN, hdaRegReadU8  , hdaRegWriteSDSTS  , HDA_REG_IDX_STRM(name, STS)  , #name " Status" }, \
     /* Offset 0x84 (SD0) */ \
-    { offset + 0x4,  0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE,         hdaRegReadLPIB, hdaRegWriteU32    , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
+    { offset + 0x4,  0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE,         hdaRegReadLPIB, hdaRegWriteU32    , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
     /* Offset 0x88 (SD0) */ \
-    { offset + 0x8,  0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDCBL  , HDA_REG_IDX_STRM(name, CBL)  , #name " Cyclic Buffer Length" }, \
+    { offset + 0x8,  0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE,         hdaRegReadU32 , hdaRegWriteSDCBL  , HDA_REG_IDX_STRM(name, CBL)  , #name " Cyclic Buffer Length" }, \
     /* Offset 0x8C (SD0) -- upper 8 bits are reserved */ \
-    { offset + 0xC,  0x00002, 0x0000FFFF, 0x000000FF, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDLVI  , HDA_REG_IDX_STRM(name, LVI)  , #name " Last Valid Index" }, \
+    { offset + 0xC,  0x00002, 0x0000FFFF, 0x000000FF, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDLVI  , HDA_REG_IDX_STRM(name, LVI)  , #name " Last Valid Index" }, \
     /* Reserved: FIFO Watermark. ** @todo Document this! */ \
-    { offset + 0xE,  0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
+    { offset + 0xE,  0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
     /* Offset 0x90 (SD0) */ \
-    { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
+    { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
     /* Offset 0x92 (SD0) */ \
-    { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE,         hdaRegReadU16 , hdaRegWriteSDFMT  , HDA_REG_IDX_STRM(name, FMT)  , #name " Stream Format" }, \
+    { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_F_NONE,         hdaRegReadU16 , hdaRegWriteSDFMT  , HDA_REG_IDX_STRM(name, FMT)  , #name " Stream Format" }, \
     /* Reserved: 0x94 - 0x98. */ \
     /* Offset 0x98 (SD0) */ \
-    { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
+    { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
     /* Offset 0x9C (SD0) */ \
-    { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
+    { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE,         hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
 
 /** Defines a single audio stream register set (e.g. OSD0). */
@@ -385,38 +385,38 @@
     /* offset  size     read mask   write mask  flags             read callback     write callback       index + abbrev              */
     /*-------  -------  ----------  ----------  ----------------- ----------------  -------------------     ------------------------ */
-    { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(GCAP)         }, /* Global Capabilities */
-    { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMIN)         }, /* Minor Version */
-    { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMAJ)         }, /* Major Version */
-    { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTPAY)       }, /* Output Payload Capabilities */
-    { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INPAY)        }, /* Input Payload Capabilities */
-    { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteGCTL    , HDA_REG_IDX(GCTL)         }, /* Global Control */
-    { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(WAKEEN)       }, /* Wake Enable */
-    { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS)     }, /* State Change Status */
-    { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl  , HDA_REG_IDX(GSTS)         }, /* Global Status */
-    { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTSTRMPAY)   }, /* Output Stream Payload Capability */
-    { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INSTRMPAY)    }, /* Input Stream Payload Capability */
-    { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
-    { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
-    { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
-    { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
-    { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
-    { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBUBASE)    }, /* CORB Upper Base Address */
-    { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteCORBWP  , HDA_REG_IDX(CORBWP)       }, /* CORB Write Pointer */
-    { 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteCORBRP  , HDA_REG_IDX(CORBRP)       }, /* CORB Read Pointer */
-    { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL)      }, /* CORB Control */
-    { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS)      }, /* CORB Status */
-    { 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE)     }, /* CORB Size */
-    { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBLBASE)    }, /* RIRB Lower Base Address */
-    { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBUBASE)    }, /* RIRB Upper Base Address */
-    { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteRIRBWP  , HDA_REG_IDX(RIRBWP)       }, /* RIRB Write Pointer */
-    { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16   , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT)      }, /* Response Interrupt Count */
-    { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteU8      , HDA_REG_IDX(RIRBCTL)      }, /* RIRB Control */
-    { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS)      }, /* RIRB Status */
-    { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(RIRBSIZE)     }, /* RIRB Size */
-    { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(IC)           }, /* Immediate Command */
-    { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(IR)           }, /* Immediate Response */
-    { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS   , hdaRegWriteIRS     , HDA_REG_IDX(IRS)          }, /* Immediate Command Status */
-    { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPLBASE)      }, /* DMA Position Lower Base */
-    { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPUBASE)      }, /* DMA Position Upper Base */
+    { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(GCAP)         }, /* Global Capabilities */
+    { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMIN)         }, /* Minor Version */
+    { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(VMAJ)         }, /* Major Version */
+    { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTPAY)       }, /* Output Payload Capabilities */
+    { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INPAY)        }, /* Input Payload Capabilities */
+    { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteGCTL    , HDA_REG_IDX(GCTL)         }, /* Global Control */
+    { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(WAKEEN)       }, /* Wake Enable */
+    { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS)     }, /* State Change Status */
+    { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl  , HDA_REG_IDX(GSTS)         }, /* Global Status */
+    { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteU16     , HDA_REG_IDX(OUTSTRMPAY)   }, /* Output Stream Payload Capability */
+    { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteUnimpl  , HDA_REG_IDX(INSTRMPAY)    }, /* Input Stream Payload Capability */
+    { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(INTCTL)       }, /* Interrupt Control */
+    { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(INTSTS)       }, /* Interrupt Status */
+    { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl  , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
+    { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(SSYNC)        }, /* Stream Synchronization */
+    { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBLBASE)    }, /* CORB Lower Base Address */
+    { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(CORBUBASE)    }, /* CORB Upper Base Address */
+    { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteCORBWP  , HDA_REG_IDX(CORBWP)       }, /* CORB Write Pointer */
+    { 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteCORBRP  , HDA_REG_IDX(CORBRP)       }, /* CORB Read Pointer */
+    { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL)      }, /* CORB Control */
+    { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS)      }, /* CORB Status */
+    { 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE)     }, /* CORB Size */
+    { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBLBASE)    }, /* RIRB Lower Base Address */
+    { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(RIRBUBASE)    }, /* RIRB Upper Base Address */
+    { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteRIRBWP  , HDA_REG_IDX(RIRBWP)       }, /* RIRB Write Pointer */
+    { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16   , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT)      }, /* Response Interrupt Count */
+    { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteU8      , HDA_REG_IDX(RIRBCTL)      }, /* RIRB Control */
+    { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS)      }, /* RIRB Status */
+    { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8    , hdaRegWriteUnimpl  , HDA_REG_IDX(RIRBSIZE)     }, /* RIRB Size */
+    { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteU32     , HDA_REG_IDX(IC)           }, /* Immediate Command */
+    { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteUnimpl  , HDA_REG_IDX(IR)           }, /* Immediate Response */
+    { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_F_NONE, hdaRegReadIRS   , hdaRegWriteIRS     , HDA_REG_IDX(IRS)          }, /* Immediate Command Status */
+    { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPLBASE)      }, /* DMA Position Lower Base */
+    { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32   , hdaRegWriteBase    , HDA_REG_IDX(DPUBASE)      }, /* DMA Position Upper Base */
     /* 4 Serial Data In (SDI). */
     HDA_REG_MAP_DEF_STREAM(0, SD0),
@@ -3176,5 +3176,5 @@
         if (   RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
             /* Are writes to the register denied if RUN bit is set? */
-            && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
+            && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_F_SD_WRITE_RUN))
         {
             Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
@@ -3394,5 +3394,5 @@
     {
         PHDABDLEDESC pDesc = (PHDABDLEDESC)pvStruct;
-        pDesc->fFlags = fIoc ? HDA_BDLE_FLAG_IOC : 0;
+        pDesc->fFlags = fIoc ? HDA_BDLE_F_IOC : 0;
     }
     return rc;
@@ -3416,5 +3416,5 @@
     {
         PHDABDLE pState = (PHDABDLE)pvStruct;
-        pState->Desc.fFlags = fIoc ? HDA_BDLE_FLAG_IOC : 0;
+        pState->Desc.fFlags = fIoc ? HDA_BDLE_F_IOC : 0;
     }
     return rc;
@@ -4040,5 +4040,5 @@
                        "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
                        pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
-                       pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAddr);
+                       pBDLE->Desc.fFlags & HDA_BDLE_F_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAddr);
 }
 
@@ -4196,5 +4196,5 @@
 
         pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
-                        pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
+                        pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_F_IOC);
 
         cbBDLE += bd.u32BufSize;
Index: trunk/src/VBox/Devices/Audio/DevHDA.h
===================================================================
--- trunk/src/VBox/Devices/Audio/DevHDA.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/DevHDA.h	(revision 82406)
@@ -54,5 +54,5 @@
 
 /**
- * Structure for mapping a stream tag to an HDA stream.
+ * Mapping a stream tag to an HDA stream.
  */
 typedef struct HDATAG
@@ -63,5 +63,7 @@
     /** Pointer to associated stream. */
     R3PTRTYPE(PHDASTREAM) pStream;
-} HDATAG, *PHDATAG;
+} HDATAG;
+/** Pointer to a HDA stream tag mapping. */
+typedef HDATAG *PHDATAG;
 
 /** @todo Make STAM values out of this? */
Index: trunk/src/VBox/Devices/Audio/DevHDACommon.cpp
===================================================================
--- trunk/src/VBox/Devices/Audio/DevHDACommon.cpp	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/DevHDACommon.cpp	(revision 82406)
@@ -567,5 +567,5 @@
 
         LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
-                 i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC));
+                 i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_F_IOC));
 
         cbBDLE += bd.u32BufSize;
@@ -657,5 +657,5 @@
 bool hdaR3BDLENeedsInterrupt(PHDABDLE pBDLE)
 {
-    return (pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC);
+    return (pBDLE->Desc.fFlags & HDA_BDLE_F_IOC);
 }
 
Index: trunk/src/VBox/Devices/Audio/DevHDACommon.h
===================================================================
--- trunk/src/VBox/Devices/Audio/DevHDACommon.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/DevHDACommon.h	(revision 82406)
@@ -45,7 +45,6 @@
     /** Writable bits. */
     uint32_t        writable;
-    /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
-     *  These are used to specify the handling (read/write)
-     *  policy of the register. */
+    /** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
+     *  specify the handling (read/write) policy of the register. */
     uint32_t        fFlags;
     /** Read callback. */
@@ -532,5 +531,5 @@
 
 /** Interrupt on completion (IOC) flag. */
-#define HDA_BDLE_FLAG_IOC           RT_BIT(0)
+#define HDA_BDLE_F_IOC              RT_BIT(0)
 
 
Index: trunk/src/VBox/Devices/Audio/HDACodec.h
===================================================================
--- trunk/src/VBox/Devices/Audio/HDACodec.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/HDACodec.h	(revision 82406)
@@ -62,5 +62,5 @@
 
 /**
- * Structure for keeping a HDA codec state.
+ * HDA codec state.
  */
 typedef struct HDACODEC
Index: trunk/src/VBox/Devices/Audio/HDAStream.h
===================================================================
--- trunk/src/VBox/Devices/Audio/HDAStream.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/HDAStream.h	(revision 82406)
@@ -249,5 +249,5 @@
 #ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
 /**
- * Structure for keeping a HDA stream thread context.
+ * HDA stream thread context (arguments).
  */
 typedef struct HDASTREAMTHREADCTX
Index: trunk/src/VBox/Devices/Audio/HDAStreamMap.h
===================================================================
--- trunk/src/VBox/Devices/Audio/HDAStreamMap.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/HDAStreamMap.h	(revision 82406)
@@ -23,27 +23,28 @@
 
 /**
- * Structure for keeping an audio stream data mapping.
+ * Audio stream data mapping.
  */
 typedef struct HDASTREAMMAP
 {
     /** The stream's layout. */
-    PDMAUDIOSTREAMLAYOUT               enmLayout;
-    uint8_t                            cbFrameSize;
+    PDMAUDIOSTREAMLAYOUT            enmLayout;
+    uint8_t                         cbFrameSize;
     /** Number of mappings in paMappings. */
-    uint8_t                            cMappings;
-    uint8_t                            aPadding[2];
+    uint8_t                         cMappings;
+    uint8_t                         aPadding[2];
     /** Array of stream mappings.
      *  Note: The mappings *must* be layed out in an increasing order, e.g.
      *        how the data appears in the given data block. */
-    R3PTRTYPE(PPDMAUDIOSTREAMMAP)      paMappings;
+    R3PTRTYPE(PPDMAUDIOSTREAMMAP)   paMappings;
 #if HC_ARCH_BITS == 32
-    RTR3PTR                            Padding1;
+    RTR3PTR                         Padding1;
 #endif
 #ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
     /** Circular buffer holding for holding audio data for this mapping. */
-    R3PTRTYPE(PRTCIRCBUF)              pCircBuf;
+    R3PTRTYPE(PRTCIRCBUF)           pCircBuf;
 #endif
 } HDASTREAMMAP;
 AssertCompileSizeAlignment(HDASTREAMMAP, 8);
+/** Pointer to an audio stream data mapping. */
 typedef HDASTREAMMAP *PHDASTREAMMAP;
 
@@ -55,5 +56,5 @@
 void hdaR3StreamMapDestroy(PHDASTREAMMAP pMapping);
 void hdaR3StreamMapReset(PHDASTREAMMAP pMapping);
-#endif /* IN_RING3 */
+#endif
 /** @} */
 
Index: trunk/src/VBox/Devices/Audio/HDAStreamPeriod.cpp
===================================================================
--- trunk/src/VBox/Devices/Audio/HDAStreamPeriod.cpp	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/HDAStreamPeriod.cpp	(revision 82406)
@@ -50,9 +50,9 @@
 int hdaR3StreamPeriodCreate(PHDASTREAMPERIOD pPeriod)
 {
-    Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_VALID));
+    Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_F_VALID));
 
     int rc = RTCritSectInit(&pPeriod->CritSect);
     AssertRCReturnStmt(rc, pPeriod->fStatus = 0, rc);
-    pPeriod->fStatus = HDASTREAMPERIOD_FLAG_VALID;
+    pPeriod->fStatus = HDASTREAMPERIOD_F_VALID;
 
     return VINF_SUCCESS;
@@ -66,9 +66,9 @@
 void hdaR3StreamPeriodDestroy(PHDASTREAMPERIOD pPeriod)
 {
-    if (pPeriod->fStatus & HDASTREAMPERIOD_FLAG_VALID)
+    if (pPeriod->fStatus & HDASTREAMPERIOD_F_VALID)
     {
         RTCritSectDelete(&pPeriod->CritSect);
 
-        pPeriod->fStatus = HDASTREAMPERIOD_FLAG_NONE;
+        pPeriod->fStatus = HDASTREAMPERIOD_F_NONE;
     }
 }
@@ -138,5 +138,5 @@
                  pPeriod->cIntPending, pPeriod->u8SD));
 
-    pPeriod->fStatus          &= ~HDASTREAMPERIOD_FLAG_ACTIVE;
+    pPeriod->fStatus          &= ~HDASTREAMPERIOD_F_ACTIVE;
     pPeriod->u64StartWalClk    = 0;
     pPeriod->u64ElapsedWalClk  = 0;
@@ -157,7 +157,7 @@
 int hdaR3StreamPeriodBegin(PHDASTREAMPERIOD pPeriod, uint64_t u64WalClk)
 {
-    Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE)); /* No nested calls. */
-
-    pPeriod->fStatus          |= HDASTREAMPERIOD_FLAG_ACTIVE;
+    Assert(!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE)); /* No nested calls. */
+
+    pPeriod->fStatus          |= HDASTREAMPERIOD_F_ACTIVE;
     pPeriod->u64StartWalClk    = u64WalClk;
     pPeriod->u64ElapsedWalClk  = 0;
@@ -181,5 +181,5 @@
     Log3Func(("[SD%RU8] Took %zuus\n", pPeriod->u8SD, (RTTimeNanoTS() - pPeriod->Dbg.tsStartNs) / 1000));
 
-    if (!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE))
+    if (!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE))
         return;
 
@@ -190,5 +190,5 @@
     Assert(hdaR3StreamPeriodIsComplete(pPeriod));
 
-    pPeriod->fStatus &= ~HDASTREAMPERIOD_FLAG_ACTIVE;
+    pPeriod->fStatus &= ~HDASTREAMPERIOD_F_ACTIVE;
 }
 
@@ -200,7 +200,7 @@
 void hdaR3StreamPeriodPause(PHDASTREAMPERIOD pPeriod)
 {
-    AssertMsg((pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE), ("Period %p already in inactive state\n", pPeriod));
-
-    pPeriod->fStatus &= ~HDASTREAMPERIOD_FLAG_ACTIVE;
+    AssertMsg((pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE), ("Period %p already in inactive state\n", pPeriod));
+
+    pPeriod->fStatus &= ~HDASTREAMPERIOD_F_ACTIVE;
 
     Log3Func(("[SD%RU8]\n", pPeriod->u8SD));
@@ -214,7 +214,7 @@
 void hdaR3StreamPeriodResume(PHDASTREAMPERIOD pPeriod)
 {
-    AssertMsg(!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE), ("Period %p already in active state\n", pPeriod));
-
-    pPeriod->fStatus |= HDASTREAMPERIOD_FLAG_ACTIVE;
+    AssertMsg(!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE), ("Period %p already in active state\n", pPeriod));
+
+    pPeriod->fStatus |= HDASTREAMPERIOD_F_ACTIVE;
 
     Log3Func(("[SD%RU8]\n", pPeriod->u8SD));
@@ -321,5 +321,5 @@
 {
     /* Period not in use? */
-    if (!(pPeriod->fStatus & HDASTREAMPERIOD_FLAG_ACTIVE))
+    if (!(pPeriod->fStatus & HDASTREAMPERIOD_F_ACTIVE))
         return true; /* ... implies that it has passed. */
 
Index: trunk/src/VBox/Devices/Audio/HDAStreamPeriod.h
===================================================================
--- trunk/src/VBox/Devices/Audio/HDAStreamPeriod.h	(revision 82405)
+++ trunk/src/VBox/Devices/Audio/HDAStreamPeriod.h	(revision 82406)
@@ -29,26 +29,27 @@
 
 struct HDASTREAM;
-typedef HDASTREAM *PHDASTREAM;
+typedef struct HDASTREAM *PHDASTREAM;
 
 #ifdef LOG_ENABLED
 /**
- * Structure for debug information of an HDA stream's period.
+ * Debug stuff for a HDA stream's period.
  */
-typedef struct HDASTREAMPERIODDBGINFO
+typedef struct HDASTREAMPERIODDDEBUG
 {
     /** Host start time (in ns) of the period. */
     uint64_t                tsStartNs;
-} HDASTREAMPERIODDBGINFO, *PHDASTREAMPERIODDBGINFO;
+} HDASTREAMPERIODDDEBUG;
 #endif
 
 /** No flags set. */
-#define HDASTREAMPERIOD_FLAG_NONE    0
+#define HDASTREAMPERIOD_F_NONE      0
 /** The stream period has been initialized and is in a valid state. */
-#define HDASTREAMPERIOD_FLAG_VALID   RT_BIT(0)
+#define HDASTREAMPERIOD_F_VALID     RT_BIT(0)
 /** The stream period is active. */
-#define HDASTREAMPERIOD_FLAG_ACTIVE  RT_BIT(1)
+#define HDASTREAMPERIOD_F_ACTIVE    RT_BIT(1)
 
 /**
- * Structure for keeping an HDA stream's (time) period.
+ * HDA stream's time period.
+ *
  * This is needed in order to keep track of stream timing and interrupt delivery.
  */
@@ -79,6 +80,6 @@
     uint32_t                framesTransferred;
 #ifdef LOG_ENABLED
-    /** Debugging information. */
-    HDASTREAMPERIODDBGINFO  Dbg;
+    /** Debugging state. */
+    HDASTREAMPERIODDDEBUG   Dbg;
 #endif
 } HDASTREAMPERIOD;
