Changeset 83057 in vbox

Timestamp:

Feb 12, 2020 5:07:09 AM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

136094

Message:

VMM/HM: VMX: Drop 32-bit guest switcher and use the 64-bit switcher for all guest code.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMR0A.asm (modified) (1 diff)
• HMVMXR0.cpp (modified) (3 diffs)
• HMVMXR0.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/HMR0A.asm

@@ -1236 +1236 @@
 
 
-;; @def RESTORE_STATE_VM32
-; Macro restoring essential host state and updating guest state
-; for common host, 32-bit guest for VT-x.
-%macro RESTORE_STATE_VM32 0
-    ; Restore base and limit of the IDTR & GDTR.
- %ifndef VMX_SKIP_IDTR
-    lidt    [xSP]
-    add     xSP, xCB * 2
- %endif
- %ifndef VMX_SKIP_GDTR
-    lgdt    [xSP]
-    add     xSP, xCB * 2
- %endif
-
-    push    xDI
- %ifndef VMX_SKIP_TR
-    mov     xDI, [xSP + xCB * 3]         ; pCtx (*3 to skip the saved xDI, TR, LDTR).
- %else
-    mov     xDI, [xSP + xCB * 2]         ; pCtx (*2 to skip the saved xDI, LDTR).
- %endif
-
-    mov     [ss:xDI + CPUMCTX.eax], eax
-    mov     xAX, SPECTRE_FILLER
-    mov     [ss:xDI + CPUMCTX.ebx], ebx
-    mov     xBX, xAX
-    mov     [ss:xDI + CPUMCTX.ecx], ecx
-    mov     xCX, xAX
-    mov     [ss:xDI + CPUMCTX.edx], edx
-    mov     xDX, xAX
-    mov     [ss:xDI + CPUMCTX.esi], esi
-    mov     xSI, xAX
-    mov     [ss:xDI + CPUMCTX.ebp], ebp
-    mov     xBP, xAX
-    mov     xAX, cr2
-    mov     [ss:xDI + CPUMCTX.cr2], xAX
-
- %ifdef RT_ARCH_AMD64
-    pop     xAX                                 ; The guest edi we pushed above.
-    mov     dword [ss:xDI + CPUMCTX.edi], eax
- %else
-    pop     dword [ss:xDI + CPUMCTX.edi]        ; The guest edi we pushed above.
- %endif
-
-    ; Fight spectre.
-    INDIRECT_BRANCH_PREDICTION_BARRIER ss:xDI, CPUMCTX_WSF_IBPB_EXIT
-
- %ifndef VMX_SKIP_TR
-    ; Restore TSS selector; must mark it as not busy before using ltr (!)
-    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
-    ; @todo get rid of sgdt
-    pop     xBX         ; Saved TR
-    sub     xSP, xCB * 2
-    sgdt    [xSP]
-    mov     xAX, xBX
-    and     eax, X86_SEL_MASK_OFF_RPL               ; Mask away TI and RPL bits leaving only the descriptor offset.
-    add     xAX, [xSP + 2]                          ; eax <- GDTR.address + descriptor offset.
-    and     dword [ss:xAX + 4], ~RT_BIT(9)          ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
-    ltr     bx
-    add     xSP, xCB * 2
- %endif
-
-    pop     xAX         ; Saved LDTR
- %ifdef RT_ARCH_AMD64
-    cmp     eax, 0
-    je      %%skip_ldt_write32
- %endif
-    lldt    ax
-
-%%skip_ldt_write32:
-    add     xSP, xCB     ; pCtx
-
-    ; Restore segment registers.
-    MYPOPSEGS xAX, ax
-
-    ; Restore the host XCR0 if necessary.
-    pop     xCX
-    test    ecx, ecx
-    jnz     %%xcr0_after_skip
-    pop     xAX
-    pop     xDX
-    xsetbv                              ; ecx is already zero.
-%%xcr0_after_skip:
-
-    ; Restore general purpose registers.
-    MYPOPAD
-%endmacro
-
-
-;;
-; Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
-;
-; @returns VBox status code
-; @param    fResume    x86:[ebp+8], msc:rcx,gcc:rdi     Whether to use vmlauch/vmresume.
-; @param    pCtx       x86:[ebp+c], msc:rdx,gcc:rsi     Pointer to the guest-CPU context.
-; @param    pvUnused   x86:[ebp+10],msc:r8, gcc:rdx     Unused argument.
-; @param    pVM        x86:[ebp+14],msc:r9, gcc:rcx     The cross context VM structure.
-; @param    pVCpu      x86:[ebp+18],msc:[ebp+30],gcc:r8 The cross context virtual CPU structure of the calling EMT.
-;
-ALIGNCODE(16)
-BEGINPROC VMXR0StartVM32
-    push    xBP
-    mov     xBP, xSP
-
-    pushf
-    cli
-
-    ;
-    ; Save all general purpose host registers.
-    ;
-    MYPUSHAD
-
-    ;
-    ; First we have to write some final guest CPU context registers.
-    ;
-    mov     eax, VMX_VMCS_HOST_RIP
-%ifdef RT_ARCH_AMD64
-    lea     r10, [.vmlaunch_done wrt rip]
-    vmwrite rax, r10
-%else
-    mov     ecx, .vmlaunch_done
-    vmwrite eax, ecx
-%endif
-    ; Note: assumes success!
-
-    ;
-    ; Unify input parameter registers.
-    ;
-%ifdef RT_ARCH_AMD64
- %ifdef ASM_CALL64_GCC
-    ; fResume already in rdi
-    ; pCtx    already in rsi
-    mov     rbx, rdx        ; pvUnused
- %else
-    mov     rdi, rcx        ; fResume
-    mov     rsi, rdx        ; pCtx
-    mov     rbx, r8         ; pvUnused
- %endif
-%else
-    mov     edi, [ebp + 8]  ; fResume
-    mov     esi, [ebp + 12] ; pCtx
-    mov     ebx, [ebp + 16] ; pvUnused
-%endif
-
-    ;
-    ; Save the host XCR0 and load the guest one if necessary.
-    ; Note! Trashes rdx and rcx.
-    ;
-%ifdef ASM_CALL64_MSC
-    mov     rax, [xBP + 30h]            ; pVCpu
-%elifdef ASM_CALL64_GCC
-    mov     rax, r8                     ; pVCpu
-%else
-    mov     eax, [xBP + 18h]            ; pVCpu
-%endif
-    test    byte [xAX + VMCPU.hm + HMCPU.fLoadSaveGuestXcr0], 1
-    jz      .xcr0_before_skip
-
-    xor     ecx, ecx
-    xgetbv                              ; Save the host one on the stack.
-    push    xDX
-    push    xAX
-
-    mov     eax, [xSI + CPUMCTX.aXcr]   ; Load the guest one.
-    mov     edx, [xSI + CPUMCTX.aXcr + 4]
-    xor     ecx, ecx                    ; paranoia
-    xsetbv
-
-    push    0                           ; Indicate that we must restore XCR0 (popped into ecx, thus 0).
-    jmp     .xcr0_before_done
-
-.xcr0_before_skip:
-    push    3fh                         ; indicate that we need not.
-.xcr0_before_done:
-
-    ;
-    ; Save segment registers.
-    ; Note! Trashes rdx & rcx, so we moved it here (amd64 case).
-    ;
-    MYPUSHSEGS xAX, ax
-
-    ; Save the pCtx pointer.
-    push    xSI
-
-    ; Save host LDTR.
-    xor     eax, eax
-    sldt    ax
-    push    xAX
-
-%ifndef VMX_SKIP_TR
-    ; The host TR limit is reset to 0x67; save & restore it manually.
-    str     eax
-    push    xAX
-%endif
-
-%ifndef VMX_SKIP_GDTR
-    ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
-    sub     xSP, xCB * 2
-    sgdt    [xSP]
-%endif
-%ifndef VMX_SKIP_IDTR
-    sub     xSP, xCB * 2
-    sidt    [xSP]
-%endif
-
-    ; Load CR2 if necessary (may be expensive as writing CR2 is a synchronizing instruction).
-    mov     xBX, [xSI + CPUMCTX.cr2]
-    mov     xDX, cr2
-    cmp     xBX, xDX
-    je      .skip_cr2_write32
-    mov     cr2, xBX
-
-.skip_cr2_write32:
-    mov     eax, VMX_VMCS_HOST_RSP
-    vmwrite xAX, xSP
-    ; Note: assumes success!
-    ; Don't mess with ESP anymore!!!
-
-    ; Fight spectre and similar.
-    INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY, CPUMCTX_WSF_MDS_ENTRY
-
-    ; Load guest general purpose registers.
-    mov     eax, [xSI + CPUMCTX.eax]
-    mov     ebx, [xSI + CPUMCTX.ebx]
-    mov     ecx, [xSI + CPUMCTX.ecx]
-    mov     edx, [xSI + CPUMCTX.edx]
-    mov     ebp, [xSI + CPUMCTX.ebp]
-
-    ; Resume or start VM?
-    cmp     xDI, 0                  ; fResume
-
-    ; Load guest edi & esi.
-    mov     edi, [xSI + CPUMCTX.edi]
-    mov     esi, [xSI + CPUMCTX.esi]
-
-    je      .vmlaunch_launch
-
-    vmresume
-    jc      near .vmxstart_invalid_vmcs_ptr
-    jz      near .vmxstart_start_failed
-    jmp     .vmlaunch_done;      ; Here if vmresume detected a failure.
-
-.vmlaunch_launch:
-    vmlaunch
-    jc      near .vmxstart_invalid_vmcs_ptr
-    jz      near .vmxstart_start_failed
-    jmp     .vmlaunch_done;      ; Here if vmlaunch detected a failure.
-
-ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
-.vmlaunch_done:
-    RESTORE_STATE_VM32
-    mov     eax, VINF_SUCCESS
-
-.vmstart_end:
-    popf
-    pop     xBP
-    ret
-
-.vmxstart_invalid_vmcs_ptr:
-    RESTORE_STATE_VM32
-    mov     eax, VERR_VMX_INVALID_VMCS_PTR_TO_START_VM
-    jmp     .vmstart_end
-
-.vmxstart_start_failed:
-    RESTORE_STATE_VM32
-    mov     eax, VERR_VMX_UNABLE_TO_START_VM
-    jmp     .vmstart_end
-
-ENDPROC VMXR0StartVM32
-
-
 %ifdef RT_ARCH_AMD64
 ;; @def RESTORE_STATE_VM64

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -4155 +4155 @@
         if (RT_SUCCESS(rc))
         {
+            /*
+             * Initialize the hardware-assisted VMX execution handler for guest and nested-guest VMCS.
+             * The host is always 64-bit since we no longer support 32-bit hosts.
+             * Currently we have just a single handler for all guest modes as well, see @bugref{6208#c73}.
+             */
+            pVmcsInfo->pfnStartVM = VMXR0StartVM64;
             if (!fIsNstGstVmcs)
             {
@@ -4852 +4858 @@
         PVMCC pVM = pVCpu->CTX_SUFF(pVM);
         PVMXVMCSINFO pVmcsInfo      = pVmxTransient->pVmcsInfo;
-        bool const   fGstInLongMode = CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx);
-
-        /*
-         * VMRUN function.
-         * If the guest supports long mode, always use the 64-bit guest handler, see @bugref{6208#c73}.
-         * The host is always 64-bit since we no longer support 32-bit hosts.
-         */
-        if (pVM->hm.s.fAllow64BitGuests)
-            pVmcsInfo->pfnStartVM = VMXR0StartVM64;
-        else
-            pVmcsInfo->pfnStartVM = VMXR0StartVM32;
 
         /*
@@ -4889 +4884 @@
              * here rather than while merging the guest VMCS controls.
              */
-            if (fGstInLongMode)
+            if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
             {
                 Assert(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME);

trunk/src/VBox/VMM/VMMR0/HMVMXR0.h

@@ -46 +46 @@
 VMMR0DECL(int)          VMXR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat);
 VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPUCC pVCpu);
-DECLASM(int)            VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, void *pvUnused, PVMCC pVM, PVMCPUCC pVCpu);
 DECLASM(int)            VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, void *pvUnused, PVMCC pVM, PVMCPUCC pVCpu);
 #endif /* IN_RING0 */