Changeset 83067 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Feb 13, 2020 4:39:07 AM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

136107

Message:

VMM/HM: Cleanup nits.

File:

• trunk/src/VBox/VMM/VMMR0/HMR0A.asm (modified) (44 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0A.asm

@@ -1 +1 @@
 ; $Id$
 ;; @file
-; HM - Ring-0 VMX, SVM world-switch and helper routines
+; HM - Ring-0 VMX, SVM world-switch and helper routines.
 ;
 
@@ -65 +65 @@
 
 ;;
-; Determine skipping restoring of GDTR, IDTR, TR across VMX non-root operation
+; Determine skipping restoring of GDTR, IDTR, TR across VMX non-root operation.
 ;
 %ifdef RT_ARCH_AMD64
@@ -83 +83 @@
 
 ;; @def MYPUSHAD
-; Macro generating an equivalent to pushad
+; Macro generating an equivalent to PUSHAD instruction.
 
 ;; @def MYPOPAD
-; Macro generating an equivalent to popad
+; Macro generating an equivalent to POPAD instruction.
 
 ;; @def MYPUSHSEGS
 ; Macro saving all segment registers on the stack.
-; @param 1  full width register name
+; @param 1  Full width register name.
 ; @param 2  16-bit register name for \a 1.
 
 ;; @def MYPOPSEGS
-; Macro restoring all segment registers on the stack
-; @param 1  full width register name
+; Macro restoring all segment registers on the stack.
+; @param 1  Full width register name.
 ; @param 2  16-bit register name for \a 1.
 
@@ -142 +142 @@
  %endmacro
 %else       ; !VBOX_SKIP_RESTORE_SEG
- ; trashes, rax, rdx & rcx
+ ; Trashes, rax, rdx & rcx.
  %macro MYPUSHSEGS64 2
   %ifndef HM_64_BIT_USE_NULL_SEL
@@ -151 +151 @@
   %endif
 
-   ; Special case for FS; Windows and Linux either don't use it or restore it when leaving kernel mode, Solaris OTOH doesn't and we must save it.
+   ; Special case for FS; Windows and Linux either don't use it or restore it when leaving kernel mode,
+   ; Solaris OTOH doesn't and we must save it.
    mov     ecx, MSR_K8_FS_BASE
    rdmsr
@@ -160 +161 @@
   %endif
 
-   ; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel. The same happens on exit
+   ; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel.
+   ; The same happens on exit.
    mov     ecx, MSR_K8_GS_BASE
    rdmsr
@@ -283 +285 @@
     mov     ecx, MSR_IA32_FLUSH_CMD
     wrmsr
-    jmp     %%no_mds_buffer_flushing    ; MDS flushing is included in L1D_FLUSH.
+    jmp     %%no_mds_buffer_flushing    ; MDS flushing is included in L1D_FLUSH
 %%no_cache_flush_barrier:
 
@@ -310 +312 @@
 
 
-;/**
-; * Restores host-state fields.
-; *
-; * @returns VBox status code
-; * @param   f32RestoreHost x86: [ebp + 08h]  msc: ecx  gcc: edi   RestoreHost flags.
-; * @param   pRestoreHost   x86: [ebp + 0ch]  msc: rdx  gcc: rsi   Pointer to the RestoreHost struct.
-; */
+;;
+; Restores host-state fields.
+;
+; @returns VBox status code
+; @param   f32RestoreHost x86: [ebp + 08h]  msc: ecx  gcc: edi   RestoreHost flags.
+; @param   pRestoreHost   x86: [ebp + 0ch]  msc: rdx  gcc: rsi   Pointer to the RestoreHost struct.
+;
 ALIGNCODE(16)
 BEGINPROC VMXRestoreHostState
@@ -357 +359 @@
     mov         dx, [rsi + VMXRESTOREHOST.uHostSelTR]
     mov         ax, dx
-    and         eax, X86_SEL_MASK_OFF_RPL                       ; Mask away TI and RPL bits leaving only the descriptor offset.
+    and         eax, X86_SEL_MASK_OFF_RPL                       ; mask away TI and RPL bits leaving only the descriptor offset
     test        edi, VMX_RESTORE_HOST_GDT_READ_ONLY | VMX_RESTORE_HOST_GDT_NEED_WRITABLE
     jnz         .gdt_readonly
     add         rax, qword [rsi + VMXRESTOREHOST.HostGdtr + 2]  ; xAX <- descriptor offset + GDTR.pGdt.
-    and         dword [rax + 4], ~RT_BIT(9)                     ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
+    and         dword [rax + 4], ~RT_BIT(9)                     ; clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit)
     ltr         dx
     jmp short   .test_fs
@@ -372 +374 @@
     and         rcx, ~X86_CR0_WP
     mov         cr0, rcx
-    and         dword [rax + 4], ~RT_BIT(9)                     ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
+    and         dword [rax + 4], ~RT_BIT(9)                     ; clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit)
     ltr         dx
     mov         cr0, r9
     jmp short   .test_fs
 .gdt_readonly_need_writable:
-    add         rax, qword [rsi + VMXRESTOREHOST.HostGdtrRw + 2]  ; xAX <- descriptor offset + GDTR.pGdtRw.
-    and         dword [rax + 4], ~RT_BIT(9)                     ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
+    add         rax, qword [rsi + VMXRESTOREHOST.HostGdtrRw + 2]  ; xAX <- descriptor offset + GDTR.pGdtRw
+    and         dword [rax + 4], ~RT_BIT(9)                     ; clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit)
     lgdt        [rsi + VMXRESTOREHOST.HostGdtrRw]
     ltr         dx
-    lgdt        [rsi + VMXRESTOREHOST.HostGdtr]                 ; Load the original GDT
+    lgdt        [rsi + VMXRESTOREHOST.HostGdtr]                 ; load the original GDT
 
 .test_fs:
@@ -434 +436 @@
 
 
-;/**
-; * Dispatches an NMI to the host.
-; */
+;;
+; Dispatches an NMI to the host.
+;
 ALIGNCODE(16)
 BEGINPROC VMXDispatchHostNmi
-    int 2   ; NMI is always vector 2. The IDT[2] IRQ handler cannot be anything else. See Intel spec. 6.3.1 "External Interrupts".
+    ; NMI is always vector 2. The IDT[2] IRQ handler cannot be anything else. See Intel spec. 6.3.1 "External Interrupts".
+    int 2
     ret
 ENDPROC VMXDispatchHostNmi
 
 
-;/**
-; * Executes VMWRITE, 64-bit value.
-; *
-; * @returns VBox status code.
-; * @param   idxField   x86: [ebp + 08h]  msc: rcx  gcc: rdi   VMCS index.
-; * @param   u64Data    x86: [ebp + 0ch]  msc: rdx  gcc: rsi   VM field value.
-; */
+;;
+; Executes VMWRITE, 64-bit value.
+;
+; @returns VBox status code.
+; @param   idxField   x86: [ebp + 08h]  msc: rcx  gcc: rdi   VMCS index.
+; @param   u64Data    x86: [ebp + 0ch]  msc: rdx  gcc: rsi   VM field value.
+;
 ALIGNCODE(16)
 BEGINPROC VMXWriteVmcs64
@@ -485 +488 @@
 
 
-;/**
-; * Executes VMREAD, 64-bit value.
-; *
-; * @returns VBox status code.
-; * @param   idxField        VMCS index.
-; * @param   pData           Where to store VM field value.
-; */
+;;
+; Executes VMREAD, 64-bit value.
+;
+; @returns VBox status code.
+; @param   idxField        VMCS index.
+; @param   pData           Where to store VM field value.
+;
 ;DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
 ALIGNCODE(16)
@@ -527 +530 @@
 
 
-;/**
-; * Executes VMREAD, 32-bit value.
-; *
-; * @returns VBox status code.
-; * @param   idxField        VMCS index.
-; * @param   pu32Data        Where to store VM field value.
-; */
+;;
+; Executes VMREAD, 32-bit value.
+;
+; @returns VBox status code.
+; @param   idxField        VMCS index.
+; @param   pu32Data        Where to store VM field value.
+;
 ;DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pu32Data);
 ALIGNCODE(16)
@@ -566 +569 @@
 
 
-;/**
-; * Executes VMWRITE, 32-bit value.
-; *
-; * @returns VBox status code.
-; * @param   idxField        VMCS index.
-; * @param   u32Data         Where to store VM field value.
-; */
+;;
+; Executes VMWRITE, 32-bit value.
+;
+; @returns VBox status code.
+; @param   idxField        VMCS index.
+; @param   u32Data         Where to store VM field value.
+;
 ;DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Data);
 ALIGNCODE(16)
@@ -605 +608 @@
 
 
-;/**
-; * Executes VMXON.
-; *
-; * @returns VBox status code.
-; * @param   HCPhysVMXOn      Physical address of VMXON structure.
-; */
+;;
+; Executes VMXON.
+;
+; @returns VBox status code.
+; @param   HCPhysVMXOn      Physical address of VMXON structure.
+;
 ;DECLASM(int) VMXEnable(RTHCPHYS HCPhysVMXOn);
 BEGINPROC VMXEnable
@@ -641 +644 @@
 
 
-;/**
-; * Executes VMXOFF.
-; */
+;;
+; Executes VMXOFF.
+;
 ;DECLASM(void) VMXDisable(void);
 BEGINPROC VMXDisable
@@ -652 +655 @@
 
 
-;/**
-; * Executes VMCLEAR.
-; *
-; * @returns VBox status code.
-; * @param   HCPhysVmcs     Physical address of VM control structure.
-; */
+;;
+; Executes VMCLEAR.
+;
+; @returns VBox status code.
+; @param   HCPhysVmcs     Physical address of VM control structure.
+;
 ;DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
 ALIGNCODE(16)
@@ -683 +686 @@
 
 
-;/**
-; * Executes VMPTRLD.
-; *
-; * @returns VBox status code.
-; * @param   HCPhysVmcs     Physical address of VMCS structure.
-; */
+;;
+; Executes VMPTRLD.
+;
+; @returns VBox status code.
+; @param   HCPhysVmcs     Physical address of VMCS structure.
+;
 ;DECLASM(int) VMXLoadVmcs(RTHCPHYS HCPhysVmcs);
 ALIGNCODE(16)
@@ -714 +717 @@
 
 
-;/**
-; * Executes VMPTRST.
-; *
-; * @returns VBox status code.
-; * @param    [esp + 04h]  gcc:rdi  msc:rcx   Param 1 - First parameter - Address that will receive the current pointer.
-; */
+;;
+; Executes VMPTRST.
+;
+; @returns VBox status code.
+; @param    [esp + 04h]  gcc:rdi  msc:rcx   Param 1 - First parameter - Address that will receive the current pointer.
+;
 ;DECLASM(int) VMXGetCurrentVmcs(RTHCPHYS *pVMCS);
 BEGINPROC VMXGetCurrentVmcs
@@ -741 +744 @@
 ENDPROC VMXGetCurrentVmcs
 
-;/**
-; * Invalidate a page using INVEPT.
+;;
+; Invalidate a page using INVEPT.
+;
 ; @param   enmTlbFlush  msc:ecx  gcc:edi  x86:[esp+04]  Type of flush.
 ; @param   pDescriptor  msc:edx  gcc:esi  x86:[esp+08]  Descriptor pointer.
-; */
+;
 ;DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmTlbFlush, uint64_t *pDescriptor);
 BEGINPROC VMXR0InvEPT
@@ -778 +782 @@
 
 
-;/**
-; * Invalidate a page using invvpid
+;;
+; Invalidate a page using INVVPID.
+;
 ; @param   enmTlbFlush  msc:ecx  gcc:edi  x86:[esp+04]  Type of flush
 ; @param   pDescriptor  msc:edx  gcc:esi  x86:[esp+08]  Descriptor pointer
-; */
+;
 ;DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmTlbFlush, uint64_t *pDescriptor);
 BEGINPROC VMXR0InvVPID
@@ -817 +822 @@
 %if GC_ARCH_BITS == 64
 ;;
-; Executes INVLPGA
+; Executes INVLPGA.
 ;
 ; @param   pPageGC  msc:rcx  gcc:rdi  x86:[esp+04]  Virtual page to invalidate
@@ -855 +860 @@
  %else
     ; from http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
-    ; ``Perhaps unexpectedly, instructions that move or generate 32-bit register
-    ;   values also set the upper 32 bits of the register to zero. Consequently
-    ;   there is no need for an instruction movzlq.''
+    ; "Perhaps unexpectedly, instructions that move or generate 32-bit register
+    ;  values also set the upper 32 bits of the register to zero. Consequently
+    ;  there is no need for an instruction movzlq."
     mov     eax, ecx
     mov     ecx, edx
@@ -906 +911 @@
         sub     xSP, 0b0h + 040h ; Don't bother optimizing the frame size.
 
-        ; spill input parameters.
+        ; Spill input parameters.
         mov     [xBP + 010h], rcx       ; fResumeVM
         mov     [xBP + 018h], rdx       ; pCtx
@@ -959 +964 @@
         xrstor  [r10]
 
-        ; Make the call (same as in the other case ).
+        ; Make the call (same as in the other case).
         mov     r11, [xBP + 38h]        ; pfnStartVM
         mov     r10, [xBP + 30h]        ; pVCpu
@@ -979 +984 @@
         xsave  [r10]
 
-        mov     eax, r11d               ; restore return value.
+        mov     eax, r11d               ; restore return value
 
 .restore_non_volatile_host_xmm_regs:
@@ -1021 +1026 @@
         ldmxcsr        [r10 + X86FXSTATE.MXCSR]
 
-        ; Make the call (same as in the other case ).
+        ; Make the call (same as in the other case).
         mov     r11, [xBP + 38h]        ; pfnStartVM
         mov     r10, [xBP + 30h]        ; pVCpu
@@ -1083 +1088 @@
         push    xBP
         mov     xBP, xSP
-        sub     xSP, 0b0h + 040h        ; Don't bother optimizing the frame size.
-
-        ; spill input parameters.
+        sub     xSP, 0b0h + 040h        ; don't bother optimizing the frame size
+
+        ; Spill input parameters.
         mov     [xBP + 010h], rcx       ; HCPhysVmcbHost
         mov     [xBP + 018h], rdx       ; HCPhysVmcb
@@ -1138 +1143 @@
         xrstor  [r10]
 
-        ; Make the call (same as in the other case ).
+        ; Make the call (same as in the other case).
         mov     r11, [xBP + 38h]        ; pfnVMRun
         mov     r10, [xBP + 30h]        ; pVCpu
@@ -1158 +1163 @@
         xsave  [r10]
 
-        mov     eax, r11d               ; restore return value.
+        mov     eax, r11d               ; restore return value
 
 .restore_non_volatile_host_xmm_regs:
@@ -1200 +1205 @@
         ldmxcsr        [r10 + X86FXSTATE.MXCSR]
 
-        ; Make the call (same as in the other case ).
+        ; Make the call (same as in the other case).
         mov     r11, [xBP + 38h]        ; pfnVMRun
         mov     r10, [xBP + 30h]        ; pVCpu
@@ -1242 +1247 @@
 ;
 %macro RESTORE_STATE_VM64 0
-    ; Restore base and limit of the IDTR & GDTR
+    ; Restore base and limit of the IDTR & GDTR.
  %ifndef VMX_SKIP_IDTR
     lidt    [xSP]
@@ -1297 +1302 @@
 
  %ifndef VMX_SKIP_TR
-    ; Restore TSS selector; must mark it as not busy before using ltr (!)
-    ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p).
+    ; Restore TSS selector; must mark it as not busy before using ltr!
+    ; ASSUME that this is supposed to be 'BUSY' (saves 20-30 ticks on the T42p).
     ; @todo get rid of sgdt
     pop     xBX         ; Saved TR
@@ -1304 +1309 @@
     sgdt    [xSP]
     mov     xAX, xBX
-    and     eax, X86_SEL_MASK_OFF_RPL           ; Mask away TI and RPL bits leaving only the descriptor offset.
-    add     xAX, [xSP + 2]                      ; eax <- GDTR.address + descriptor offset.
-    and     dword [xAX + 4], ~RT_BIT(9)         ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
+    and     eax, X86_SEL_MASK_OFF_RPL           ; mask away TI and RPL bits leaving only the descriptor offset
+    add     xAX, [xSP + 2]                      ; eax <- GDTR.address + descriptor offset
+    and     dword [xAX + 4], ~RT_BIT(9)         ; clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit)
     ltr     bx
     add     xSP, xCB * 2
@@ -1340 +1345 @@
 ;
 ; @returns VBox status code
-; @param    fResume    msc:rcx, gcc:rdi     Whether to use vmlauch/vmresume.
-; @param    pCtx       msc:rdx, gcc:rsi     Pointer to the guest-CPU context.
-; @param    pvUnused   msc:r8,  gcc:rdx     Unused argument.
-; @param    pVM        msc:r9,  gcc:rcx     The cross context VM structure.
-; @param    pVCpu      msc:[ebp+30], gcc:r8 The cross context virtual CPU structure of the calling EMT.
+; @param    fResume    msc:rcx, gcc:rdi       Whether to use vmlauch/vmresume.
+; @param    pCtx       msc:rdx, gcc:rsi       Pointer to the guest-CPU context.
+; @param    pvUnused   msc:r8,  gcc:rdx       Unused argument.
+; @param    pVM        msc:r9,  gcc:rcx       The cross context VM structure.
+; @param    pVCpu      msc:[ebp+30], gcc:r8   The cross context virtual CPU structure of the calling EMT.
 ;
 ALIGNCODE(16)
@@ -1359 +1364 @@
     ; First we have to save some final CPU context registers.
     lea     r10, [.vmlaunch64_done wrt rip]
-    mov     rax, VMX_VMCS_HOST_RIP      ; Return address (too difficult to continue after VMLAUNCH?).
+    mov     rax, VMX_VMCS_HOST_RIP      ; return address (too difficult to continue after VMLAUNCH?)
     vmwrite rax, r10
-    ; Note: assumes success!
+    ; Note: ASSUMES success!
 
     ;
@@ -1389 +1394 @@
 
     xor     ecx, ecx
-    xgetbv                              ; Save the host one on the stack.
+    xgetbv                              ; save the host one on the stack
     push    xDX
     push    xAX
 
-    mov     eax, [xSI + CPUMCTX.aXcr]   ; Load the guest one.
+    mov     eax, [xSI + CPUMCTX.aXcr]   ; load the guest one
     mov     edx, [xSI + CPUMCTX.aXcr + 4]
     xor     ecx, ecx                    ; paranoia
     xsetbv
 
-    push    0                           ; Indicate that we must restore XCR0 (popped into ecx, thus 0).
+    push    0                           ; indicate that we must restore XCR0 (popped into ecx, thus 0)
     jmp     .xcr0_before_done
 
 .xcr0_before_skip:
-    push    3fh                         ; indicate that we need not.
+    push    3fh                         ; indicate that we need not
 .xcr0_before_done:
 
@@ -1445 +1450 @@
     mov     eax, VMX_VMCS_HOST_RSP
     vmwrite xAX, xSP
-    ; Note: assumes success!
+    ; Note: ASSUMES success!
     ; Don't mess with ESP anymore!!!
 
@@ -1478 +1483 @@
     jc      near .vmxstart64_invalid_vmcs_ptr
     jz      near .vmxstart64_start_failed
-    jmp     .vmlaunch64_done;      ; Here if vmresume detected a failure.
+    jmp     .vmlaunch64_done;      ; here if vmresume detected a failure
 
 .vmlaunch64_launch:
@@ -1484 +1489 @@
     jc      near .vmxstart64_invalid_vmcs_ptr
     jz      near .vmxstart64_start_failed
-    jmp     .vmlaunch64_done;      ; Here if vmlaunch detected a failure.
+    jmp     .vmlaunch64_done;      ; here if vmlaunch detected a failure
 
 ALIGNCODE(16)
@@ -1536 +1541 @@
     ; Fake a cdecl stack frame
  %ifdef ASM_CALL64_GCC
-    push    r8                ;pVCpu
-    push    rcx               ;pVM
-    push    rdx               ;pCtx
-    push    rsi               ;HCPhysVmcb
-    push    rdi               ;HCPhysVmcbHost
+    push    r8                ; pVCpu
+    push    rcx               ; pVM
+    push    rdx               ; pCtx
+    push    rsi               ; HCPhysVmcb
+    push    rdi               ; HCPhysVmcbHost
  %else
     mov     rax, [rsp + 28h]
@@ -1575 +1580 @@
 
     xor     ecx, ecx
-    xgetbv                                  ; save the host XCR0 on the stack.
+    xgetbv                                  ; save the host XCR0 on the stack
     push    xDX
     push    xAX
@@ -1596 +1601 @@
 
     ; Save host fs, gs, sysenter msr etc.
-    mov     rax, [rbp + xCB * 2]                    ; HCPhysVmcbHost (64 bits physical address; x86: take low dword only)
-    push    rax                                     ; save for the vmload after vmrun
+    mov     rax, [rbp + xCB * 2]            ; HCPhysVmcbHost (64 bits physical address; x86: take low dword only)
+    push    rax                             ; save for the vmload after vmrun
     vmsave
 
@@ -1604 +1609 @@
 
     ; Setup rax for VMLOAD.
-    mov     rax, [rbp + xCB * 2 + RTHCPHYS_CB]      ; HCPhysVmcb (64 bits physical address; take low dword only)
+    mov     rax, [rbp + xCB * 2 + RTHCPHYS_CB] ; HCPhysVmcb (64 bits physical address; take low dword only)
 
     ; Load guest general purpose registers (rax is loaded from the VMCB by VMRUN).