Changeset 83519 in vbox
- Timestamp:
- Apr 3, 2020 7:39:23 AM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 136831
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r83498 r83519 22 22 #define LOG_GROUP LOG_GROUP_DEV_IOMMU 23 23 #include <VBox/vmm/pdmdev.h> 24 #include <VBox/AssertGuest.h> 24 25 25 26 #include "VBoxDD.h" … … 29 30 * Defined Constants And Macros * 30 31 *********************************************************************************************************************************/ 32 /** @name PCI configuration register offsets. 33 @{ */ 34 #define IOMMU_PCI_OFF_CAP_HDR 0x00 35 #define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x04 36 #define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x08 37 #define IOMMU_PCI_OFF_RANGE_REG 0x0c 38 #define IOMMU_PCI_OFF_MISCINFO_REG_0 0x10 39 #define IOMMU_PCI_OFF_MISCINFO_REG_1 0x14 40 /** @} */ 41 42 /** @name MMIO register offsets. 43 * @{ */ 44 #define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00 45 #define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08 46 #define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10 47 #define IOMMU_MMIO_OFF_CTRL 0x18 48 #define IOMMU_MMIO_OFF_EXCL_BAR 0x20 49 #define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28 50 #define IOMMU_MMIO_OFF_EXT_FEAT 0x30 51 52 #define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38 53 #define IOMMU_MMIO_OFF_HW_EVT_HI 0x40 54 #define IOMMU_MMIO_OFF_HW_EVT_LO 0x48 55 #define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50 56 57 #define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60 58 #define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8 59 60 #define IOMMU_MMIO_OFF_GALOG_BAR 0xe0 61 #define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8 62 63 #define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0 64 #define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8 65 66 #define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100 67 #define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130 68 69 #define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138 70 #define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140 71 #define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148 72 73 #define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150 74 #define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154 75 #define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158 76 #define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c 77 #define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160 78 #define IOMMU_MMIO_OFF_MSI_DATA 0x164 79 #define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168 80 81 #define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c 82 83 #define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170 84 #define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178 85 #define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180 86 87 #define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200 88 #define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208 89 #define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210 90 #define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218 91 #define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220 92 #define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228 93 #define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230 94 #define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238 95 #define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240 96 #define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248 97 #define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250 98 #define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258 99 100 #define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8 101 102 #define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000 103 #define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008 104 #define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010 105 #define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018 106 107 #define IOMMU_MMIO_OFF_STATUS 0x2020 108 109 #define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030 110 #define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038 111 112 #define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040 113 #define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048 114 115 #define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050 116 #define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058 117 118 #define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070 119 #define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078 120 121 #define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080 122 #define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088 123 #define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090 124 /** @} */ 125 31 126 /** 32 127 * @name Commands. … … 1423 1518 1424 1519 /** 1520 * Memory Access and Routing Control (MARC) Aperture Base Register (MMIO). 1521 * In accordance with the AMD spec. 1522 */ 1523 typedef union 1524 { 1525 struct 1526 { 1527 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 11:0 - Reserved. */ 1528 RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /**< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. */ 1529 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved. */ 1530 } n; 1531 /** The 64-bit unsigned integer view. */ 1532 uint64_t u64; 1533 } MARC_APER_BAR_T; 1534 AssertCompileSize(MARC_APER_BAR_T, 8); 1535 1536 /** 1537 * Memory Access and Routing Control (MARC) Relocation Register (MMIO). 1538 * In accordance with the AMD spec. 1539 */ 1540 typedef union 1541 { 1542 struct 1543 { 1544 RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /**< Bit 0 - RelocEn: Relocation Enabled. */ 1545 RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /**< Bit 1 - ReadOnly: Whether only read-only acceses allowed. */ 1546 RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /**< Bits 11:2 - Reserved. */ 1547 RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /**< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. */ 1548 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved. */ 1549 } n; 1550 /** The 64-bit unsigned integer view. */ 1551 uint64_t u64; 1552 } MARC_APER_RELOC_T; 1553 AssertCompileSize(MARC_APER_RELOC_T, 8); 1554 1555 /** 1556 * Memory Access and Routing Control (MARC) Length Register (MMIO). 1557 * In accordance with the AMD spec. 1558 */ 1559 typedef union 1560 { 1561 struct 1562 { 1563 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 11:0 - Reserved. */ 1564 RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /**< Bits 51:12 - MarcLength: MARC Aperture Length. */ 1565 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved. */ 1566 } n; 1567 /** The 64-bit unsigned integer view. */ 1568 uint64_t u64; 1569 } MARC_APER_LEN_T; 1570 1571 /** 1572 * Memory Access and Routing Control (MARC) Aperture Register. 1573 * This combines other registers to match the MMIO layout for convenient access. 1574 */ 1575 typedef struct 1576 { 1577 MARC_APER_BAR_T Base; 1578 MARC_APER_RELOC_T Reloc; 1579 MARC_APER_LEN_T Length; 1580 } MARC_APER_T; 1581 AssertCompileSize(MARC_APER_T, 24); 1582 1583 /** 1425 1584 * IOMMU Reserved Register (MMIO). 1426 1585 * In accordance with the AMD spec. … … 1641 1800 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */ 1642 1801 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */ 1643 IOMMU_CTRL_T IommuCtrl;/**< IOMMU control register. */1802 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */ 1644 1803 IOMMU_EXCL_BASE_T ExclBase; /**< IOMMU exclusion base register. */ 1645 1804 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */ … … 1650 1809 * @{ */ 1651 1810 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */ 1652 IOMMU_HW_EVT_HI_T IommuHwEvtHi;/**< IOMMU hardware event register (Hi). */1653 IOMMU_HW_EVT_LO_T IommuHwEvtLo;/**< IOMMU hardware event register (Lo). */1654 IOMMU_HW_EVT_STATUS_T IommuHwEvtStatus;/**< IOMMU hardware event status. */1811 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */ 1812 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */ 1813 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */ 1655 1814 /** @} */ 1656 1815 … … 1692 1851 /** @name MMIO: Performance Optimization Control registers. 1693 1852 * @{ */ 1694 IOMMU_PERF_OPT_CTRL_T IommuPerfOptCtrl;/**< IOMMU Performance optimization control register. */1853 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */ 1695 1854 /** @} */ 1696 1855 1697 1856 /** @name MMIO: x2APIC Control registers. 1698 1857 * @{ */ 1699 IOMMU_XT_GEN_INTR_CTRL_T IommuXtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */1700 IOMMU_XT_PPR_INTR_CTRL_T IommuXtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */1701 IOMMU_XT_GALOG_INTR_CTRL_T IommuXtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */1858 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */ 1859 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */ 1860 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */ 1702 1861 /** @} */ 1703 1862 1704 /** @todo MARC registers. */ 1863 /** @name MMIO: MARC registers. 1864 * @{ */ 1865 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */ 1866 /** @} */ 1705 1867 1706 1868 /** @name MMIO: Reserved register. 1707 1869 * @{ */ 1708 IOMMU_RSVD_REG_T IommuRsvdReg;/**< IOMMU Reserved Register. */1870 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */ 1709 1871 /** @} */ 1710 1872 … … 1719 1881 /** @name MMIO: Command and Event Status register. 1720 1882 * @{ */ 1721 IOMMU_STATUS_T IommuStatus;/**< IOMMU status register. */1883 IOMMU_STATUS_T Status; /**< IOMMU status register. */ 1722 1884 /** @} */ 1723 1885 … … 1754 1916 1755 1917 /** @todo IOMMU: IOMMU Event counter registers. */ 1918 1919 /** @todo IOMMU: Stat counters. */ 1756 1920 } IOMMU; 1757 1921 /** Pointer to the IOMMU device state. */ 1758 1922 typedef struct IOMMU *PIOMMU; 1923 /** Pointer to the const IOMMU device state. */ 1924 typedef const struct IOMMU *PCIOMMU; 1759 1925 1760 1926 /** … … 1799 1965 #ifndef VBOX_DEVICE_STRUCT_TESTCASE 1800 1966 1967 static VBOXSTRICTRC iommuAmdReadRegister(PCIOMMU pThis, uint32_t off, uint8_t cb, uint64_t *puResult) 1968 { 1969 Assert(off < _16K); 1970 Assert(cb == 4 || cb == 8); 1971 Assert(cb == 4 || !(off & 7)); 1972 Assert(cb == 8 || !(off & 3)); 1973 1974 switch (off) 1975 { 1976 case IOMMU_MMIO_OFF_DEV_TAB_BAR: *puResult = pThis->DevTabBaseAddr.u64; break; 1977 case IOMMU_MMIO_OFF_CMD_BUF_BAR: *puResult = pThis->CmdBufBaseAddr.u64; break; 1978 case IOMMU_MMIO_OFF_EVT_LOG_BAR: *puResult = pThis->EvtLogBaseAddr.u64; break; 1979 case IOMMU_MMIO_OFF_CTRL: *puResult = pThis->Ctrl.u64; break; 1980 case IOMMU_MMIO_OFF_EXCL_BAR: *puResult = pThis->ExclBase.u64; break; 1981 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: *puResult = pThis->ExclRangeLimit.u64; break; 1982 case IOMMU_MMIO_OFF_EXT_FEAT: *puResult = pThis->ExtFeat.u64; break; 1983 1984 case IOMMU_MMIO_OFF_PPR_LOG_BAR: *puResult = pThis->PprLogBaseAddr.u64; break; 1985 case IOMMU_MMIO_OFF_HW_EVT_HI: *puResult = pThis->HwEvtHi.u64; break; 1986 case IOMMU_MMIO_OFF_HW_EVT_LO: *puResult = pThis->HwEvtLo; break; 1987 case IOMMU_MMIO_OFF_HW_EVT_STATUS: *puResult = pThis->HwEvtStatus.u64; break; 1988 1989 case IOMMU_MMIO_OFF_GALOG_BAR: *puResult = pThis->GALogBaseAddr.u64; break; 1990 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: *puResult = pThis->GALogTailAddr.u64; break; 1991 1992 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: *puResult = pThis->PprLogBBaseAddr.u64; break; 1993 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: *puResult = pThis->EvtLogBBaseAddr.u64; break; 1994 1995 case IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST: 1996 case IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST: 1997 { 1998 uint8_t const idxDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3; 1999 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->DevTabSeg)); 2000 *puResult = pThis->DevTabSeg[idxDevTabSeg].u64; 2001 break; 2002 } 2003 2004 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: *puResult = pThis->DevSpecificFeat.u64; break; 2005 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: *puResult = pThis->DevSpecificCtrl.u64; break; 2006 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: *puResult = pThis->DevSpecificStatus.u64; break; 2007 2008 case IOMMU_MMIO_OFF_MSI_VECTOR_0: *puResult = pThis->MsiMiscInfo.u64; break; 2009 case IOMMU_MMIO_OFF_MSI_VECTOR_1: *puResult = pThis->MsiMiscInfo.au32[1]; break; 2010 case IOMMU_MMIO_OFF_MSI_CAP_HDR: *puResult = RT_MAKE_U64(pThis->MsiCapHdr.u32, pThis->MsiAddr.au32[0]); break; 2011 case IOMMU_MMIO_OFF_MSI_ADDR_LO: *puResult = pThis->MsiAddr.au32[0]; break; 2012 case IOMMU_MMIO_OFF_MSI_ADDR_HI: *puResult = RT_MAKE_U64(pThis->MsiAddr.au32[1], pThis->MsiData.u32); break; 2013 case IOMMU_MMIO_OFF_MSI_DATA: *puResult = pThis->MsiData.u32; break; 2014 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: *puResult = RT_MAKE_U64(pThis->MsiMapCapHdr.u32, pThis->PerfOptCtrl.u32); break; 2015 2016 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: *puResult = pThis->PerfOptCtrl.u32; break; 2017 2018 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: *puResult = pThis->XtGenIntrCtrl.u64; break; 2019 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: *puResult = pThis->XtPprIntrCtrl.u64; break; 2020 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: *puResult = pThis->XtGALogIntrCtrl.u64; break; 2021 2022 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: *puResult = pThis->aMarcApers[0].Base.u64; break; 2023 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: *puResult = pThis->aMarcApers[0].Reloc.u64; break; 2024 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: *puResult = pThis->aMarcApers[0].Length.u64; break; 2025 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: *puResult = pThis->aMarcApers[1].Base.u64; break; 2026 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: *puResult = pThis->aMarcApers[1].Reloc.u64; break; 2027 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: *puResult = pThis->aMarcApers[1].Length.u64; break; 2028 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: *puResult = pThis->aMarcApers[2].Base.u64; break; 2029 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: *puResult = pThis->aMarcApers[2].Reloc.u64; break; 2030 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: *puResult = pThis->aMarcApers[2].Length.u64; break; 2031 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: *puResult = pThis->aMarcApers[3].Base.u64; break; 2032 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: *puResult = pThis->aMarcApers[3].Reloc.u64; break; 2033 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: *puResult = pThis->aMarcApers[3].Length.u64; break; 2034 2035 case IOMMU_MMIO_OFF_RSVD_REG: *puResult = pThis->RsvdReg; break; 2036 2037 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: *puResult = pThis->CmdBufHeadPtr.u64; break; 2038 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: *puResult = pThis->CmdBufTailPtr.u64; break; 2039 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: *puResult = pThis->EvtLogHeadPtr.u64; break; 2040 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: *puResult = pThis->EvtLogTailPtr.u64; break; 2041 2042 case IOMMU_MMIO_OFF_STATUS: *puResult = pThis->Status.u64; break; 2043 2044 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: *puResult = pThis->PprLogHeadPtr.u64; break; 2045 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: *puResult = pThis->PprLogTailPtr.u64; break; 2046 2047 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: *puResult = pThis->GALogHeadPtr.u64; break; 2048 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: *puResult = pThis->GALogTailPtr.u64; break; 2049 2050 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: *puResult = pThis->PprLogBHeadPtr.u64; break; 2051 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: *puResult = pThis->PprLogBTailPtr.u64; break; 2052 2053 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: *puResult = pThis->EvtLogBHeadPtr.u64; break; 2054 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: *puResult = pThis->EvtLogBTailPtr.u64; break; 2055 2056 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: *puResult = pThis->PprLogAutoResp.u64; break; 2057 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: *puResult = pThis->PprLogOverflowEarly.u64; break; 2058 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: *puResult = pThis->PprLogBOverflowEarly.u64; break; 2059 2060 /* Not implemented. */ 2061 case IOMMU_MMIO_OFF_SMI_FLT_FIRST: 2062 case IOMMU_MMIO_OFF_SMI_FLT_LAST: 2063 { 2064 *puResult = 0; 2065 break; 2066 } 2067 2068 /* Unknown */ 2069 default: 2070 { 2071 *puResult = 0; 2072 ASSERT_GUEST_MSG_FAILED((IOMMU_LOG_PFX ": iommuAmdReadRegister: Unknown offset %u (cb=%u)\n", off, cb)); 2073 break; 2074 } 2075 } 2076 } 2077 2078 1801 2079 /** 1802 2080 * @callback_method_impl{FNIOMMMIONEWWRITE} … … 1815 2093 static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb) 1816 2094 { 1817 /** @todo IOMMU: MMIO read. */ 1818 RT_NOREF5(pDevIns, pvUser, off, pv, cb); 1819 return VERR_NOT_IMPLEMENTED; 2095 NOREF(pvUser); 2096 Assert(cb == 4 || cb == 8); 2097 2098 uint64_t uResult = 0; 2099 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); 2100 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pThis, off, cb, &uResult); 2101 if (cb == 8) 2102 *(uint64_t *)pv = uResult; 2103 else 2104 *(uint32_t *)pv = (uint32_t)uResult; 2105 2106 return rcStrict; 1820 2107 } 1821 2108 … … 2007 2294 */ 2008 2295 rc = PDMDevHlpMmioCreateAndMap(pDevIns, u64MmioBase, IOMMU_MMIO_REGION_SIZE, iommuAmdMmioWrite, iommuAmdMmioRead, 2009 IOMMMIO_FLAGS_READ_ PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,2296 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING, 2010 2297 "IOMMU-AMD", &pThis->hMmio); 2011 2298 AssertRCReturn(rc, rc);
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