Changeset 8361 in vbox
- Timestamp:
- Apr 24, 2008 1:59:24 PM (17 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
-
include/VBox/disopcode.h (modified) (1 diff)
-
src/VBox/Disassembler/Disasm.cpp (modified) (10 diffs)
-
src/VBox/Disassembler/DisasmCore.cpp (modified) (8 diffs)
-
src/VBox/Disassembler/DisasmTables.cpp (modified) (2 diffs)
-
src/VBox/Disassembler/DisasmTablesX64.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/disopcode.h
r8336 r8361 46 46 #define OP_INVALID 0 47 47 #define OP_OPSIZE 1 48 #define OP_AD RSIZE248 #define OP_ADDRSIZE 2 49 49 #define OP_SEG 3 50 50 #define OP_REPNE 4 -
trunk/src/VBox/Disassembler/Disasm.cpp
r8333 r8361 92 92 */ 93 93 DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, 94 94 char *pszOutput) 95 95 { 96 96 return DISInstrEx(pCpu, pu8Instruction, u32EipOffset, pcbSize, pszOutput, OPTYPE_ALL); … … 113 113 */ 114 114 DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, 115 115 char *pszOutput, unsigned uFilter) 116 116 { 117 117 unsigned i = 0, prefixbytes; … … 124 124 pCpu->prefix = PREFIX_NONE; 125 125 pCpu->prefix_seg = 0; 126 pCpu->addrmode = pCpu->mode;127 pCpu->opmode = pCpu->mode;128 126 pCpu->ModRM.u = 0; 129 127 pCpu->SIB.u = 0; … … 147 145 *pszOutput = '\0'; 148 146 147 if (pCpu->mode == CPUMODE_64BIT) 148 { 149 pCpu->addrmode = CPUMODE_64BIT; 150 pCpu->opmode = CPUMODE_32BIT; 151 } 152 else 153 { 154 pCpu->addrmode = pCpu->mode; 155 pCpu->opmode = pCpu->mode; 156 } 157 149 158 prefixbytes = 0; 150 159 #ifndef __L4ENV__ /* Unfortunately, we have no exception handling in l4env */ … … 164 173 { 165 174 pCpu->lastprefix = opcode; 175 176 /* The REX prefix must precede the opcode byte(s). Any other placement is ignored. */ 177 if (opcode != OP_REX) 178 pCpu->prefix &= ~PREFIX_REX; 179 166 180 switch(opcode) 167 181 { … … 175 189 case OP_SEG: 176 190 pCpu->prefix_seg = g_aOneByteMapX86[codebyte].param1 - OP_PARM_REG_SEG_START; 177 pCpu->prefix |= PREFIX_SEG; 191 /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */ 192 if ( pCpu->mode != CPUMODE_64BIT 193 || pCpu->prefix_seg >= OP_PARM_REG_FS) 194 { 195 pCpu->prefix |= PREFIX_SEG; 196 } 178 197 i += sizeof(uint8_t); 179 198 prefixbytes++; … … 188 207 189 208 // address size override prefix byte 190 case OP_AD RSIZE:209 case OP_ADDRSIZE: 191 210 pCpu->prefix |= PREFIX_ADDRSIZE; 192 if(pCpu->mode == CPUMODE_16BIT) 193 pCpu->addrmode = CPUMODE_32BIT; 194 else pCpu->addrmode = CPUMODE_16BIT; 211 if (pCpu->mode == CPUMODE_16BIT) 212 pCpu->addrmode = CPUMODE_32BIT; 213 else 214 if (pCpu->mode == CPUMODE_32BIT) 215 pCpu->addrmode = CPUMODE_16BIT; 216 else 217 pCpu->addrmode = CPUMODE_32BIT; /* 64 bits */ 218 195 219 i += sizeof(uint8_t); 196 220 prefixbytes++; … … 200 224 case OP_OPSIZE: 201 225 pCpu->prefix |= PREFIX_OPSIZE; 202 if(pCpu->mode == CPUMODE_16BIT) 203 pCpu->opmode = CPUMODE_32BIT; 204 else pCpu->opmode = CPUMODE_16BIT; 226 if (pCpu->mode == CPUMODE_16BIT) 227 pCpu->opmode = CPUMODE_32BIT; 228 else 229 pCpu->opmode = CPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */ 230 205 231 i += sizeof(uint8_t); 206 232 prefixbytes++; … … 225 251 pCpu->prefix |= PREFIX_REX; 226 252 pCpu->prefix_rex = PREFIX_REX_OP_2_FLAGS(opcode); 253 254 if (pCpu->prefix_rex & PREFIX_REX_FLAGS_W) 255 pCpu->opmode = CPUMODE_64BIT; /* overrides size prefix byte */ 227 256 break; 228 257 } … … 390 419 case 'e': //register based on operand size (e.g. %eAX) 391 420 if(pCpu->opmode == CPUMODE_32BIT) 392 {393 421 RTStrPrintf(&pszOutput[strlen(pszOutput)], 64, "E"); 394 } 422 if(pCpu->opmode == CPUMODE_64BIT) 423 RTStrPrintf(&pszOutput[strlen(pszOutput)], 64, "R"); 424 395 425 RTStrPrintf(&pszOutput[strlen(pszOutput)], 64, "%c%c", lpszFormat[2], lpszFormat[3]); 396 426 break; -
trunk/src/VBox/Disassembler/DisasmCore.cpp
r8357 r8361 174 174 pCpu->prefix_seg = 0; 175 175 pCpu->lastprefix = 0; 176 pCpu->addrmode = pCpu->mode;177 pCpu->opmode = pCpu->mode;178 176 pCpu->ModRM.u = 0; 179 177 pCpu->SIB.u = 0; … … 221 219 pCpu->lastprefix = 0; 222 220 pCpu->mode = enmCpuMode; 223 pCpu->addrmode = enmCpuMode;224 pCpu->opmode = enmCpuMode;225 221 pCpu->ModRM.u = 0; 226 222 pCpu->SIB.u = 0; … … 261 257 unsigned cbInc; 262 258 259 if (pCpu->mode == CPUMODE_64BIT) 260 { 261 pCpu->addrmode = CPUMODE_64BIT; 262 pCpu->opmode = CPUMODE_32BIT; 263 } 264 else 265 { 266 pCpu->addrmode = pCpu->mode; 267 pCpu->opmode = pCpu->mode; 268 } 269 263 270 while(1) 264 271 { … … 284 291 case OP_SEG: 285 292 pCpu->prefix_seg = g_aOneByteMapX86[codebyte].param1 - OP_PARM_REG_SEG_START; 286 pCpu->prefix |= PREFIX_SEG; 287 iByte += sizeof(uint8_t); 293 /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */ 294 if ( pCpu->mode != CPUMODE_64BIT 295 || pCpu->prefix_seg >= OP_PARM_REG_FS) 296 { 297 pCpu->prefix |= PREFIX_SEG; 298 } 299 iByte += sizeof(uint8_t); 288 300 continue; //fetch the next byte 289 301 … … 295 307 296 308 // address size override prefix byte 297 case OP_AD RSIZE:309 case OP_ADDRSIZE: 298 310 pCpu->prefix |= PREFIX_ADDRSIZE; 299 311 if (pCpu->mode == CPUMODE_16BIT) 300 pCpu->addrmode = CPUMODE_32BIT; 301 else pCpu->addrmode = CPUMODE_16BIT; 312 pCpu->addrmode = CPUMODE_32BIT; 313 else 314 if (pCpu->mode == CPUMODE_32BIT) 315 pCpu->addrmode = CPUMODE_16BIT; 316 else 317 pCpu->addrmode = CPUMODE_32BIT; /* 64 bits */ 318 302 319 iByte += sizeof(uint8_t); 303 320 continue; //fetch the next byte … … 307 324 pCpu->prefix |= PREFIX_OPSIZE; 308 325 if (pCpu->mode == CPUMODE_16BIT) 309 pCpu->opmode = CPUMODE_32BIT; 310 else pCpu->opmode = CPUMODE_16BIT; 326 pCpu->opmode = CPUMODE_32BIT; 327 else 328 pCpu->opmode = CPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */ 311 329 312 330 iByte += sizeof(uint8_t); … … 390 408 pCpu->param3.param = pOp->param3; 391 409 410 /* Correct the operand size if the instruction is marked as forced or default 64 bits */ 411 if (pCpu->mode == CPUMODE_64BIT) 412 { 413 if (pOp->optype & OPTYPE_FORCED_64_OP_SIZE) 414 pCpu->opsize = CPUMODE_64BIT; 415 else 416 if ( (pOp->optype & OPTYPE_DEFAULT_64_OP_SIZE) 417 && !(pCpu->prefix & PREFIX_OPSIZE)) 418 pCpu->opsize = CPUMODE_64BIT; 419 } 420 392 421 if (pOp->idxParse1 != IDX_ParseNop) 393 422 { … … 450 479 /* Not filtered out -> full disassembly */ 451 480 pCpu->pfnDisasmFnTable = pfnFullDisasm; 481 } 482 483 /* Correct the operand size if the instruction is marked as forced or default 64 bits */ 484 if (pCpu->mode == CPUMODE_64BIT) 485 { 486 /* Note: redundant, but just in case this ever changes */ 487 if (fpop->optype & OPTYPE_FORCED_64_OP_SIZE) 488 pCpu->opsize = CPUMODE_64BIT; 489 else 490 if ( (fpop->optype & OPTYPE_DEFAULT_64_OP_SIZE) 491 && !(pCpu->prefix & PREFIX_OPSIZE)) 492 pCpu->opsize = CPUMODE_64BIT; 452 493 } 453 494 -
trunk/src/VBox/Disassembler/DisasmTables.cpp
r8357 r8361 199 199 OP("SEG GS", 0, 0, 0, OP_SEG, OP_PARM_REG_GS, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 200 200 OP("OP SIZE", 0, 0, 0, OP_OPSIZE, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 201 OP("ADR SIZE", 0, 0, 0, OP_AD RSIZE,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),201 OP("ADR SIZE", 0, 0, 0, OP_ADDRSIZE,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 202 202 OP("push %Iv", IDX_ParseImmV, 0, 0, OP_PUSH, OP_PARM_Iv, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS | OPTYPE_DEFAULT_64_OP_SIZE), 203 203 OP("imul %Gv,%Ev,%Iv", IDX_ParseModRM, IDX_UseModRM, IDX_ParseImmV, OP_IMUL, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_Iv, OPTYPE_HARMLESS), … … 517 517 518 518 /* 7 */ 519 OP("pshufw %Pq,%Qq,%Ib", IDX_ParseModRM, IDX_UseModRM, IDX_ParseImmByte, OP_PSHUFW,OP_PARM_Pq, OP_PARM_Qq, OP_PARM_Ib, OPTYPE_HARMLESS),520 OP("Grp12", IDX_ParseGrp12, 0, 0,OP_GRP12, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),521 OP("Grp13", IDX_ParseGrp13, 0, 0,OP_GRP13, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),522 OP("Grp14", IDX_ParseGrp14, 0, 0,OP_GRP14, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),523 OP("pcmpeqb %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQB, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, OPTYPE_HARMLESS),524 OP("pcmpeqw %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQW, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, OPTYPE_HARMLESS),525 OP("pcmpeqd %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQD, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, OPTYPE_HARMLESS),526 OP("emms", 0, 0, 0,OP_EMMS, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),527 OP("MMX UD 0x78", 0, 0, 0,OP_MMX_UD78,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),528 OP("MMX UD 0x79", 0, 0, 0,OP_MMX_UD79,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),529 OP("MMX UD 0x7A", 0, 0, 0,OP_MMX_UD7A,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),530 OP("MMX UD 0x7B", 0, 0, 0,OP_MMX_UD7B,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),531 OP("MMX UD 0x7C", 0, 0, 0,OP_MMX_UD7C,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),532 OP("MMX UD 0x7D", 0, 0, 0,OP_MMX_UD7D,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),533 OP("movd %Ed,%Pd", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVD, OP_PARM_Ed, OP_PARM_Pd, OP_PARM_NONE, OPTYPE_HARMLESS),534 OP("movq %Qq,%Pq", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVQ, OP_PARM_Qq, OP_PARM_Pq, OP_PARM_NONE, OPTYPE_HARMLESS),519 OP("pshufw %Pq,%Qq,%Ib", IDX_ParseModRM, IDX_UseModRM, IDX_ParseImmByte, OP_PSHUFW, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_Ib, OPTYPE_HARMLESS), 520 OP("Grp12", IDX_ParseGrp12, 0, 0, OP_GRP12, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 521 OP("Grp13", IDX_ParseGrp13, 0, 0, OP_GRP13, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 522 OP("Grp14", IDX_ParseGrp14, 0, 0, OP_GRP14, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 523 OP("pcmpeqb %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQB, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, OPTYPE_HARMLESS), 524 OP("pcmpeqw %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQW, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, OPTYPE_HARMLESS), 525 OP("pcmpeqd %Pq,%Qq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PCMPEQD, OP_PARM_Pq, OP_PARM_Qq, OP_PARM_NONE, OPTYPE_HARMLESS), 526 OP("emms", 0, 0, 0, OP_EMMS, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 527 OP("MMX UD 0x78", 0, 0, 0, OP_MMX_UD78,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 528 OP("MMX UD 0x79", 0, 0, 0, OP_MMX_UD79,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 529 OP("MMX UD 0x7A", 0, 0, 0, OP_MMX_UD7A,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 530 OP("MMX UD 0x7B", 0, 0, 0, OP_MMX_UD7B,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 531 OP("MMX UD 0x7C", 0, 0, 0, OP_MMX_UD7C,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 532 OP("MMX UD 0x7D", 0, 0, 0, OP_MMX_UD7D,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 533 OP("movd %Ed,%Pd", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVD, OP_PARM_Ed, OP_PARM_Pd, OP_PARM_NONE, OPTYPE_HARMLESS), 534 OP("movq %Qq,%Pq", IDX_ParseModRM, IDX_UseModRM, 0, OP_MOVQ, OP_PARM_Qq, OP_PARM_Pq, OP_PARM_NONE, OPTYPE_HARMLESS), 535 535 536 536 /* 8 */ -
trunk/src/VBox/Disassembler/DisasmTablesX64.cpp
r8357 r8361 199 199 OP("SEG GS", 0, 0, 0, OP_SEG, OP_PARM_REG_GS, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 200 200 OP("OP SIZE", 0, 0, 0, OP_OPSIZE, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 201 OP("AD R SIZE", 0, 0, 0, OP_ADRSIZE,OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS),201 OP("ADDR SIZE", 0, 0, 0, OP_ADDRSIZE, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS), 202 202 OP("push %Iv", IDX_ParseImmV, 0, 0, OP_PUSH, OP_PARM_Iv, OP_PARM_NONE, OP_PARM_NONE, OPTYPE_HARMLESS | OPTYPE_DEFAULT_64_OP_SIZE), 203 203 OP("imul %Gv,%Ev,%Iv", IDX_ParseModRM, IDX_UseModRM, IDX_ParseImmV, OP_IMUL, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_Iv, OPTYPE_HARMLESS),
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