Changeset 83669 in vbox
- Timestamp:
- Apr 10, 2020 1:42:32 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 137150
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (12 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r83666 r83669 1454 1454 } MSI_ADDR_T; 1455 1455 AssertCompileSize(MSI_ADDR_T, 8); 1456 #define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc) 1456 1457 1457 1458 /** … … 1470 1471 } MSI_DATA_T; 1471 1472 AssertCompileSize(MSI_DATA_T, 4); 1473 #define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff) 1472 1474 1473 1475 /** … … 2078 2080 * Writes to a read-only register. 2079 2081 */ 2080 static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2081 { 2082 RT_NOREF(pDevIns, pThis, iReg );2082 static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2083 { 2084 RT_NOREF(pDevIns, pThis, iReg, u64Value); 2083 2085 Log((IOMMU_LOG_PFX ": iommuAmdIgnore_w: Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value)); 2084 2086 return VINF_SUCCESS; … … 2089 2091 * Writes the Device Table Base Address Register. 2090 2092 */ 2091 static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2092 { 2093 RT_NOREF(pDevIns, pThis,iReg);2093 static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2094 { 2095 RT_NOREF(pDevIns, iReg); 2094 2096 pThis->DevTabBaseAddr.u64 = u64Value & IOMMU_DEV_TAB_BAR_VALID_MASK; 2095 2097 return VINF_SUCCESS; … … 2100 2102 * Writes the Command Buffer Base Address Register. 2101 2103 */ 2102 static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2103 { 2104 RT_NOREF(pDevIns, pThis,iReg);2104 static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2105 { 2106 RT_NOREF(pDevIns, iReg); 2105 2107 pThis->CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK; 2106 2108 iommuAmdCheckBufferLength(pThis->CmdBufBaseAddr.n.u4CmdLen, __PRETTY_FUNCTION__); … … 2111 2113 * Writes the Event Log Base Address Register. 2112 2114 */ 2113 static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2114 { 2115 RT_NOREF(pDevIns, pThis,iReg);2115 static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2116 { 2117 RT_NOREF(pDevIns, iReg); 2116 2118 pThis->EvtLogBaseAddr.u64 = u64Value & IOMMU_EVT_LOG_BAR_VALID_MASK; 2117 2119 iommuAmdCheckBufferLength(pThis->EvtLogBaseAddr.n.u4EvtLen, __PRETTY_FUNCTION__); … … 2123 2125 * Writes to the Excluse Range Base Address Register. 2124 2126 */ 2125 static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2126 { 2127 RT_NOREF(pDevIns, pThis,iReg);2127 static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2128 { 2129 RT_NOREF(pDevIns, iReg); 2128 2130 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK; 2129 2131 return VINF_SUCCESS; … … 2134 2136 * Writes to the Excluse Range Limit Register. 2135 2137 */ 2136 static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2137 { 2138 RT_NOREF(pDevIns, pThis,iReg);2138 static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2139 { 2140 RT_NOREF(pDevIns, iReg); 2139 2141 pThis->ExclRangeLimit.u64 = u64Value & IOMMU_EXCL_RANGE_LIMIT_VALID_MASK; 2140 2142 return VINF_SUCCESS; … … 2145 2147 * Writes the PPR Log Base Address Register. 2146 2148 */ 2147 static VBOXSTRICTRC iommuAmdPprLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t 2148 { 2149 RT_NOREF(pDevIns, pThis,iReg);2149 static VBOXSTRICTRC iommuAmdPprLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2150 { 2151 RT_NOREF(pDevIns, iReg); 2150 2152 pThis->PprLogBaseAddr.u64 = u64Value & IOMMU_PPR_LOG_BAR_VALID_MASK; 2151 2153 iommuAmdCheckBufferLength(pThis->PprLogBaseAddr.n.u4PprLogLen, __PRETTY_FUNCTION__); 2154 return VINF_SUCCESS; 2155 } 2156 2157 2158 /** 2159 * Writes the MSI Address (Lo) Register (32-bit). 2160 */ 2161 static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2162 { 2163 RT_NOREF(pDevIns, iReg); 2164 Assert(!RT_HI_U32(u64Value)); 2165 pThis->MsiAddr.au32[0] = u64Value & IOMMU_MSI_ADDR_VALID_MASK; 2166 return VINF_SUCCESS; 2167 } 2168 2169 2170 /** 2171 * Writes the MSI Address (Hi) Register (32-bit). 2172 */ 2173 static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2174 { 2175 RT_NOREF(pDevIns, iReg); 2176 Assert(!RT_HI_U32(u64Value)); 2177 pThis->MsiAddr.au32[1] = u64Value; 2178 return VINF_SUCCESS; 2179 } 2180 2181 2182 /** 2183 * Writes the MSI Data Register (32-bit). 2184 */ 2185 static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value) 2186 { 2187 RT_NOREF(pDevIns, iReg); 2188 pThis->MsiData.u32 = u64Value & IOMMU_MSI_DATA_VALID_MASK; 2152 2189 return VINF_SUCCESS; 2153 2190 } … … 2191 2228 switch (off) 2192 2229 { 2193 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);2194 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);2195 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);2196 case IOMMU_MMIO_OFF_CTRL: 2197 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);2198 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);2199 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2200 2201 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdPprLogBar_w(pDevIns, pThis, off, uValue);2202 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2203 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2204 case IOMMU_MMIO_OFF_HW_EVT_STATUS: 2205 2206 case IOMMU_MMIO_OFF_GALOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2207 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2208 2209 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2210 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);2230 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue); 2231 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue); 2232 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue); 2233 case IOMMU_MMIO_OFF_CTRL: /** @todo IOMMU: Control register. */ 2234 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue); 2235 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue); 2236 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2237 2238 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdPprLogBar_w(pDevIns, pThis, off, uValue); 2239 case IOMMU_MMIO_OFF_HW_EVT_HI: 2240 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2241 case IOMMU_MMIO_OFF_HW_EVT_STATUS: /** @todo IOMMU: HW Event Status is RW. Figure this out later. */ 2242 2243 case IOMMU_MMIO_OFF_GALOG_BAR: 2244 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2245 2246 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: 2247 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2211 2248 2212 2249 case IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST: … … 2220 2257 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: 2221 2258 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: 2222 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: 2259 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2223 2260 2224 2261 case IOMMU_MMIO_OFF_MSI_VECTOR_0: 2225 case IOMMU_MMIO_OFF_MSI_VECTOR_1: 2262 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2226 2263 case IOMMU_MMIO_OFF_MSI_CAP_HDR: 2227 case IOMMU_MMIO_OFF_MSI_ADDR_LO: 2264 { 2265 VBOXSTRICTRC rcStrict = iommuAmdIgnore_w(pDevIns, pThis, off, (uint32_t)uValue); 2266 if (cb == 4 || RT_FAILURE(rcStrict)) 2267 return rcStrict; 2268 uValue >>= 32; 2269 RT_FALL_THRU(); 2270 } 2271 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue); 2228 2272 case IOMMU_MMIO_OFF_MSI_ADDR_HI: 2229 case IOMMU_MMIO_OFF_MSI_DATA: 2230 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: 2231 2232 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: 2273 { 2274 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue); 2275 if (cb == 4 || RT_FAILURE(rcStrict)) 2276 return rcStrict; 2277 uValue >>= 32; 2278 RT_FALL_THRU(); 2279 } 2280 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue); 2281 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2282 2283 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2233 2284 2234 2285 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: 2235 2286 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: 2236 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: 2287 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2237 2288 2238 2289 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: … … 2247 2298 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: 2248 2299 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: 2249 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: 2250 2251 case IOMMU_MMIO_OFF_RSVD_REG: 2300 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2301 2302 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue); 2252 2303 2253 2304 case IOMMU_MMIO_CMD_BUF_HEAD_PTR:
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