Changeset 83714 in vbox for trunk/src/VBox/Devices

Timestamp:

Apr 16, 2020 9:37:02 AM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

137224

Message:

AMD IOMMU: bugref:9654 Bits.

File:

• trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (3 diffs)

trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

@@ -2072 +2072 @@
 
 
-DECLINLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
+DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
 {
     IOMMU_STATUS_T Status;
@@ -2129 +2129 @@
     pThis->CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
     iommuAmdCheckBufferLength(pThis->CmdBufBaseAddr.n.u4CmdLen, __PRETTY_FUNCTION__);
+
+    /*
+     * While this is not explicitly specified like the event log base address register,
+     * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
+     * Inconsistent specs :/
+     */
+    IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
+    if (Status.n.u1CmdBufRunning)
+    {
+        Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
+        return VINF_SUCCESS;
+    }
+
+    /*
+     * Writing the command log base address, clears the command buffer head and tail pointers.
+     * See AMD spec. 2.4 "Commands".
+     */
+    pThis->CmdBufHeadPtr.u64 = 0;
+    pThis->CmdBufTailPtr.u64 = 0;
+
     return VINF_SUCCESS;
 }
@@ -3539 +3559 @@
     MsiReg.iMsiCapOffset  = IOMMU_PCI_OFF_MSI_CAP_HDR;
     MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
+    MsiReg.fMsi64bit      = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
     rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
     AssertRCReturn(rc, rc);