Changeset 8379 in vbox for trunk/src/VBox

Timestamp:

Apr 25, 2008 9:09:35 AM (17 years ago)

Author:

vboxsync

Message:

More fixes.

Location:

trunk/src/VBox/Disassembler

Files:

• Disasm.cpp (modified) (1 diff)
• DisasmCore.cpp (modified) (9 diffs)
• DisasmTestA.asm (modified) (2 diffs)

trunk/src/VBox/Disassembler/Disasm.cpp

@@ -175 +175 @@
             if (opcode <= OP_LAST_PREFIX)
             {
-                pCpu->lastprefix = opcode;
-
                 /* The REX prefix must precede the opcode byte(s). Any other placement is ignored. */
                 if (opcode != OP_REX)
+                {
+                    pCpu->lastprefix = opcode;
                     pCpu->prefix &= ~PREFIX_REX;
+                }
 
                 switch(opcode)

trunk/src/VBox/Disassembler/DisasmCore.cpp

@@ -280 +280 @@
         if (opcode <= OP_LAST_PREFIX)
         {
-            pCpu->lastprefix = opcode;
-
             /* The REX prefix must precede the opcode byte(s). Any other placement is ignored. */
             if (opcode != OP_REX)
+            {
+                /** Last prefix byte (for SSE2 extension tables); don't include the REX prefix */
+                pCpu->lastprefix = opcode;
                 pCpu->prefix &= ~PREFIX_REX;
+            }
 
             switch (opcode)
@@ -516 +518 @@
 // Scale  Index  Base
 //*****************************************************************************
-const char *szSIBBaseReg[8]  = {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"};
-const char *szSIBIndexReg[8] = {"EAX", "ECX", "EDX", "EBX", NULL,  "EBP", "ESI", "EDI"};
+const char *szSIBBaseReg[8]    = {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"};
+const char *szSIBIndexReg[8]   = {"EAX", "ECX", "EDX", "EBX", NULL,  "EBP", "ESI", "EDI"};
+const char *szSIBBaseReg64[16] = {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
+const char *szSIBIndexReg64[16]= {"RAX", "RCX", "RDX", "RBX", NULL,  "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
 const char *szSIBScale[4]    = {"", "*2", "*4", "*8"};
 
@@ -523 +527 @@
 void UseSIB(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
 {
-    unsigned scale, base, index;
+    unsigned scale, base, index, regtype;
+    const char **ppszSIBIndexReg;
+    const char **ppszSIBBaseReg;
     char szTemp[32];
     szTemp[0] = '\0';
@@ -531 +537 @@
     index = pCpu->SIB.Bits.Index;
 
-    if (szSIBIndexReg[index])
+    if (pCpu->addrmode == CPUMODE_32BIT)
+    {
+        ppszSIBIndexReg = szSIBIndexReg;
+        ppszSIBBaseReg  = szSIBBaseReg;
+        regtype         = USE_REG_GEN32;
+    }
+    else
+    {
+        ppszSIBIndexReg = szSIBIndexReg64;
+        ppszSIBBaseReg  = szSIBBaseReg64;
+        regtype         = USE_REG_GEN64;
+    }
+
+    if (ppszSIBIndexReg[index])
     {
          pParam->flags |= USE_INDEX;
@@ -543 +562 @@
 
          if (base == 5 && pCpu->ModRM.Bits.Mod == 0)
-             disasmAddStringF(szTemp, sizeof(szTemp), "%s%s", szSIBIndexReg[index], szSIBScale[scale]);
+             disasmAddStringF(szTemp, sizeof(szTemp), "%s%s", ppszSIBIndexReg[index], szSIBScale[scale]);
          else
-             disasmAddStringF(szTemp, sizeof(szTemp), "%s+%s%s", szSIBBaseReg[base], szSIBIndexReg[index], szSIBScale[scale]);
+             disasmAddStringF(szTemp, sizeof(szTemp), "%s+%s%s", ppszSIBBaseReg[base], ppszSIBIndexReg[index], szSIBScale[scale]);
     }
     else
     {
          if (base != 5 || pCpu->ModRM.Bits.Mod != 0)
-             disasmAddStringF(szTemp, sizeof(szTemp), "%s", szSIBBaseReg[base]);
+             disasmAddStringF(szTemp, sizeof(szTemp), "%s", ppszSIBBaseReg[base]);
     }
 
@@ -566 +585 @@
         disasmAddString(pParam->szParam, szTemp);
 
-        pParam->flags |= USE_BASE | USE_REG_GEN32;
+        pParam->flags |= USE_BASE | regtype;
         pParam->base.reg_gen = base;
     }
@@ -691 +710 @@
                 if (mod != 3)
                     break;  /* memory operand */
+                reg = rm; /* the RM field specifies the xmm register */
                 /* else no break */
+
             case OP_PARM_V: //XMM register
                 disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "XMM%d", reg);
@@ -2028 +2049 @@
     subtype = OP_PARM_VSUBTYPE(pParam->param);
     if (fRegAddr)
-        subtype = (pCpu->opmode == CPUMODE_64BIT) ? OP_PARM_q : OP_PARM_d;
+        subtype = (pCpu->addrmode == CPUMODE_64BIT) ? OP_PARM_q : OP_PARM_d;
     else
     if (subtype == OP_PARM_v || subtype == OP_PARM_NONE)
@@ -2152 +2173 @@
     if (subtype == OP_PARM_v)
     {
-        subtype = (pCpu->opmode == CPUMODE_32BIT) ? OP_PARM_d : OP_PARM_w;
+        switch(pCpu->opmode)
+        {
+        case CPUMODE_32BIT:
+            subtype = OP_PARM_d;
+            break;
+        case CPUMODE_64BIT:
+            subtype = OP_PARM_q;
+            break;
+        case CPUMODE_16BIT:
+            subtype = OP_PARM_w;
+            break;
+        }
     }
 

trunk/src/VBox/Disassembler/DisasmTestA.asm

@@ -72 +72 @@
       movzx rax,byte  [edx]
       movzx rax,word  [edx]
+      movzx rax,byte  [rdx]
       lock cmpxchg [rcx], rax
       lock cmpxchg [rcx], ax
@@ -82 +83 @@
       mov rbx, [rbp + rax*4 + 4]
       mov rbx, [rbp + rax*4]
+      mov rbx, [ebp + eax*4]
       int 80h
       in  al, 60h