Changeset 84060 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

Apr 28, 2020 5:13:50 PM (5 years ago)

Author:

vboxsync

Message:

AMD IOMMU: bugref:9654 Bits.

File:

• trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (8 diffs)

trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

@@ -417 +417 @@
 /** PprOverflowEarly: PPR log overflow early warning. */
 #define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY         RT_BIT_64(18)
+/** @} */
+
+/**
+ * @name IOMMU Control Register Bits.
+ * In accordance with the AMD spec.
+ * @{
+ */
+/** IommuEn: Enable the IOMMU. */
+#define IOMMU_CTRL_IOMMU_EN                         RT_BIT_64(0)
+/** HtTunEn: HyperTransport tunnel translation enable. */
+#define IOMMU_CTRL_HT_TUNNEL_EN                     RT_BIT_64(1)
+/** EventLogEn: Event log enable. */
+#define IOMMU_CTRL_EVT_LOG_EN                       RT_BIT_64(2)
+/** EventIntEn: Event interrupt enable. */
+#define IOMMU_CTRL_EVT_INTR_EN                      RT_BIT_64(3)
+/** ComWaitIntEn: Completion wait interrupt enable. */
+#define IOMMU_CTRL_COMPLETION_WAIT_INTR_EN          RT_BIT_64(4)
+/** InvTimeout: Invalidation timeout. */
+#define IOMMU_CTRL_INV_TIMEOUT                      RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7)
+/** @todo IOMMU: the rest or remove it. */
 /** @} */
 
@@ -1221 +1241 @@
 } IOMMU_CTRL_T;
 AssertCompileSize(IOMMU_CTRL_T, 8);
+#define IOMMU_CTRL_VALID_MASK       UINT64_C(0x004defffffffffff)
 
 /**
@@ -2209 +2230 @@
 
 
+/**
+ * The IOMMU command thread.
+ *
+ * @returns VBox status code.
+ * @param   pDevIns     The IOMMU device instance.
+ * @param   pThread     The command thread.
+ */
+static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
+{
+    RT_NOREF(pDevIns, pThread);
+}
+
+
+/**
+ * Unblocks the command thread so it can respond to a state change.
+ *
+ * @returns VBox status code.
+ * @param   pDevIns     The IOMMU device instance.
+ * @param   pThread     The command thread.
+ */
+static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
+{
+    RT_NOREF(pThread);
+    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
+    return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
+}
+
 
 /**
@@ -2280 +2328 @@
 
     /*
-     * Writing the command log base address, clears the command buffer head and tail pointers.
+     * Writing the command buffer base address, clears the command buffer head and tail pointers.
      * See AMD spec. 2.4 "Commands".
      */
@@ -2335 +2383 @@
 
     return VINF_SUCCESS;
+}
+
+
+/**
+ * Writes the Control Register.
+ */
+static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
+{
+    RT_NOREF(pDevIns, iReg);
+
+    /* Mask out all unrecognized bits. */
+    u64Value &= IOMMU_CTRL_VALID_MASK;
+
+    IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
+    IOMMU_CTRL_T NewCtrl;
+    NewCtrl.u64 = u64Value;
+
+    /* Enable or disable event logging when the bit transitions. */
+    if (OldCtrl.n.u1EvtLogEn != NewCtrl.n.u1EvtLogEn)
+    {
+        if (NewCtrl.n.u1EvtLogEn)
+        {
+            ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
+            ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
+        }
+        else
+            ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
+    }
+
+    /* Update the control register. */
+    ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
+
+    /* Enable or disable command buffer processing when the bit transitions. */
+    if (OldCtrl.n.u1CmdBufEn != NewCtrl.n.u1CmdBufEn)
+    {
+        if (NewCtrl.n.u1CmdBufEn)
+        {
+            ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
+            /* If the command buffer isn't empty, kick the command thread to start processing commands. */
+            if (pThis->CmdBufHeadPtr.n.u15Ptr != pThis->CmdBufTailPtr.n.u15Ptr)
+                PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
+        }
+        else
+        {
+            ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
+            /* Kick the command thread to stop processing commands. */
+            PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
+        }
+    }
 }
 
@@ -2623 +2720 @@
 
 
-/**
- * The IOMMU command thread.
- *
- * @returns VBox status code.
- * @param   pDevIns     The IOMMU device instance.
- * @param   pThread     The command thread.
- */
-static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
-{
-    RT_NOREF(pDevIns, pThread);
-}
-
-
-/**
- * Unblocks the command thread so it can respond to a state change.
- *
- * @returns VBox status code.
- * @param   pDevIns     The IOMMU device instance.
- * @param   pThread     The command thread.
- */
-static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
-{
-    RT_NOREF(pThread);
-    PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
-    return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
-}
-
-
 #if 0
 /**
@@ -2689 +2758 @@
         case IOMMU_MMIO_OFF_CMD_BUF_BAR:         return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
         case IOMMU_MMIO_OFF_EVT_LOG_BAR:         return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
-        case IOMMU_MMIO_OFF_CTRL:                /** @todo IOMMU: Control register. */
+        case IOMMU_MMIO_OFF_CTRL:                return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
         case IOMMU_MMIO_OFF_EXCL_BAR:            return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
         case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT:    return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
@@ -2998 +3067 @@
 
 /**
- * Writes an entry to the event log.
+ * Writes an entry to the event log in memory.
  *
  * @returns VBox status code.