Changeset 84183 in vbox

Timestamp:

May 7, 2020 11:23:48 AM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

137790

Message:

AMD IOMMU: bugref:9654 Bits.

File:

• trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (9 diffs)

trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp

@@ -481 +481 @@
 /** Maximum number of host address translation levels supported. */
 #define IOMMU_MAX_HOST_PT_LEVEL                     6
+/** The IOTLB entry magic. */
+#define IOMMU_IOTLBE_MAGIC                          0x10acce55
 /** @} */
 
@@ -2213 +2215 @@
 typedef struct
 {
+    /** Magic (IOMMU_IOTLBE_MAGIC). */
+    uint32_t        uMagic;
+    /** Reserved for future (eviction hints?). */
+    uint16_t        uRsvd0;
     /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
     uint8_t         fIoPerm;
     /** The number of offset bits in the system physical address. */
     uint8_t         cShift;
-    /** Reserved for future (eviction hints?). */
-    uint16_t        uRsvd0;
-    /** Alignment padding. */
-    uint32_t        uRsvd1;
     /** The translated system physical address of the page. */
     RTGCPHYS        GCPhysSpa;
@@ -3780 +3782 @@
 static void iommuAmdInitIotlbe(RTGCPHYS GCPhysSpa, uint8_t cShift, uint8_t fIoPerm, PIOTLBE_T pIotlbe)
 {
+    pIotlbe->uMagic    = IOMMU_IOTLBE_MAGIC;
+    pIotlbe->uRsvd0    = 0;
     pIotlbe->fIoPerm   = fIoPerm;
-    pIotlbe->uRsvd0    = 0;
-    pIotlbe->uRsvd1    = 0;
+    pIotlbe->cShift    = cShift;
+    pIotlbe->GCPhysSpa = GCPhysSpa;
+}
+
+/**
+ * Updates an IOTLB entry.
+ *
+ * @param   GCPhysSpa   The translated system physical address.
+ * @param   cShift      The number of offset bits in the system physical address.
+ * @param   fIoPerm     The I/O access permissions (IOMMU_IO_PERM_XXX).
+ * @param   pIotlbe     The IOTLB entry to update.
+ */
+static void iommuAmdUpdateIotlbe(RTGCPHYS GCPhysSpa, uint8_t cShift, uint8_t fIoPerm, PIOTLBE_T pIotlbe)
+{
+    Assert(pIotlbe->uMagic == IOMMU_IOTLBE_MAGIC);
+    pIotlbe->fIoPerm   = fIoPerm;
     pIotlbe->cShift    = cShift;
     pIotlbe->GCPhysSpa = GCPhysSpa;
@@ -3886 +3904 @@
         iommuAmdRaiseIoPageFaultEvent(pDevIns, uDevId, pDte->n.u16DomainId, uIova, true /* fPresentOrValid */,
                                       enmOp, kIoPageFaultType_DteTranslationDisabled);
-        iommuAmdInitIotlbe(NIL_RTGCPHYS, 0 /* cShift */,  IOMMU_IO_PERM_NONE, pIotlbe);
+        iommuAmdUpdateIotlbe(NIL_RTGCPHYS, 0 /* cShift */,  IOMMU_IO_PERM_NONE, pIotlbe);
         return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
     }
@@ -3899 +3917 @@
             return VERR_IOMMU_ADDR_ACCESS_DENIED;
         }
-        iommuAmdInitIotlbe(uIova, 0 /* cShift */, fDtePerm, pIotlbe);
+        iommuAmdUpdateIotlbe(uIova, 0 /* cShift */, fDtePerm, pIotlbe);
         return VINF_SUCCESS;
     }
@@ -3910 +3928 @@
          *        I'm just going with this one... */
         /** @todo IOMMU: raise I/O page fault. */
-        iommuAmdInitIotlbe(NIL_RTGCPHYS, 0 /* cShift */,  IOMMU_IO_PERM_NONE, pIotlbe);
+        iommuAmdUpdateIotlbe(NIL_RTGCPHYS, 0 /* cShift */,  IOMMU_IO_PERM_NONE, pIotlbe);
         return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
     }
@@ -3937 +3955 @@
                                       PIOTLBE_T pIotlbe)
 {
+    Assert(pIotlbe->uMagic == IOMMU_IOTLBE_MAGIC);
     PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
 
@@ -3949 +3968 @@
         else
         {
-            iommuAmdInitIotlbe(uIova, 0 /* cShift */, IOMMU_IO_PERM_READ_WRITE, pIotlbe);
+            iommuAmdUpdateIotlbe(uIova, 0 /* cShift */, IOMMU_IO_PERM_READ_WRITE, pIotlbe);
             return VINF_SUCCESS;
         }
@@ -3973 +3992 @@
         else
         {
-            iommuAmdInitIotlbe(uIova, 0 /* cShift */, IOMMU_IO_PERM_READ_WRITE, pIotlbe);
+            iommuAmdUpdateIotlbe(uIova, 0 /* cShift */, IOMMU_IO_PERM_READ_WRITE, pIotlbe);
             return VINF_SUCCESS;
         }