Changeset 84476 in vbox
- Timestamp:
- May 24, 2020 6:17:04 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 138193
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r84247 r84476 10286 10286 * using the 32-bit operand size override. How can that be restarted? See 10287 10287 * weird pseudo code in intel manual. */ 10288 10289 /** NB: At least Windows for Workgroups 3.11 (NDIS.386) and Windows 95 (NDIS.VXD, IOS) 10290 * use LOOP $-2 to implement NdisStallExecution and other CPU stall APIs. Shortcutting 10291 * the loop causes guest crashes, but when logging it's nice to skip a few million 10292 * lines of useless output. */ 10293 #if defined(LOG_ENABLED) 10294 if ((LogIs3Enabled() || LogIs4Enabled()) && (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) == i8Imm)) 10295 switch (pVCpu->iem.s.enmEffAddrMode) 10296 { 10297 case IEMMODE_16BIT: 10298 IEM_MC_BEGIN(0,0); 10299 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0); 10300 IEM_MC_ADVANCE_RIP(); 10301 IEM_MC_END(); 10302 return VINF_SUCCESS; 10303 10304 case IEMMODE_32BIT: 10305 IEM_MC_BEGIN(0,0); 10306 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0); 10307 IEM_MC_ADVANCE_RIP(); 10308 IEM_MC_END(); 10309 return VINF_SUCCESS; 10310 10311 case IEMMODE_64BIT: 10312 IEM_MC_BEGIN(0,0); 10313 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0); 10314 IEM_MC_ADVANCE_RIP(); 10315 IEM_MC_END(); 10316 return VINF_SUCCESS; 10317 10318 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 10319 } 10320 #endif 10321 10288 10322 switch (pVCpu->iem.s.enmEffAddrMode) 10289 10323 { 10290 10324 case IEMMODE_16BIT: 10291 10325 IEM_MC_BEGIN(0,0); 10292 if (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) != i8Imm) /** @todo Harmfull to windows 3.11 for workgroups and such. Make optional. */ 10293 { 10294 IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1); 10295 IEM_MC_IF_CX_IS_NZ() { 10296 IEM_MC_REL_JMP_S8(i8Imm); 10297 } IEM_MC_ELSE() { 10298 IEM_MC_ADVANCE_RIP(); 10299 } IEM_MC_ENDIF(); 10300 } 10301 else 10302 { 10303 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0); 10326 10327 IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1); 10328 IEM_MC_IF_CX_IS_NZ() { 10329 IEM_MC_REL_JMP_S8(i8Imm); 10330 } IEM_MC_ELSE() { 10304 10331 IEM_MC_ADVANCE_RIP(); 10305 } 10332 } IEM_MC_ENDIF(); 10306 10333 IEM_MC_END(); 10307 10334 return VINF_SUCCESS; … … 10309 10336 case IEMMODE_32BIT: 10310 10337 IEM_MC_BEGIN(0,0); 10311 if (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) != i8Imm) 10312 { 10313 IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1); 10314 IEM_MC_IF_ECX_IS_NZ() { 10315 IEM_MC_REL_JMP_S8(i8Imm); 10316 } IEM_MC_ELSE() { 10317 IEM_MC_ADVANCE_RIP(); 10318 } IEM_MC_ENDIF(); 10319 } 10320 else 10321 { 10322 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0); 10338 IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1); 10339 IEM_MC_IF_ECX_IS_NZ() { 10340 IEM_MC_REL_JMP_S8(i8Imm); 10341 } IEM_MC_ELSE() { 10323 10342 IEM_MC_ADVANCE_RIP(); 10324 } 10343 } IEM_MC_ENDIF(); 10325 10344 IEM_MC_END(); 10326 10345 return VINF_SUCCESS; … … 10328 10347 case IEMMODE_64BIT: 10329 10348 IEM_MC_BEGIN(0,0); 10330 if (-(int8_t)IEM_GET_INSTR_LEN(pVCpu) != i8Imm) 10331 { 10332 IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1); 10333 IEM_MC_IF_RCX_IS_NZ() { 10334 IEM_MC_REL_JMP_S8(i8Imm); 10335 } IEM_MC_ELSE() { 10336 IEM_MC_ADVANCE_RIP(); 10337 } IEM_MC_ENDIF(); 10338 } 10339 else 10340 { 10341 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0); 10349 IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1); 10350 IEM_MC_IF_RCX_IS_NZ() { 10351 IEM_MC_REL_JMP_S8(i8Imm); 10352 } IEM_MC_ELSE() { 10342 10353 IEM_MC_ADVANCE_RIP(); 10343 } 10354 } IEM_MC_ENDIF(); 10344 10355 IEM_MC_END(); 10345 10356 return VINF_SUCCESS;
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