Changeset 84652 in vbox
- Timestamp:
- Jun 3, 2020 9:08:30 AM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 138404
- Location:
- trunk
- Files:
-
- 5 edited
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include/VBox/apic.h (modified) (2 diffs)
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include/VBox/vmm/apic.h (modified) (2 diffs)
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src/VBox/VMM/VMMAll/APICAll.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR3/APIC.cpp (modified) (1 diff)
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src/VBox/VMM/include/APICInternal.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/apic.h
r82968 r84652 33 33 34 34 #include <iprt/types.h> 35 35 #include <iprt/x86.h> 36 37 /** @todo These are defines used by CPUM and perhaps some assembly code. Remove 38 * these and use the XAPIC counterpart defines below later. */ 36 39 #define APIC_REG_VERSION 0x0030 37 40 #define APIC_REG_VERSION_GET_VER(u32) (u32 & 0xff) … … 58 61 #define APIC_REG_LVT_MASKED RT_BIT(16) 59 62 63 /** The APIC hardware version number for Pentium 4. */ 64 #define XAPIC_HARDWARE_VERSION_P4 UINT8_C(0x14) 65 /** Maximum number of LVT entries for Pentium 4. */ 66 #define XAPIC_MAX_LVT_ENTRIES_P4 UINT8_C(6) 67 /** Size of the APIC ID bits for Pentium 4. */ 68 #define XAPIC_APIC_ID_BIT_COUNT_P4 UINT8_C(8) 69 70 /** The APIC hardware version number for Pentium 6. */ 71 #define XAPIC_HARDWARE_VERSION_P6 UINT8_C(0x10) 72 /** Maximum number of LVT entries for Pentium 6. */ 73 #define XAPIC_MAX_LVT_ENTRIES_P6 UINT8_C(4) 74 /** Size of the APIC ID bits for Pentium 6. */ 75 #define XAPIC_APIC_ID_BIT_COUNT_P6 UINT8_C(4) 76 77 /** Illegal APIC vector value start. */ 78 #define XAPIC_ILLEGAL_VECTOR_START UINT8_C(0) 79 /** Illegal APIC vector value end (inclusive). */ 80 #define XAPIC_ILLEGAL_VECTOR_END UINT8_C(15) 81 /** Reserved APIC vector value start. */ 82 #define XAPIC_RSVD_VECTOR_START UINT8_C(16) 83 /** Reserved APIC vector value end (inclusive). */ 84 #define XAPIC_RSVD_VECTOR_END UINT8_C(31) 85 86 /** ESR - Send checksum error for Pentium 6. */ 87 # define XAPIC_ESR_SEND_CHKSUM_ERROR_P6 RT_BIT(0) 88 /** ESR - Send accept error for Pentium 6. */ 89 # define XAPIC_ESR_RECV_CHKSUM_ERROR_P6 RT_BIT(1) 90 /** ESR - Send accept error for Pentium 6. */ 91 # define XAPIC_ESR_SEND_ACCEPT_ERROR_P6 RT_BIT(2) 92 /** ESR - Receive accept error for Pentium 6. */ 93 # define XAPIC_ESR_RECV_ACCEPT_ERROR_P6 RT_BIT(3) 94 95 /** ESR - Redirectable IPI. */ 96 #define XAPIC_ESR_REDIRECTABLE_IPI RT_BIT(4) 97 /** ESR - Send accept error. */ 98 #define XAPIC_ESR_SEND_ILLEGAL_VECTOR RT_BIT(5) 99 /** ESR - Send accept error. */ 100 #define XAPIC_ESR_RECV_ILLEGAL_VECTOR RT_BIT(6) 101 /** ESR - Send accept error. */ 102 #define XAPIC_ESR_ILLEGAL_REG_ADDRESS RT_BIT(7) 103 /** ESR - Valid write-only bits. */ 104 #define XAPIC_ESR_WO_VALID UINT32_C(0x0) 105 106 /** TPR - Valid bits. */ 107 #define XAPIC_TPR_VALID UINT32_C(0xff) 108 /** TPR - Task-priority class. */ 109 #define XAPIC_TPR_TP UINT32_C(0xf0) 110 /** TPR - Task-priority subclass. */ 111 #define XAPIC_TPR_TP_SUBCLASS UINT32_C(0x0f) 112 /** TPR - Gets the task-priority class. */ 113 #define XAPIC_TPR_GET_TP(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP) 114 /** TPR - Gets the task-priority subclass. */ 115 #define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS) 116 117 /** PPR - Valid bits. */ 118 #define XAPIC_PPR_VALID UINT32_C(0xff) 119 /** PPR - Processor-priority class. */ 120 #define XAPIC_PPR_PP UINT32_C(0xf0) 121 /** PPR - Processor-priority subclass. */ 122 #define XAPIC_PPR_PP_SUBCLASS UINT32_C(0x0f) 123 /** PPR - Get the processor-priority class. */ 124 #define XAPIC_PPR_GET_PP(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP) 125 /** PPR - Get the processor-priority subclass. */ 126 #define XAPIC_PPR_GET_PP_SUBCLASS(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP_SUBCLASS) 127 128 /** Timer mode - One-shot. */ 129 #define XAPIC_TIMER_MODE_ONESHOT UINT32_C(0) 130 /** Timer mode - Periodic. */ 131 #define XAPIC_TIMER_MODE_PERIODIC UINT32_C(1) 132 /** Timer mode - TSC deadline. */ 133 #define XAPIC_TIMER_MODE_TSC_DEADLINE UINT32_C(2) 134 135 /** LVT - The vector. */ 136 #define XAPIC_LVT_VECTOR UINT32_C(0xff) 137 /** LVT - Gets the vector from an LVT entry. */ 138 #define XAPIC_LVT_GET_VECTOR(a_Lvt) ((a_Lvt) & XAPIC_LVT_VECTOR) 139 /** LVT - The mask. */ 140 #define XAPIC_LVT_MASK RT_BIT(16) 141 /** LVT - Is the LVT masked? */ 142 #define XAPIC_LVT_IS_MASKED(a_Lvt) RT_BOOL((a_Lvt) & XAPIC_LVT_MASK) 143 /** LVT - Timer mode. */ 144 #define XAPIC_LVT_TIMER_MODE RT_BIT(17) 145 /** LVT - Timer TSC-deadline timer mode. */ 146 #define XAPIC_LVT_TIMER_TSCDEADLINE RT_BIT(18) 147 /** LVT - Gets the timer mode. */ 148 #define XAPIC_LVT_GET_TIMER_MODE(a_Lvt) (XAPICTIMERMODE)(((a_Lvt) >> 17) & UINT32_C(3)) 149 /** LVT - Delivery mode. */ 150 #define XAPIC_LVT_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10)) 151 /** LVT - Gets the delivery mode. */ 152 #define XAPIC_LVT_GET_DELIVERY_MODE(a_Lvt) (XAPICDELIVERYMODE)(((a_Lvt) >> 8) & UINT32_C(7)) 153 /** LVT - Delivery status. */ 154 #define XAPIC_LVT_DELIVERY_STATUS RT_BIT(12) 155 /** LVT - Trigger mode. */ 156 #define XAPIC_LVT_TRIGGER_MODE RT_BIT(15) 157 /** LVT - Gets the trigger mode. */ 158 #define XAPIC_LVT_GET_TRIGGER_MODE(a_Lvt) (XAPICTRIGGERMODE)(((a_Lvt) >> 15) & UINT32_C(1)) 159 /** LVT - Remote IRR. */ 160 #define XAPIC_LVT_REMOTE_IRR RT_BIT(14) 161 /** LVT - Gets the Remote IRR. */ 162 #define XAPIC_LVT_GET_REMOTE_IRR(a_Lvt) (((a_Lvt) >> 14) & 1) 163 /** LVT - Interrupt Input Pin Polarity. */ 164 #define XAPIC_LVT_POLARITY RT_BIT(13) 165 /** LVT - Gets the Interrupt Input Pin Polarity. */ 166 #define XAPIC_LVT_GET_POLARITY(a_Lvt) (((a_Lvt) >> 13) & 1) 167 /** LVT - Valid bits common to all LVTs. */ 168 #define XAPIC_LVT_COMMON_VALID (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK) 169 /** LVT CMCI - Valid bits. */ 170 #define XAPIC_LVT_CMCI_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE) 171 /** LVT Timer - Valid bits. */ 172 #define XAPIC_LVT_TIMER_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE) 173 /** LVT Thermal - Valid bits. */ 174 #define XAPIC_LVT_THERMAL_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE) 175 /** LVT Perf - Valid bits. */ 176 #define XAPIC_LVT_PERF_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE) 177 /** LVT LINTx - Valid bits. */ 178 #define XAPIC_LVT_LINT_VALID ( XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \ 179 | XAPIC_LVT_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE) 180 /** LVT Error - Valid bits. */ 181 #define XAPIC_LVT_ERROR_VALID (XAPIC_LVT_COMMON_VALID) 182 183 /** SVR - The vector. */ 184 #define XAPIC_SVR_VECTOR UINT32_C(0xff) 185 /** SVR - APIC Software enable. */ 186 #define XAPIC_SVR_SOFTWARE_ENABLE RT_BIT(8) 187 /** SVR - Supress EOI broadcast. */ 188 #define XAPIC_SVR_SUPRESS_EOI_BROADCAST RT_BIT(12) 189 /** SVR - Valid bits for Pentium 4. */ 190 # define XAPIC_SVR_VALID_P4 (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE) 191 /** @todo SVR - Valid bits for Pentium 6. */ 192 193 /** DFR - Valid bits. */ 194 #define XAPIC_DFR_VALID UINT32_C(0xf0000000) 195 /** DFR - Reserved bits that must always remain set. */ 196 #define XAPIC_DFR_RSVD_MB1 UINT32_C(0x0fffffff) 197 /** DFR - The model. */ 198 #define XAPIC_DFR_MODEL UINT32_C(0xf) 199 /** DFR - Gets the destination model. */ 200 #define XAPIC_DFR_GET_MODEL(a_uReg) (((a_uReg) >> 28) & XAPIC_DFR_MODEL) 201 202 /** LDR - Valid bits. */ 203 #define XAPIC_LDR_VALID UINT32_C(0xff000000) 204 /** LDR - Cluster ID mask (x2APIC). */ 205 #define X2APIC_LDR_CLUSTER_ID UINT32_C(0xffff0000) 206 /** LDR - Mask of the LDR cluster ID (x2APIC). */ 207 #define X2APIC_LDR_GET_CLUSTER_ID(a_uReg) ((a_uReg) & X2APIC_LDR_CLUSTER_ID) 208 /** LDR - Mask of the LDR logical ID (x2APIC). */ 209 #define X2APIC_LDR_LOGICAL_ID UINT32_C(0x0000ffff) 210 211 /** LDR - Flat mode logical ID mask. */ 212 #define XAPIC_LDR_FLAT_LOGICAL_ID UINT32_C(0xff) 213 /** LDR - Clustered mode cluster ID mask. */ 214 #define XAPIC_LDR_CLUSTERED_CLUSTER_ID UINT32_C(0xf0) 215 /** LDR - Clustered mode logical ID mask. */ 216 #define XAPIC_LDR_CLUSTERED_LOGICAL_ID UINT32_C(0x0f) 217 /** LDR - Gets the clustered mode cluster ID. */ 218 #define XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(a_uReg) ((a_uReg) & XAPIC_LDR_CLUSTERED_CLUSTER_ID) 219 220 221 /** EOI - Valid write-only bits. */ 222 #define XAPIC_EOI_WO_VALID UINT32_C(0x0) 223 /** Timer ICR - Valid bits. */ 224 #define XAPIC_TIMER_ICR_VALID UINT32_C(0xffffffff) 225 /** Timer DCR - Valid bits. */ 226 #define XAPIC_TIMER_DCR_VALID (RT_BIT(0) | RT_BIT(1) | RT_BIT(3)) 227 228 /** Self IPI - Valid bits. */ 229 #define XAPIC_SELF_IPI_VALID UINT32_C(0xff) 230 /** Self IPI - The vector. */ 231 #define XAPIC_SELF_IPI_VECTOR UINT32_C(0xff) 232 /** Self IPI - Gets the vector. */ 233 #define XAPIC_SELF_IPI_GET_VECTOR(a_uReg) ((a_uReg) & XAPIC_SELF_IPI_VECTOR) 234 235 /** ICR Low - The Vector. */ 236 #define XAPIC_ICR_LO_VECTOR UINT32_C(0xff) 237 /** ICR Low - Gets the vector. */ 238 #define XAPIC_ICR_LO_GET_VECTOR(a_uIcr) ((a_uIcr) & XAPIC_ICR_LO_VECTOR) 239 /** ICR Low - The delivery mode. */ 240 #define XAPIC_ICR_LO_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10)) 241 /** ICR Low - The destination mode. */ 242 #define XAPIC_ICR_LO_DEST_MODE RT_BIT(11) 243 /** ICR Low - The delivery status. */ 244 #define XAPIC_ICR_LO_DELIVERY_STATUS RT_BIT(12) 245 /** ICR Low - The level. */ 246 #define XAPIC_ICR_LO_LEVEL RT_BIT(14) 247 /** ICR Low - The trigger mode. */ 248 #define XAPIC_ICR_TRIGGER_MODE RT_BIT(15) 249 /** ICR Low - The destination shorthand. */ 250 #define XAPIC_ICR_LO_DEST_SHORTHAND (RT_BIT(18) | RT_BIT(19)) 251 /** ICR Low - Valid write bits. */ 252 #define XAPIC_ICR_LO_WR_VALID ( XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \ 253 | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND) 254 255 /** ICR High - The destination field. */ 256 #define XAPIC_ICR_HI_DEST UINT32_C(0xff000000) 257 /** ICR High - Get the destination field. */ 258 #define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi) (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST) 259 /** ICR High - Valid write bits in xAPIC mode. */ 260 #define XAPIC_ICR_HI_WR_VALID XAPIC_ICR_HI_DEST 261 262 /** APIC ID broadcast mask - x2APIC mode. */ 263 #define X2APIC_ID_BROADCAST_MASK UINT32_C(0xffffffff) 264 /** APIC ID broadcast mask - xAPIC mode for Pentium 4. */ 265 # define XAPIC_ID_BROADCAST_MASK_P4 UINT32_C(0xff) 266 /** @todo Broadcast mask for Pentium 6. */ 267 268 /** Get an xAPIC page offset for an x2APIC MSR value. */ 269 #define X2APIC_GET_XAPIC_OFF(a_uMsr) ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0)) 270 /** Get an x2APIC MSR for an xAPIC page offset. */ 271 #define XAPIC_GET_X2APIC_MSR(a_offReg) ((((a_offReg) & UINT32_C(0xff0)) >> 4) | MSR_IA32_X2APIC_START) 272 273 /** @name xAPIC and x2APIC register offsets. 274 * See Intel spec. 10.4.1 "The Local APIC Block Diagram". 275 * @{ */ 276 /** Offset of APIC ID Register. */ 277 #define XAPIC_OFF_ID 0x020 278 /** Offset of APIC Version Register. */ 279 #define XAPIC_OFF_VERSION 0x030 280 /** Offset of Task Priority Register. */ 281 #define XAPIC_OFF_TPR 0x080 282 /** Offset of Arbitrartion Priority register. */ 283 #define XAPIC_OFF_APR 0x090 284 /** Offset of Processor Priority register. */ 285 #define XAPIC_OFF_PPR 0x0A0 286 /** Offset of End Of Interrupt register. */ 287 #define XAPIC_OFF_EOI 0x0B0 288 /** Offset of Remote Read Register. */ 289 #define XAPIC_OFF_RRD 0x0C0 290 /** Offset of Logical Destination Register. */ 291 #define XAPIC_OFF_LDR 0x0D0 292 /** Offset of Destination Format Register. */ 293 #define XAPIC_OFF_DFR 0x0E0 294 /** Offset of Spurious Interrupt Vector Register. */ 295 #define XAPIC_OFF_SVR 0x0F0 296 /** Offset of In-service Register (bits 31:0). */ 297 #define XAPIC_OFF_ISR0 0x100 298 /** Offset of In-service Register (bits 63:32). */ 299 #define XAPIC_OFF_ISR1 0x110 300 /** Offset of In-service Register (bits 95:64). */ 301 #define XAPIC_OFF_ISR2 0x120 302 /** Offset of In-service Register (bits 127:96). */ 303 #define XAPIC_OFF_ISR3 0x130 304 /** Offset of In-service Register (bits 159:128). */ 305 #define XAPIC_OFF_ISR4 0x140 306 /** Offset of In-service Register (bits 191:160). */ 307 #define XAPIC_OFF_ISR5 0x150 308 /** Offset of In-service Register (bits 223:192). */ 309 #define XAPIC_OFF_ISR6 0x160 310 /** Offset of In-service Register (bits 255:224). */ 311 #define XAPIC_OFF_ISR7 0x170 312 /** Offset of Trigger Mode Register (bits 31:0). */ 313 #define XAPIC_OFF_TMR0 0x180 314 /** Offset of Trigger Mode Register (bits 63:32). */ 315 #define XAPIC_OFF_TMR1 0x190 316 /** Offset of Trigger Mode Register (bits 95:64). */ 317 #define XAPIC_OFF_TMR2 0x1A0 318 /** Offset of Trigger Mode Register (bits 127:96). */ 319 #define XAPIC_OFF_TMR3 0x1B0 320 /** Offset of Trigger Mode Register (bits 159:128). */ 321 #define XAPIC_OFF_TMR4 0x1C0 322 /** Offset of Trigger Mode Register (bits 191:160). */ 323 #define XAPIC_OFF_TMR5 0x1D0 324 /** Offset of Trigger Mode Register (bits 223:192). */ 325 #define XAPIC_OFF_TMR6 0x1E0 326 /** Offset of Trigger Mode Register (bits 255:224). */ 327 #define XAPIC_OFF_TMR7 0x1F0 328 /** Offset of Interrupt Request Register (bits 31:0). */ 329 #define XAPIC_OFF_IRR0 0x200 330 /** Offset of Interrupt Request Register (bits 63:32). */ 331 #define XAPIC_OFF_IRR1 0x210 332 /** Offset of Interrupt Request Register (bits 95:64). */ 333 #define XAPIC_OFF_IRR2 0x220 334 /** Offset of Interrupt Request Register (bits 127:96). */ 335 #define XAPIC_OFF_IRR3 0x230 336 /** Offset of Interrupt Request Register (bits 159:128). */ 337 #define XAPIC_OFF_IRR4 0x240 338 /** Offset of Interrupt Request Register (bits 191:160). */ 339 #define XAPIC_OFF_IRR5 0x250 340 /** Offset of Interrupt Request Register (bits 223:192). */ 341 #define XAPIC_OFF_IRR6 0x260 342 /** Offset of Interrupt Request Register (bits 255:224). */ 343 #define XAPIC_OFF_IRR7 0x270 344 /** Offset of Error Status Register. */ 345 #define XAPIC_OFF_ESR 0x280 346 /** Offset of LVT CMCI Register. */ 347 #define XAPIC_OFF_LVT_CMCI 0x2F0 348 /** Offset of Interrupt Command Register - Lo. */ 349 #define XAPIC_OFF_ICR_LO 0x300 350 /** Offset of Interrupt Command Register - Hi. */ 351 #define XAPIC_OFF_ICR_HI 0x310 352 /** Offset of LVT Timer Register. */ 353 #define XAPIC_OFF_LVT_TIMER 0x320 354 /** Offset of LVT Thermal Sensor Register. */ 355 #define XAPIC_OFF_LVT_THERMAL 0x330 356 /** Offset of LVT Performance Counter Register. */ 357 #define XAPIC_OFF_LVT_PERF 0x340 358 /** Offset of LVT LINT0 Register. */ 359 #define XAPIC_OFF_LVT_LINT0 0x350 360 /** Offset of LVT LINT1 Register. */ 361 #define XAPIC_OFF_LVT_LINT1 0x360 362 /** Offset of LVT Error Register . */ 363 #define XAPIC_OFF_LVT_ERROR 0x370 364 /** Offset of Timer Initial Count Register. */ 365 #define XAPIC_OFF_TIMER_ICR 0x380 366 /** Offset of Timer Current Count Register. */ 367 #define XAPIC_OFF_TIMER_CCR 0x390 368 /** Offset of Timer Divide Configuration Register. */ 369 #define XAPIC_OFF_TIMER_DCR 0x3E0 370 /** Offset of Self-IPI Register (x2APIC only). */ 371 #define X2APIC_OFF_SELF_IPI 0x3F0 372 373 /** Offset of LVT range start. */ 374 #define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER 375 /** Offset of LVT range end (inclusive). */ 376 #define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR 377 /** Offset of LVT extended range start. */ 378 #define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI 379 /** Offset of LVT extended range end (inclusive). */ 380 #define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI 381 /** Offset of the last register (incl. reserved) in the xAPIC/x2APIC range. */ 382 #define XAPIC_OFF_END 0x3F0 383 /** @} */ 384 385 /** @name xAPIC Destination Format Register bits. 386 * See Intel spec. 10.6.2.2 "Logical Destination Mode". 387 * @{ */ 388 typedef enum XAPICDESTFORMAT 389 { 390 XAPICDESTFORMAT_FLAT = 0xf, 391 XAPICDESTFORMAT_CLUSTER = 0 392 } XAPICDESTFORMAT; 393 /** @} */ 394 395 /** @name xAPIC Timer Mode bits. 396 * See Intel spec. 10.5.1 "Local Vector Table". 397 * @{ */ 398 typedef enum XAPICTIMERMODE 399 { 400 XAPICTIMERMODE_ONESHOT = XAPIC_TIMER_MODE_ONESHOT, 401 XAPICTIMERMODE_PERIODIC = XAPIC_TIMER_MODE_PERIODIC, 402 XAPICTIMERMODE_TSC_DEADLINE = XAPIC_TIMER_MODE_TSC_DEADLINE 403 } XAPICTIMERMODE; 404 /** @} */ 405 406 /** @name xAPIC Interrupt Command Register bits. 407 * See Intel spec. 10.6.1 "Interrupt Command Register (ICR)". 408 * See Intel spec. 10.5.1 "Local Vector Table". 409 * @{ */ 410 /** 411 * xAPIC destination shorthand. 412 */ 413 typedef enum XAPICDESTSHORTHAND 414 { 415 XAPICDESTSHORTHAND_NONE = 0, 416 XAPICDESTSHORTHAND_SELF, 417 XAPIDDESTSHORTHAND_ALL_INCL_SELF, 418 XAPICDESTSHORTHAND_ALL_EXCL_SELF 419 } XAPICDESTSHORTHAND; 420 421 /** 422 * xAPIC INIT level de-assert delivery mode. 423 */ 424 typedef enum XAPICINITLEVEL 425 { 426 XAPICINITLEVEL_DEASSERT = 0, 427 XAPICINITLEVEL_ASSERT 428 } XAPICLEVEL; 429 430 /** 431 * xAPIC destination mode. 432 */ 433 typedef enum XAPICDESTMODE 434 { 435 XAPICDESTMODE_PHYSICAL = 0, 436 XAPICDESTMODE_LOGICAL 437 } XAPICDESTMODE; 438 439 /** 440 * xAPIC delivery mode type. 441 */ 442 typedef enum XAPICDELIVERYMODE 443 { 444 XAPICDELIVERYMODE_FIXED = 0, 445 XAPICDELIVERYMODE_LOWEST_PRIO = 1, 446 XAPICDELIVERYMODE_SMI = 2, 447 XAPICDELIVERYMODE_NMI = 4, 448 XAPICDELIVERYMODE_INIT = 5, 449 XAPICDELIVERYMODE_STARTUP = 6, 450 XAPICDELIVERYMODE_EXTINT = 7 451 } XAPICDELIVERYMODE; 452 453 /** 454 * xAPIC trigger mode. 455 */ 456 typedef enum XAPICTRIGGERMODE 457 { 458 XAPICTRIGGERMODE_EDGE = 0, 459 XAPICTRIGGERMODE_LEVEL 460 } XAPICTRIGGERMODE; 461 /** @} */ 462 463 60 464 DECLINLINE(uint32_t) ApicRegRead(void *pvBase, uint32_t offReg) 61 465 { -
trunk/include/VBox/vmm/apic.h
r82968 r84652 31 31 32 32 #include <VBox/types.h> 33 #include <VBox/apic.h> 33 34 struct PDMDEVREGCB; 34 35 … … 37 38 * @{ 38 39 */ 39 40 /** Offset of APIC ID Register. */41 #define XAPIC_OFF_ID 0x02042 /** Offset of APIC Version Register. */43 #define XAPIC_OFF_VERSION 0x03044 /** Offset of Task Priority Register. */45 #define XAPIC_OFF_TPR 0x08046 /** Offset of Arbitrartion Priority register. */47 #define XAPIC_OFF_APR 0x09048 /** Offset of Processor Priority register. */49 #define XAPIC_OFF_PPR 0x0A050 /** Offset of End Of Interrupt register. */51 #define XAPIC_OFF_EOI 0x0B052 /** Offset of Remote Read Register. */53 #define XAPIC_OFF_RRD 0x0C054 /** Offset of Logical Destination Register. */55 #define XAPIC_OFF_LDR 0x0D056 /** Offset of Destination Format Register. */57 #define XAPIC_OFF_DFR 0x0E058 /** Offset of Spurious Interrupt Vector Register. */59 #define XAPIC_OFF_SVR 0x0F060 /** Offset of In-service Register (bits 31:0). */61 #define XAPIC_OFF_ISR0 0x10062 /** Offset of In-service Register (bits 63:32). */63 #define XAPIC_OFF_ISR1 0x11064 /** Offset of In-service Register (bits 95:64). */65 #define XAPIC_OFF_ISR2 0x12066 /** Offset of In-service Register (bits 127:96). */67 #define XAPIC_OFF_ISR3 0x13068 /** Offset of In-service Register (bits 159:128). */69 #define XAPIC_OFF_ISR4 0x14070 /** Offset of In-service Register (bits 191:160). */71 #define XAPIC_OFF_ISR5 0x15072 /** Offset of In-service Register (bits 223:192). */73 #define XAPIC_OFF_ISR6 0x16074 /** Offset of In-service Register (bits 255:224). */75 #define XAPIC_OFF_ISR7 0x17076 /** Offset of Trigger Mode Register (bits 31:0). */77 #define XAPIC_OFF_TMR0 0x18078 /** Offset of Trigger Mode Register (bits 63:32). */79 #define XAPIC_OFF_TMR1 0x19080 /** Offset of Trigger Mode Register (bits 95:64). */81 #define XAPIC_OFF_TMR2 0x1A082 /** Offset of Trigger Mode Register (bits 127:96). */83 #define XAPIC_OFF_TMR3 0x1B084 /** Offset of Trigger Mode Register (bits 159:128). */85 #define XAPIC_OFF_TMR4 0x1C086 /** Offset of Trigger Mode Register (bits 191:160). */87 #define XAPIC_OFF_TMR5 0x1D088 /** Offset of Trigger Mode Register (bits 223:192). */89 #define XAPIC_OFF_TMR6 0x1E090 /** Offset of Trigger Mode Register (bits 255:224). */91 #define XAPIC_OFF_TMR7 0x1F092 /** Offset of Interrupt Request Register (bits 31:0). */93 #define XAPIC_OFF_IRR0 0x20094 /** Offset of Interrupt Request Register (bits 63:32). */95 #define XAPIC_OFF_IRR1 0x21096 /** Offset of Interrupt Request Register (bits 95:64). */97 #define XAPIC_OFF_IRR2 0x22098 /** Offset of Interrupt Request Register (bits 127:96). */99 #define XAPIC_OFF_IRR3 0x230100 /** Offset of Interrupt Request Register (bits 159:128). */101 #define XAPIC_OFF_IRR4 0x240102 /** Offset of Interrupt Request Register (bits 191:160). */103 #define XAPIC_OFF_IRR5 0x250104 /** Offset of Interrupt Request Register (bits 223:192). */105 #define XAPIC_OFF_IRR6 0x260106 /** Offset of Interrupt Request Register (bits 255:224). */107 #define XAPIC_OFF_IRR7 0x270108 /** Offset of Error Status Register. */109 #define XAPIC_OFF_ESR 0x280110 /** Offset of LVT CMCI Register. */111 #define XAPIC_OFF_LVT_CMCI 0x2F0112 /** Offset of Interrupt Command Register - Lo. */113 #define XAPIC_OFF_ICR_LO 0x300114 /** Offset of Interrupt Command Register - Hi. */115 #define XAPIC_OFF_ICR_HI 0x310116 /** Offset of LVT Timer Register. */117 #define XAPIC_OFF_LVT_TIMER 0x320118 /** Offset of LVT Thermal Sensor Register. */119 #define XAPIC_OFF_LVT_THERMAL 0x330120 /** Offset of LVT Performance Counter Register. */121 #define XAPIC_OFF_LVT_PERF 0x340122 /** Offset of LVT LINT0 Register. */123 #define XAPIC_OFF_LVT_LINT0 0x350124 /** Offset of LVT LINT1 Register. */125 #define XAPIC_OFF_LVT_LINT1 0x360126 /** Offset of LVT Error Register . */127 #define XAPIC_OFF_LVT_ERROR 0x370128 /** Offset of Timer Initial Count Register. */129 #define XAPIC_OFF_TIMER_ICR 0x380130 /** Offset of Timer Current Count Register. */131 #define XAPIC_OFF_TIMER_CCR 0x390132 /** Offset of Timer Divide Configuration Register. */133 #define XAPIC_OFF_TIMER_DCR 0x3E0134 /** Offset of Self-IPI Register (x2APIC only). */135 #define X2APIC_OFF_SELF_IPI 0x3F0136 137 /** Offset of LVT range start. */138 #define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER139 /** Offset of LVT range end (inclusive). */140 #define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR141 /** Offset of LVT extended range start. */142 #define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI143 /** Offset of LVT extended range end (inclusive). */144 #define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI145 /** Offset of the last register (incl. reserved) in the xAPIC/x2APIC range. */146 #define XAPIC_OFF_END 0x3F0147 148 /**149 * xAPIC trigger mode.150 */151 typedef enum XAPICTRIGGERMODE152 {153 XAPICTRIGGERMODE_EDGE = 0,154 XAPICTRIGGERMODE_LEVEL155 } XAPICTRIGGERMODE;156 40 157 41 RT_C_DECLS_BEGIN -
trunk/src/VBox/VMM/VMMAll/APICAll.cpp
r82968 r84652 22 22 #define LOG_GROUP LOG_GROUP_DEV_APIC 23 23 #include "APICInternal.h" 24 #include <VBox/vmm/apic.h> 24 25 #include <VBox/vmm/pdmdev.h> 25 26 #include <VBox/vmm/pdmapi.h> -
trunk/src/VBox/VMM/VMMR3/APIC.cpp
r82968 r84652 23 23 #include <VBox/log.h> 24 24 #include "APICInternal.h" 25 #include <VBox/vmm/apic.h> 25 26 #include <VBox/vmm/cpum.h> 26 27 #include <VBox/vmm/hm.h> -
trunk/src/VBox/VMM/include/APICInternal.h
r82968 r84652 22 22 #endif 23 23 24 #include <VBox/apic.h> 24 25 #include <VBox/sup.h> 25 #include <VBox/vmm/pdmdev.h> /* before apic.h! */ 26 #include <VBox/vmm/apic.h> 26 #include <VBox/vmm/pdmdev.h> 27 27 28 28 /** @defgroup grp_apic_int Internal … … 32 32 */ 33 33 34 /** The APIC hardware version number for Pentium 4. */35 #define XAPIC_HARDWARE_VERSION_P4 UINT8_C(0x14)36 /** Maximum number of LVT entries for Pentium 4. */37 #define XAPIC_MAX_LVT_ENTRIES_P4 UINT8_C(6)38 /** Size of the APIC ID bits for Pentium 4. */39 #define XAPIC_APIC_ID_BIT_COUNT_P4 UINT8_C(8)40 41 /** The APIC hardware version number for Pentium 6. */42 #define XAPIC_HARDWARE_VERSION_P6 UINT8_C(0x10)43 /** Maximum number of LVT entries for Pentium 6. */44 #define XAPIC_MAX_LVT_ENTRIES_P6 UINT8_C(4)45 /** Size of the APIC ID bits for Pentium 6. */46 #define XAPIC_APIC_ID_BIT_COUNT_P6 UINT8_C(4)47 48 34 /** The APIC hardware version we are emulating. */ 49 35 #define XAPIC_HARDWARE_VERSION XAPIC_HARDWARE_VERSION_P4 36 37 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4 38 #define XAPIC_SVR_VALID XAPIC_SVR_VALID_P4 39 #define XAPIC_ID_BROADCAST_MASK XAPIC_ID_BROADCAST_MASK_P4 40 #else 41 # error "Implement Pentium and P6 family APIC architectures" 42 #endif 50 43 51 44 #define VMCPU_TO_XAPICPAGE(a_pVCpu) ((PXAPICPAGE)(CTX_SUFF((a_pVCpu)->apic.s.pvApicPage))) … … 67 60 #define APICCPU_TO_CXAPICPAGE(a_ApicCpu) ((PCXAPICPAGE)(CTX_SUFF((a_ApicCpu)->pvApicPage))) 68 61 62 /** Vector offset in an APIC 256-bit sparse register. */ 63 #define XAPIC_REG256_VECTOR_OFF(a_Vector) (((a_Vector) & UINT32_C(0xe0)) >> 1) 64 /** Bit position at offset in an APIC 256-bit sparse register. */ 65 #define XAPIC_REG256_VECTOR_BIT(a_Vector) ((a_Vector) & UINT32_C(0x1f)) 66 67 /** Maximum valid offset for a register (16-byte aligned, 4 byte wide access). */ 68 #define XAPIC_OFF_MAX_VALID (sizeof(XAPICPAGE) - 4 * sizeof(uint32_t)) 69 69 70 /** Whether the APIC is in X2APIC mode or not. */ 70 71 #define XAPIC_IN_X2APIC_MODE(a_pVCpu) ( ( ((a_pVCpu)->apic.s.uApicBaseMsr) \ 71 72 & (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD)) \ 72 73 == (MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD) ) 73 74 /** Get an xAPIC page offset for an x2APIC MSR value. */75 #define X2APIC_GET_XAPIC_OFF(a_uMsr) ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & UINT32_C(0xff0))76 /** Get an x2APIC MSR for an xAPIC page offset. */77 #define XAPIC_GET_X2APIC_MSR(a_offReg) ((((a_offReg) & UINT32_C(0xff0)) >> 4) | MSR_IA32_X2APIC_START)78 79 /** Illegal APIC vector value start. */80 #define XAPIC_ILLEGAL_VECTOR_START UINT8_C(0)81 /** Illegal APIC vector value end (inclusive). */82 #define XAPIC_ILLEGAL_VECTOR_END UINT8_C(15)83 /** Reserved APIC vector value start. */84 #define XAPIC_RSVD_VECTOR_START UINT8_C(16)85 /** Reserved APIC vector value end (inclusive). */86 #define XAPIC_RSVD_VECTOR_END UINT8_C(31)87 88 /** Vector offset in an APIC 256-bit sparse register. */89 #define XAPIC_REG256_VECTOR_OFF(a_Vector) (((a_Vector) & UINT32_C(0xe0)) >> 1)90 /** Bit position at offset in an APIC 256-bit sparse register. */91 #define XAPIC_REG256_VECTOR_BIT(a_Vector) ((a_Vector) & UINT32_C(0x1f))92 93 /** Maximum valid offset for a register (16-byte aligned, 4 byte wide access). */94 #define XAPIC_OFF_MAX_VALID (sizeof(XAPICPAGE) - 4 * sizeof(uint32_t))95 96 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P697 /** ESR - Send checksum error. */98 # define XAPIC_ESR_SEND_CHKSUM_ERROR RT_BIT(0)99 /** ESR - Send accept error. */100 # define XAPIC_ESR_RECV_CHKSUM_ERROR RT_BIT(1)101 /** ESR - Send accept error. */102 # define XAPIC_ESR_SEND_ACCEPT_ERROR RT_BIT(2)103 /** ESR - Receive accept error. */104 # define XAPIC_ESR_RECV_ACCEPT_ERROR RT_BIT(3)105 #endif106 /** ESR - Redirectable IPI. */107 #define XAPIC_ESR_REDIRECTABLE_IPI RT_BIT(4)108 /** ESR - Send accept error. */109 #define XAPIC_ESR_SEND_ILLEGAL_VECTOR RT_BIT(5)110 /** ESR - Send accept error. */111 #define XAPIC_ESR_RECV_ILLEGAL_VECTOR RT_BIT(6)112 /** ESR - Send accept error. */113 #define XAPIC_ESR_ILLEGAL_REG_ADDRESS RT_BIT(7)114 /** ESR - Valid write-only bits. */115 #define XAPIC_ESR_WO_VALID UINT32_C(0x0)116 117 /** TPR - Valid bits. */118 #define XAPIC_TPR_VALID UINT32_C(0xff)119 /** TPR - Task-priority class. */120 #define XAPIC_TPR_TP UINT32_C(0xf0)121 /** TPR - Task-priority subclass. */122 #define XAPIC_TPR_TP_SUBCLASS UINT32_C(0x0f)123 /** TPR - Gets the task-priority class. */124 #define XAPIC_TPR_GET_TP(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP)125 /** TPR - Gets the task-priority subclass. */126 #define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS)127 128 /** PPR - Valid bits. */129 #define XAPIC_PPR_VALID UINT32_C(0xff)130 /** PPR - Processor-priority class. */131 #define XAPIC_PPR_PP UINT32_C(0xf0)132 /** PPR - Processor-priority subclass. */133 #define XAPIC_PPR_PP_SUBCLASS UINT32_C(0x0f)134 /** PPR - Get the processor-priority class. */135 #define XAPIC_PPR_GET_PP(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP)136 /** PPR - Get the processor-priority subclass. */137 #define XAPIC_PPR_GET_PP_SUBCLASS(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP_SUBCLASS)138 139 /** Timer mode - One-shot. */140 #define XAPIC_TIMER_MODE_ONESHOT UINT32_C(0)141 /** Timer mode - Periodic. */142 #define XAPIC_TIMER_MODE_PERIODIC UINT32_C(1)143 /** Timer mode - TSC deadline. */144 #define XAPIC_TIMER_MODE_TSC_DEADLINE UINT32_C(2)145 146 /** LVT - The vector. */147 #define XAPIC_LVT_VECTOR UINT32_C(0xff)148 /** LVT - Gets the vector from an LVT entry. */149 #define XAPIC_LVT_GET_VECTOR(a_Lvt) ((a_Lvt) & XAPIC_LVT_VECTOR)150 /** LVT - The mask. */151 #define XAPIC_LVT_MASK RT_BIT(16)152 /** LVT - Is the LVT masked? */153 #define XAPIC_LVT_IS_MASKED(a_Lvt) RT_BOOL((a_Lvt) & XAPIC_LVT_MASK)154 /** LVT - Timer mode. */155 #define XAPIC_LVT_TIMER_MODE RT_BIT(17)156 /** LVT - Timer TSC-deadline timer mode. */157 #define XAPIC_LVT_TIMER_TSCDEADLINE RT_BIT(18)158 /** LVT - Gets the timer mode. */159 #define XAPIC_LVT_GET_TIMER_MODE(a_Lvt) (XAPICTIMERMODE)(((a_Lvt) >> 17) & UINT32_C(3))160 /** LVT - Delivery mode. */161 #define XAPIC_LVT_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))162 /** LVT - Gets the delivery mode. */163 #define XAPIC_LVT_GET_DELIVERY_MODE(a_Lvt) (XAPICDELIVERYMODE)(((a_Lvt) >> 8) & UINT32_C(7))164 /** LVT - Delivery status. */165 #define XAPIC_LVT_DELIVERY_STATUS RT_BIT(12)166 /** LVT - Trigger mode. */167 #define XAPIC_LVT_TRIGGER_MODE RT_BIT(15)168 /** LVT - Gets the trigger mode. */169 #define XAPIC_LVT_GET_TRIGGER_MODE(a_Lvt) (XAPICTRIGGERMODE)(((a_Lvt) >> 15) & UINT32_C(1))170 /** LVT - Remote IRR. */171 #define XAPIC_LVT_REMOTE_IRR RT_BIT(14)172 /** LVT - Gets the Remote IRR. */173 #define XAPIC_LVT_GET_REMOTE_IRR(a_Lvt) (((a_Lvt) >> 14) & 1)174 /** LVT - Interrupt Input Pin Polarity. */175 #define XAPIC_LVT_POLARITY RT_BIT(13)176 /** LVT - Gets the Interrupt Input Pin Polarity. */177 #define XAPIC_LVT_GET_POLARITY(a_Lvt) (((a_Lvt) >> 13) & 1)178 /** LVT - Valid bits common to all LVTs. */179 #define XAPIC_LVT_COMMON_VALID (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)180 /** LVT CMCI - Valid bits. */181 #define XAPIC_LVT_CMCI_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)182 /** LVT Timer - Valid bits. */183 #define XAPIC_LVT_TIMER_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)184 /** LVT Thermal - Valid bits. */185 #define XAPIC_LVT_THERMAL_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)186 /** LVT Perf - Valid bits. */187 #define XAPIC_LVT_PERF_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)188 /** LVT LINTx - Valid bits. */189 #define XAPIC_LVT_LINT_VALID ( XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \190 | XAPIC_LVT_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE)191 /** LVT Error - Valid bits. */192 #define XAPIC_LVT_ERROR_VALID (XAPIC_LVT_COMMON_VALID)193 194 /** SVR - The vector. */195 #define XAPIC_SVR_VECTOR UINT32_C(0xff)196 /** SVR - APIC Software enable. */197 #define XAPIC_SVR_SOFTWARE_ENABLE RT_BIT(8)198 /** SVR - Supress EOI broadcast. */199 #define XAPIC_SVR_SUPRESS_EOI_BROADCAST RT_BIT(12)200 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4201 /** SVR - Valid bits. */202 # define XAPIC_SVR_VALID (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)203 #else204 # error "Implement Pentium and P6 family APIC architectures"205 #endif206 207 /** DFR - Valid bits. */208 #define XAPIC_DFR_VALID UINT32_C(0xf0000000)209 /** DFR - Reserved bits that must always remain set. */210 #define XAPIC_DFR_RSVD_MB1 UINT32_C(0x0fffffff)211 /** DFR - The model. */212 #define XAPIC_DFR_MODEL UINT32_C(0xf)213 /** DFR - Gets the destination model. */214 #define XAPIC_DFR_GET_MODEL(a_uReg) (((a_uReg) >> 28) & XAPIC_DFR_MODEL)215 216 /** LDR - Valid bits. */217 #define XAPIC_LDR_VALID UINT32_C(0xff000000)218 /** LDR - Cluster ID mask (x2APIC). */219 #define X2APIC_LDR_CLUSTER_ID UINT32_C(0xffff0000)220 /** LDR - Mask of the LDR cluster ID (x2APIC). */221 #define X2APIC_LDR_GET_CLUSTER_ID(a_uReg) ((a_uReg) & X2APIC_LDR_CLUSTER_ID)222 /** LDR - Mask of the LDR logical ID (x2APIC). */223 #define X2APIC_LDR_LOGICAL_ID UINT32_C(0x0000ffff)224 225 /** LDR - Flat mode logical ID mask. */226 #define XAPIC_LDR_FLAT_LOGICAL_ID UINT32_C(0xff)227 /** LDR - Clustered mode cluster ID mask. */228 #define XAPIC_LDR_CLUSTERED_CLUSTER_ID UINT32_C(0xf0)229 /** LDR - Clustered mode logical ID mask. */230 #define XAPIC_LDR_CLUSTERED_LOGICAL_ID UINT32_C(0x0f)231 /** LDR - Gets the clustered mode cluster ID. */232 #define XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(a_uReg) ((a_uReg) & XAPIC_LDR_CLUSTERED_CLUSTER_ID)233 234 235 /** EOI - Valid write-only bits. */236 #define XAPIC_EOI_WO_VALID UINT32_C(0x0)237 /** Timer ICR - Valid bits. */238 #define XAPIC_TIMER_ICR_VALID UINT32_C(0xffffffff)239 /** Timer DCR - Valid bits. */240 #define XAPIC_TIMER_DCR_VALID (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))241 242 /** Self IPI - Valid bits. */243 #define XAPIC_SELF_IPI_VALID UINT32_C(0xff)244 /** Self IPI - The vector. */245 #define XAPIC_SELF_IPI_VECTOR UINT32_C(0xff)246 /** Self IPI - Gets the vector. */247 #define XAPIC_SELF_IPI_GET_VECTOR(a_uReg) ((a_uReg) & XAPIC_SELF_IPI_VECTOR)248 249 /** ICR Low - The Vector. */250 #define XAPIC_ICR_LO_VECTOR UINT32_C(0xff)251 /** ICR Low - Gets the vector. */252 #define XAPIC_ICR_LO_GET_VECTOR(a_uIcr) ((a_uIcr) & XAPIC_ICR_LO_VECTOR)253 /** ICR Low - The delivery mode. */254 #define XAPIC_ICR_LO_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))255 /** ICR Low - The destination mode. */256 #define XAPIC_ICR_LO_DEST_MODE RT_BIT(11)257 /** ICR Low - The delivery status. */258 #define XAPIC_ICR_LO_DELIVERY_STATUS RT_BIT(12)259 /** ICR Low - The level. */260 #define XAPIC_ICR_LO_LEVEL RT_BIT(14)261 /** ICR Low - The trigger mode. */262 #define XAPIC_ICR_TRIGGER_MODE RT_BIT(15)263 /** ICR Low - The destination shorthand. */264 #define XAPIC_ICR_LO_DEST_SHORTHAND (RT_BIT(18) | RT_BIT(19))265 /** ICR Low - Valid write bits. */266 #define XAPIC_ICR_LO_WR_VALID ( XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \267 | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND)268 269 /** ICR High - The destination field. */270 #define XAPIC_ICR_HI_DEST UINT32_C(0xff000000)271 /** ICR High - Get the destination field. */272 #define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi) (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST)273 /** ICR High - Valid write bits in xAPIC mode. */274 #define XAPIC_ICR_HI_WR_VALID XAPIC_ICR_HI_DEST275 276 /** APIC ID broadcast mask - x2APIC mode. */277 #define X2APIC_ID_BROADCAST_MASK UINT32_C(0xffffffff)278 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4279 /** APIC ID broadcast mask - xAPIC mode. */280 # define XAPIC_ID_BROADCAST_MASK UINT32_C(0xff)281 #else282 # error "Implement Pentium and P6 family APIC architectures"283 #endif284 74 285 75 /** … … 1055 845 APICMSRACCESS_COUNT 1056 846 } APICMSRACCESS; 1057 1058 /** @name xAPIC Destination Format Register bits.1059 * See Intel spec. 10.6.2.2 "Logical Destination Mode".1060 * @{ */1061 typedef enum XAPICDESTFORMAT1062 {1063 XAPICDESTFORMAT_FLAT = 0xf,1064 XAPICDESTFORMAT_CLUSTER = 01065 } XAPICDESTFORMAT;1066 /** @} */1067 1068 /** @name xAPIC Timer Mode bits.1069 * See Intel spec. 10.5.1 "Local Vector Table".1070 * @{ */1071 typedef enum XAPICTIMERMODE1072 {1073 XAPICTIMERMODE_ONESHOT = XAPIC_TIMER_MODE_ONESHOT,1074 XAPICTIMERMODE_PERIODIC = XAPIC_TIMER_MODE_PERIODIC,1075 XAPICTIMERMODE_TSC_DEADLINE = XAPIC_TIMER_MODE_TSC_DEADLINE1076 } XAPICTIMERMODE;1077 /** @} */1078 1079 /** @name xAPIC Interrupt Command Register bits.1080 * See Intel spec. 10.6.1 "Interrupt Command Register (ICR)".1081 * See Intel spec. 10.5.1 "Local Vector Table".1082 * @{ */1083 /**1084 * xAPIC destination shorthand.1085 */1086 typedef enum XAPICDESTSHORTHAND1087 {1088 XAPICDESTSHORTHAND_NONE = 0,1089 XAPICDESTSHORTHAND_SELF,1090 XAPIDDESTSHORTHAND_ALL_INCL_SELF,1091 XAPICDESTSHORTHAND_ALL_EXCL_SELF1092 } XAPICDESTSHORTHAND;1093 1094 /**1095 * xAPIC INIT level de-assert delivery mode.1096 */1097 typedef enum XAPICINITLEVEL1098 {1099 XAPICINITLEVEL_DEASSERT = 0,1100 XAPICINITLEVEL_ASSERT1101 } XAPICLEVEL;1102 1103 /**1104 * xAPIC destination mode.1105 */1106 typedef enum XAPICDESTMODE1107 {1108 XAPICDESTMODE_PHYSICAL = 0,1109 XAPICDESTMODE_LOGICAL1110 } XAPICDESTMODE;1111 1112 /**1113 * xAPIC delivery mode type.1114 */1115 typedef enum XAPICDELIVERYMODE1116 {1117 XAPICDELIVERYMODE_FIXED = 0,1118 XAPICDELIVERYMODE_LOWEST_PRIO = 1,1119 XAPICDELIVERYMODE_SMI = 2,1120 XAPICDELIVERYMODE_NMI = 4,1121 XAPICDELIVERYMODE_INIT = 5,1122 XAPICDELIVERYMODE_STARTUP = 6,1123 XAPICDELIVERYMODE_EXTINT = 71124 } XAPICDELIVERYMODE;1125 847 /** @} */ 1126 848
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