- Timestamp:
- Jun 15, 2020 8:20:40 AM (5 years ago)
- Location:
- trunk
- Files:
-
- 18 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/msi.h
r84677 r84826 145 145 * fields but specifies reserved bits. 146 146 */ 147 typedef union 147 typedef union MSIADDR 148 148 { 149 149 struct … … 177 177 178 178 /** 179 * MSI Data Register (PCI + MMIO).179 * MSI Data Register. 180 180 * In accordance to the Intel spec. 181 181 * See Intel spec. 10.11.2 "Message Data Register Format". … … 184 184 * fields but specifies reserved bits. 185 185 */ 186 typedef union 186 typedef union MSIDATA 187 187 { 188 188 struct … … 210 210 * MSI Message (Address and Data Register Pair). 211 211 */ 212 typedef struct 212 typedef struct MSIMSG 213 213 { 214 214 /** The MSI Address Register. */ … … 217 217 MSIDATA Data; 218 218 } MSIMSG; 219 /** Pointer to an MSI message struct. */220 typedef MSIMSG *PMSIMSG;221 /** Pointer to a const MSI message struct. */222 typedef MSIMSG const *PCMSIMSG;223 219 224 220 #endif /* !VBOX_INCLUDED_msi_h */ -
trunk/include/VBox/pci.h
r84799 r84826 469 469 /** Make a device+function number. */ 470 470 #define VBOX_PCI_DEVFN_MAKE(a_uPciDevNo, a_uPciFunNo) (((a_uPciDevNo) << VBOX_PCI_DEVFN_DEV_SHIFT) | (a_uPciFunNo)) 471 /** Make a bus+device+function number. */ 472 #define VBOX_PCI_BUSDEVFN_MAKE(a_uPciBusNo, a_uPciDevFunNo) (((a_uPciBusNo) << VBOX_PCI_BUS_SHIFT) | (a_uPciDevFunNo)) 471 472 /** Checks whether the PCIBDF is valid. */ 473 #define PCIBDF_IS_VALID(a_uBusDevFn) (!((a_uBusDevFn) & PCI_BDF_F_INVALID)) 474 /** Make a PCIBDF given the bus and device:function. */ 475 #define PCIBDF_MAKE(a_uBus, a_uDevFn) (((a_uBus) << VBOX_PCI_BUS_SHIFT) | (a_uDevFn)) 473 476 474 477 -
trunk/include/VBox/types.h
r84458 r84826 1201 1201 1202 1202 1203 /** 1204 * A PCI bus:device:function (BDF) identifier. 1205 * 1206 * All 16 bits of a BDF are valid according to the PCI spec. We need one extra bit 1207 * to determine whether the BDF is valid in interfaces where the BDF may be 1208 * optional. 1209 */ 1210 typedef uint32_t PCIBDF; 1211 /** PCIBDF flag: Invalid. */ 1212 #define PCI_BDF_F_INVALID RT_BIT(31) 1213 /** Nil PCIBDF value. */ 1214 #define NIL_PCIBDF PCI_BDF_F_INVALID 1215 1216 /** Pointer to an MSI message struct. */ 1217 typedef struct MSIMSG *PMSIMSG; 1218 /** Pointer to a const MSI message struct. */ 1219 typedef const struct MSIMSG *PCMSIMSG; 1220 1221 1203 1222 /** @} */ 1204 1223 -
trunk/include/VBox/vmm/pdmapi.h
r84459 r84826 53 53 VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM); 54 54 VMM_INT_DECL(bool) PDMHasApic(PVM pVM); 55 VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc);55 VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc); 56 56 VMM_INT_DECL(VBOXSTRICTRC) PDMIoApicBroadcastEoi(PVM pVM, uint8_t uVector); 57 VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc);57 VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc); 58 58 VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys); 59 59 VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM); -
trunk/include/VBox/vmm/pdmdev.h
r84714 r84826 1034 1034 * 1035 1035 * @param pDevIns PCI device instance. 1036 * @param uBusDevFn The bus:device:function of the device initiating the 1037 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or 1038 * interrupt. 1036 1039 * @param iIrq IRQ number to set. 1037 1040 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines. … … 1039 1042 * @thread EMT only. 1040 1043 */ 1041 DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));1044 DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)); 1042 1045 1043 1046 /** … … 1045 1048 * 1046 1049 * @param pDevIns PCI device instance. 1047 * @param GCPhys Physical address MSI request was written. 1048 * @param uValue Value written. 1050 * @param uBusDevFn The bus:device:function of the device initiating the 1051 * MSI. Cannot be NIL_PCIBDF. 1052 * @param pMsi The MSI to send. 1049 1053 * @param uTagSrc The IRQ tag and source (for tracing). 1050 1054 * @thread EMT only. 1051 1055 */ 1052 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));1056 DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)); 1053 1057 1054 1058 … … 1088 1092 1089 1093 /** Current PDMPCIHLPRC version number. */ 1090 #define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 3, 0)1094 #define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0) 1091 1095 1092 1096 … … 1114 1118 * 1115 1119 * @param pDevIns PCI device instance. 1120 * @param uBusDevFn The bus:device:function of the device initiating the 1121 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or 1122 * interrupt. 1116 1123 * @param iIrq IRQ number to set. 1117 1124 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines. … … 1119 1126 * @thread EMT only. 1120 1127 */ 1121 DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));1128 DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)); 1122 1129 1123 1130 /** … … 1125 1132 * 1126 1133 * @param pDevIns PCI device instance. 1127 * @param GCPhys Physical address MSI request was written. 1128 * @param uValue Value written. 1134 * @param uBusDevFn The bus:device:function of the device initiating the 1135 * MSI. Cannot be NIL_PCIBDF. 1136 * @param pMsi The MSI to send. 1129 1137 * @param uTagSrc The IRQ tag and source (for tracing). 1130 1138 * @thread EMT only. 1131 1139 */ 1132 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));1140 DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)); 1133 1141 1134 1142 /** … … 1167 1175 1168 1176 /** Current PDMPCIHLPR0 version number. */ 1169 #define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 5, 0)1177 #define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0) 1170 1178 1171 1179 /** … … 1191 1199 * 1192 1200 * @param pDevIns The PCI device instance. 1201 * @param uBusDevFn The bus:device:function of the device initiating the 1202 * IRQ. Pass NIL_PCIBDF when it's not a PCI device or 1203 * interrupt. 1193 1204 * @param iIrq IRQ number to set. 1194 1205 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines. 1195 1206 * @param uTagSrc The IRQ tag and source (for tracing). 1196 1207 */ 1197 DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));1208 DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)); 1198 1209 1199 1210 /** … … 1201 1212 * 1202 1213 * @param pDevIns PCI device instance. 1203 * @param GCPhys Physical address MSI request was written. 1204 * @param uValue Value written. 1214 * @param uBusDevFn The bus:device:function of the device initiating the 1215 * MSI. Cannot be NIL_PCIBDF. 1216 * @param pMsi The MSI to send. 1205 1217 * @param uTagSrc The IRQ tag and source (for tracing). 1206 1218 */ 1207 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc));1219 DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)); 1208 1220 1209 1221 /** … … 1242 1254 1243 1255 /** Current PDMPCIHLPR3 version number. */ 1244 #define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 4, 0)1256 #define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0) 1245 1257 1246 1258 … … 1695 1707 * 1696 1708 * @param pDevIns Device instance of the I/O APIC. 1709 * @param uBusDevFn The bus:device:function of the device initiating the 1710 * IRQ. Can be NIL_PCIBDF. 1697 1711 * @param iIrq IRQ number to set. 1698 1712 * @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines. … … 1702 1716 * Actually, as per 2018-07-21 this isn't true (bird). 1703 1717 */ 1704 DECLCALLBACKMEMBER(void, pfnSetIrq)(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc);1718 DECLCALLBACKMEMBER(void, pfnSetIrq)(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc); 1705 1719 1706 1720 /** … … 1708 1722 * 1709 1723 * @param pDevIns Device instance of the I/O APIC. 1710 * @param GCPhys Request address. 1711 * @param uValue Request value. 1724 * @param uBusDevFn The bus:device:function of the device initiating the 1725 * MSI. Cannot be NIL_PCIBDF. 1726 * @param pMsi The MSI to send. 1712 1727 * @param uTagSrc The IRQ tag and source (for tracing). 1713 1728 * … … 1715 1730 * Actually, as per 2018-07-21 this isn't true (bird). 1716 1731 */ 1717 DECLCALLBACKMEMBER(void, pfnSendMsi)(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc);1732 DECLCALLBACKMEMBER(void, pfnSendMsi)(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc); 1718 1733 1719 1734 /** … … 1739 1754 1740 1755 /** Current PDMAPICREG version number. */ 1741 #define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 6, 0)1756 #define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 7, 0) 1742 1757 1743 1758 -
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r84808 r84826 4223 4223 if (uNextLevel == 7) 4224 4224 { 4225 /* The default page size of the translation is overrid en. */4225 /* The default page size of the translation is overridden. */ 4226 4226 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK; 4227 4227 uint8_t cShift = X86_PAGE_4K_SHIFT; -
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r82968 r84826 246 246 /* This is only allowed to be called with a pointer to the host bus. */ 247 247 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus)); 248 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn); 248 249 249 250 if (iAcpiIrq == -1) { … … 261 262 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n", 262 263 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num)); 263 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);264 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc); 264 265 265 266 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) { … … 269 270 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n", 270 271 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num)); 271 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);272 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc); 272 273 } 273 274 } else { 274 Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", 275 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq)); 276 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iAcpiIrq, iLevel, uTagSrc); 275 Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq)); 276 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iAcpiIrq, iLevel, uTagSrc); 277 277 } 278 278 } -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r82968 r84826 547 547 /* This is only allowed to be called with a pointer to the root bus. */ 548 548 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus)); 549 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn); 549 550 550 551 if (iForcedIrq == -1) … … 563 564 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n", 564 565 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc)); 565 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);566 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc); 566 567 567 568 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) … … 576 577 Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n", 577 578 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc)); 578 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, apic_irq, apic_level, uTagSrc);579 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc); 579 580 } 580 581 } else { 581 582 Log3Func(("(forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n", 582 583 R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iForcedIrq, uTagSrc)); 583 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, iForcedIrq, iLevel, uTagSrc);584 pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iForcedIrq, iLevel, uTagSrc); 584 585 } 585 586 } -
trunk/src/VBox/Devices/Bus/MsiCommon.cpp
r82968 r84826 27 27 #include "MsiCommon.h" 28 28 #include "PciInline.h" 29 #include "DevPciInternal.h" 29 30 30 31 … … 330 331 } 331 332 332 RTGCPHYS GCAddr = msiGetMsiAddress(pDev); 333 uint32_t u32Value = msiGetMsiData(pDev, iVector); 333 MSIMSG Msi; 334 Msi.Addr.u64 = msiGetMsiAddress(pDev); 335 Msi.Data.u32 = msiGetMsiData(pDev, iVector); 334 336 335 337 if (puPending) 336 338 *puPending &= ~(1<<iVector); 337 339 340 PPDMDEVINS pDevInsBus = pPciHlp->pfnGetBusByNo(pDevIns, pDev->Int.s.idxPdmBus); 341 Assert(pDevInsBus); 342 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS); 343 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, pDev->uDevFn); 344 338 345 Assert(pPciHlp->pfnIoApicSendMsi != NULL); 339 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc);340 } 341 346 pPciHlp->pfnIoApicSendMsi(pDevIns, uBusDevFn, &Msi, uTagSrc); 347 } 348 -
trunk/src/VBox/Devices/Bus/MsixCommon.cpp
r82968 r84826 29 29 30 30 #include "MsiCommon.h" 31 #include "DevPCIInternal.h" 31 32 #include "PciInline.h" 32 33 … … 268 269 msixClearPending(pDev, iVector); 269 270 270 RTGCPHYS GCAddr = msixGetMsiAddress(pDev, iVector); 271 uint32_t u32Value = msixGetMsiData(pDev, iVector); 272 273 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc); 271 MSIMSG Msi; 272 Msi.Addr.u64 = msixGetMsiAddress(pDev, iVector); 273 Msi.Data.u32 = msixGetMsiData(pDev, iVector); 274 275 PPDMDEVINS pDevInsBus = pPciHlp->pfnGetBusByNo(pDevIns, pDev->Int.s.idxPdmBus); 276 Assert(pDevInsBus); 277 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS); 278 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, pDev->uDevFn); 279 280 pPciHlp->pfnIoApicSendMsi(pDevIns, uBusDevFn, &Msi, uTagSrc); 274 281 } 275 282 -
trunk/src/VBox/Devices/PC/DevIoApic.cpp
r84677 r84826 166 166 #define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */ 167 167 168 /** The I/O APIC's Bus:Device:Function. */ 169 #define IOAPIC_BUS_DEV_FN NIL_PCIBDF 170 168 171 /* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */ 169 172 #define IOAPIC_WITH_PDM_CRITSECT … … 472 475 * @param pThis The shared I/O APIC device state. 473 476 * @param pThisCC The I/O APIC device state for the current context. 477 * @param uBusDevFn The bus:device:function of the device initiating the IRQ. 474 478 * @param idxRte The index of the RTE (validated). 475 479 * … … 478 482 * function. 479 483 */ 480 static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)484 static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte) 481 485 { 482 486 #ifndef IOAPIC_WITH_PDM_CRITSECT … … 499 503 } 500 504 } 505 506 /** @todo IOMMU: Call into the IOMMU on how to remap this interrupt. uBusDevFn 507 * will be needed then. */ 508 NOREF(uBusDevFn); 501 509 502 510 uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte); … … 622 630 uint32_t const uPinMask = UINT32_C(1) << idxRte; 623 631 if (pThis->uIrr & uPinMask) 624 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);632 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte); 625 633 626 634 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC); … … 737 745 uint32_t const uPinMask = UINT32_C(1) << idxRte; 738 746 if (pThis->uIrr & uPinMask) 739 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);747 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte); 740 748 } 741 749 } … … 754 762 * @interface_method_impl{PDMIOAPICREG,pfnSetIrq} 755 763 */ 756 static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)757 { 758 #define IOAPIC_ASSERT_IRQ(a_ idxRte, a_PinMask) do { \764 static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc) 765 { 766 #define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \ 759 767 pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \ 760 768 pThis->uIrr |= a_PinMask; \ 761 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_ idxRte)); \769 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \ 762 770 } while (0) 763 771 … … 803 811 */ 804 812 if (!uPrevIrr) 805 IOAPIC_ASSERT_IRQ( idxRte, uPinMask);813 IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask); 806 814 else 807 815 { … … 827 835 } 828 836 829 IOAPIC_ASSERT_IRQ( idxRte, uPinMask);837 IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask); 830 838 } 831 839 } … … 838 846 * hence just the assert is done. 839 847 */ 840 IOAPIC_ASSERT_IRQ( idxRte, uPinMask);848 IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask); 841 849 } 842 850 … … 850 858 * @interface_method_impl{PDMIOAPICREG,pfnSendMsi} 851 859 */ 852 static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)860 static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc) 853 861 { 854 862 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC); 855 LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue)); 856 857 MSIMSG Msi; 858 Msi.Addr.u64 = GCPhys; 859 Msi.Data.u32 = uValue; 863 LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32)); 860 864 861 865 XAPICINTR ApicIntr; 862 866 RT_ZERO(ApicIntr); 863 ioapicGetApicIntrFromMsi(&Msi, &ApicIntr); 867 ioapicGetApicIntrFromMsi(pMsi, &ApicIntr); 868 869 /** @todo IOMMU: Call into the IOMMU to remap the MSI. uBusDevFn will be used 870 * then. */ 871 NOREF(uBusDevFn); 864 872 865 873 /* -
trunk/src/VBox/VMM/VMMAll/PDMAll.cpp
r82968 r84826 156 156 u8Irq = 2; 157 157 158 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);158 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc); 159 159 rc = VINF_SUCCESS; 160 160 } … … 173 173 * @param pVM The cross context VM structure. 174 174 * @param u8Irq The IRQ line. 175 * @param uBusDevFn The bus:device:function of the device initiating the IRQ. 176 * Pass NIL_PCIBDF when it's not a PCI device or interrupt. 175 177 * @param u8Level The new level. 176 178 * @param uTagSrc The IRQ tag and source tracer ID. 177 179 */ 178 VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)180 VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc) 179 181 { 180 182 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns)) 181 183 { 182 184 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)); 183 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u 8Irq, u8Level, uTagSrc);185 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc); 184 186 return VINF_SUCCESS; 185 187 } … … 218 220 * @returns VBox status code. 219 221 * @param pVM The cross context VM structure. 220 * @param GCAddr Request address. 221 * @param uValue Request value. 222 * @param uBusDevFn The bus:device:function of the device initiating the MSI. 223 * Cannot be NIL_PCIBDF. 224 * @param pMsi The MSI to send. 222 225 * @param uTagSrc The IRQ tag and source tracer ID. 223 226 */ 224 VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc) 225 { 227 VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc) 228 { 229 Assert(PCIBDF_IS_VALID(uBusDevFn)); 226 230 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns)) 227 231 { 228 232 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)); 229 pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), GCAddr, uValue, uTagSrc);233 pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, pMsi, uTagSrc); 230 234 return VINF_SUCCESS; 231 235 } -
trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp
r84823 r84826 164 164 165 165 RTGCPHYS GCPhysOut; 166 uint16_t const uDeviceId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);166 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 167 167 int rc = pIommu->pfnMemRead(pDevInsIommu, uDeviceId, GCPhys, cbRead, &GCPhysOut); 168 168 if (RT_FAILURE(rc)) … … 216 216 217 217 RTGCPHYS GCPhysOut; 218 uint16_t const uDeviceId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);218 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 219 219 int rc = pIommu->pfnMemWrite(pDevInsIommu, uDeviceId, GCPhys, cbWrite, &GCPhysOut); 220 220 if (RT_FAILURE(rc)) … … 1612 1612 1613 1613 /** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */ 1614 static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)1615 { 1616 PDMDEV_ASSERT_DEVINS(pDevIns); 1617 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));1614 static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc) 1615 { 1616 PDMDEV_ASSERT_DEVINS(pDevIns); 1617 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc)); 1618 1618 PGVM pGVM = pDevIns->Internal.s.pGVM; 1619 1619 1620 1620 if (pGVM->pdm.s.IoApic.pDevInsR0) 1621 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);1621 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc); 1622 1622 else if (pGVM->pdm.s.IoApic.pDevInsR3) 1623 1623 { … … 1628 1628 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ; 1629 1629 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */ 1630 pTask->u.IoApicSetIRQ.uBusDevFn = uBusDevFn; 1630 1631 pTask->u.IoApicSetIRQ.iIrq = iIrq; 1631 1632 pTask->u.IoApicSetIRQ.iLevel = iLevel; … … 1641 1642 1642 1643 /** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */ 1643 static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc) 1644 { 1645 PDMDEV_ASSERT_DEVINS(pDevIns); 1646 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc)); 1644 static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc) 1645 { 1646 PDMDEV_ASSERT_DEVINS(pDevIns); 1647 Assert(PCIBDF_IS_VALID(uBusDevFn)); 1648 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64, 1649 pMsi->Data.u32, uTagSrc)); 1647 1650 PGVM pGVM = pDevIns->Internal.s.pGVM; 1648 1651 if (pGVM->pdm.s.IoApic.pDevInsR0) 1649 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);1652 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, pMsi, uTagSrc); 1650 1653 else 1651 1654 AssertFatalMsgFailed(("Lazy bastards!")); … … 1756 1759 * @returns true if delivered, false if postponed. 1757 1760 * @param pGVM The global (ring-0) VM structure. 1761 * @param uBusDevFn The bus:device:function of the device initiating the IRQ. 1762 * Can be NIL_PCIBDF. 1758 1763 * @param iIrq The irq. 1759 1764 * @param iLevel The new level. … … 1772 1777 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc); 1773 1778 if (pGVM->pdm.s.IoApic.pDevInsR0) 1774 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);1779 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc); 1775 1780 return true; 1776 1781 } … … 1782 1787 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ; 1783 1788 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */ 1789 pTask->u.IsaSetIRQ.uBusDevFn = NIL_PCIBDF; 1784 1790 pTask->u.IsaSetIRQ.iIrq = iIrq; 1785 1791 pTask->u.IsaSetIRQ.iLevel = iLevel; -
trunk/src/VBox/VMM/VMMR0/PDMR0DevHlpTracing.cpp
r84809 r84826 322 322 323 323 RTGCPHYS GCPhysOut; 324 uint16_t const uDeviceId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);324 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 325 325 int rc = pIommu->pfnMemRead(pDevInsIommu, uDeviceId, GCPhys, cbRead, &GCPhysOut); 326 326 if (RT_FAILURE(rc)) … … 374 374 375 375 RTGCPHYS GCPhysOut; 376 uint16_t const uDeviceId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);376 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 377 377 int rc = pIommu->pfnMemWrite(pDevInsIommu, uDeviceId, GCPhys, cbWrite, &GCPhysOut); 378 378 if (RT_FAILURE(rc)) -
trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp
r84809 r84826 1804 1804 1805 1805 RTGCPHYS GCPhysOut; 1806 uint16_t const uDevId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);1806 uint16_t const uDevId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 1807 1807 int rc = pIommu->pfnMemRead(pDevInsIommu, uDevId, GCPhys, cbRead, &GCPhysOut); 1808 1808 if (RT_FAILURE(rc)) … … 1856 1856 1857 1857 RTGCPHYS GCPhysOut; 1858 uint16_t const uDevId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);1858 uint16_t const uDevId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 1859 1859 int rc = pIommu->pfnMemWrite(pDevInsIommu, uDevId, GCPhys, cbWrite, &GCPhysOut); 1860 1860 if (RT_FAILURE(rc)) … … 5193 5193 5194 5194 case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ: 5195 PDMIoApicSetIrq(pVM, pTask->u.IoApicSetIRQ.iIrq, pTask->u.IoApicSetIRQ.iLevel, pTask->u.IoApicSetIRQ.uTagSrc); 5195 { 5196 PDMIoApicSetIrq(pVM, pTask->u.IoApicSetIRQ.uBusDevFn, pTask->u.IoApicSetIRQ.iIrq, pTask->u.IoApicSetIRQ.iLevel, 5197 pTask->u.IoApicSetIRQ.uTagSrc); 5196 5198 break; 5199 } 5197 5200 5198 5201 default: -
trunk/src/VBox/VMM/VMMR3/PDMDevHlpTracing.cpp
r84809 r84826 427 427 428 428 RTGCPHYS GCPhysOut; 429 uint16_t const uDevId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);429 uint16_t const uDevId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 430 430 int rc = pIommu->pfnMemRead(pDevInsIommu, uDevId, GCPhys, cbRead, &GCPhysOut); 431 431 if (RT_FAILURE(rc)) … … 479 479 480 480 RTGCPHYS GCPhysOut; 481 uint16_t const uDevId = VBOX_PCI_BUSDEVFN_MAKE(pBus->iBus, pPciDev->uDevFn);481 uint16_t const uDevId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn); 482 482 int rc = pIommu->pfnMemWrite(pDevInsIommu, uDevId, GCPhys, cbWrite, &GCPhysOut); 483 483 if (RT_FAILURE(rc)) -
trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp
r84678 r84826 204 204 205 205 /** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */ 206 static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)207 { 208 PDMDEV_ASSERT_DEVINS(pDevIns); 209 Log4(("pdmR3PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));210 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);206 static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc) 207 { 208 PDMDEV_ASSERT_DEVINS(pDevIns); 209 Log4(("pdmR3PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc)); 210 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, uBusDevFn, iIrq, iLevel, uTagSrc); 211 211 } 212 212 213 213 214 214 /** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */ 215 static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc) 216 { 217 PDMDEV_ASSERT_DEVINS(pDevIns); 218 Log4(("pdmR3PciHlp_IoApicSendMsi: address=%p value=%x uTagSrc=%#x\n", GCPhys, uValue, uTagSrc)); 219 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, GCPhys, uValue, uTagSrc); 215 static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc) 216 { 217 PDMDEV_ASSERT_DEVINS(pDevIns); 218 Assert(PCIBDF_IS_VALID(uBusDevFn)); 219 Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn, 220 pMsi->Addr.u64, pMsi->Data.u32, uTagSrc)); 221 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc); 220 222 } 221 223 -
trunk/src/VBox/VMM/include/PDMInternal.h
r84755 r84826 788 788 PPDMDEVINSR3 pDevInsR3; 789 789 /** @copydoc PDMIOAPICREG::pfnSetIrq */ 790 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));790 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)); 791 791 /** @copydoc PDMIOAPICREG::pfnSendMsi */ 792 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));792 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)); 793 793 /** @copydoc PDMIOAPICREG::pfnSetEoi */ 794 794 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector)); … … 797 797 PPDMDEVINSR0 pDevInsR0; 798 798 /** @copydoc PDMIOAPICREG::pfnSetIrq */ 799 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));799 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)); 800 800 /** @copydoc PDMIOAPICREG::pfnSendMsi */ 801 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));801 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)); 802 802 /** @copydoc PDMIOAPICREG::pfnSetEoi */ 803 803 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector)); … … 806 806 PPDMDEVINSRC pDevInsRC; 807 807 /** @copydoc PDMIOAPICREG::pfnSetIrq */ 808 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));808 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)); 809 809 /** @copydoc PDMIOAPICREG::pfnSendMsi */ 810 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));810 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)); 811 811 /** @copydoc PDMIOAPICREG::pfnSendMsi */ 812 812 DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector)); … … 1222 1222 struct PDMDEVHLPTASKISASETIRQ 1223 1223 { 1224 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */ 1225 PCIBDF uBusDevFn; 1224 1226 /** The IRQ */ 1225 1227 int iIrq;
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