Changeset 85007 in vbox for trunk/src/VBox/Main

Timestamp:

Jun 30, 2020 5:19:25 PM (5 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

138905

Message:

AMD IOMMU: bugref:9654 PDM, Main: Changes for southbridge I/O APIC and related PCI address assignment.

Location:

trunk/src/VBox/Main

Files:

• Makefile.kmk (modified) (1 diff)
• include/BusAssignmentManager.h (modified) (1 diff)
• src-client/BusAssignmentManager.cpp (modified) (12 diffs)
• src-client/ConsoleImpl2.cpp (modified) (2 diffs)

trunk/src/VBox/Main/Makefile.kmk

@@ -878 +878 @@
         $(if $(VBOX_WITH_DRAG_AND_DROP_GH),VBOX_WITH_DRAG_AND_DROP_GH,) \
         $(if $(VBOX_WITH_USB),VBOX_WITH_USB,) \
-        $(if $(VBOX_WITH_VRDEAUTH_IN_VBOXSVC),VBOX_WITH_VRDEAUTH_IN_VBOXSVC,)
+        $(if $(VBOX_WITH_VRDEAUTH_IN_VBOXSVC),VBOX_WITH_VRDEAUTH_IN_VBOXSVC,) \
+        $(if $(VBOX_WITH_IOMMU_AMD),VBOX_WITH_IOMMU_AMD,)
 ifdef VBOX_WITH_NETSHAPER
  VBoxC_DEFS += VBOX_WITH_NETSHAPER

trunk/src/VBox/Main/include/BusAssignmentManager.h

@@ -47 +47 @@
     };
 
-    static BusAssignmentManager *createInstance(ChipsetType_T chipsetType);
+    static BusAssignmentManager *createInstance(ChipsetType_T chipsetType, bool fIommu);
     virtual void AddRef();
     virtual void Release();

trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp

@@ -68 +68 @@
 
     /* Storage controllers */
-    {"lsilogic",      0, 20, 0,  1},
     {"buslogic",      0, 21, 0,  1},
     {"lsilogicsas",   0, 22, 0,  1},
@@ -111 +110 @@
     {"piix3ide",      0,  1,  1, 0},
     {"ahci",          0, 13,  0, 1},
+    {"lsilogic",      0, 20,  0, 1},
     {"pcibridge",     0, 24,  0, 0},
     {"pcibridge",     0, 25,  0, 0},
@@ -229 +229 @@
 };
 
+
+#ifdef VBOX_WITH_IOMMU_AMD
+/*
+ * AMD IOMMU and LSI Logic controller rules.
+ *
+ * Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
+ * conflicts with the SB I/O APIC, we assign the LSI Logic controller
+ * to device number 23 when the VM is configured for an AMD IOMMU.
+ */
+static const DeviceAssignmentRule aIch9IommuLsiRules[] =
+{
+    /* AMD IOMMU. */
+    {"iommu-amd",     0,  0,  2, 0},
+    /* AMD IOMMU: Reserved for southbridge I/O APIC. */
+    {"sb-ioapic",     0, 20,  0, 0},
+
+    /* Storage controller */
+    {"lsilogic",      0, 23,  0, 1},
+    { NULL,          -1, -1, -1, 0}
+};
+#endif
+
+/* LSI Logic Controller. */
+static const DeviceAssignmentRule aIch9LsiRules[] =
+{
+    /* Storage controller */
+    {"lsilogic",      0, 20,  0, 1},
+    { NULL,          -1, -1, -1, 0}
+};
+
 /* Aliasing rules */
 static const DeviceAliasRule aDeviceAliases[] =
@@ -280 +310 @@
     ChipsetType_T    mChipsetType;
     const char *     mpszBridgeName;
+    bool             mfIommu;
     PCIMap           mPCIMap;
     ReversePCIMap    mReversePCIMap;
@@ -289 +320 @@
     {}
 
-    HRESULT init(ChipsetType_T chipsetType);
+    HRESULT init(ChipsetType_T chipsetType, bool fIommu);
 
     HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
@@ -301 +332 @@
 };
 
-HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
+HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType, bool fIommu)
 {
     mChipsetType = chipsetType;
+    mfIommu = fIommu;
     switch (chipsetType)
     {
@@ -340 +372 @@
 }
 
-bool    BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
+bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
 {
     PCIDeviceRecord devRec(pszDevName);
@@ -358 +390 @@
 {
     size_t iRuleset, iRule;
-    const DeviceAssignmentRule *aArrays[2] = {aGenericRules, NULL};
+    const DeviceAssignmentRule *aArrays[3] = {aGenericRules, NULL, NULL};
 
     switch (mChipsetType)
@@ -366 +398 @@
             break;
         case ChipsetType_ICH9:
+        {
             aArrays[1] = aIch9Rules;
+#ifdef VBOX_WITH_IOMMU_AMD
+            if (mfIommu)
+                aArrays[2] = aIch9IommuLsiRules;
+            else
+#endif
+            {
+                aArrays[2] = aIch9LsiRules;
+            }
             break;
+        }
         default:
             AssertFailed();
@@ -405 +447 @@
     PCIRulesList matchingRules;
 
-    addMatchingRules(pszName,  matchingRules);
+    addMatchingRules(pszName, matchingRules);
     const char *pszAlias = findAlias(pszName);
     if (pszAlias)
@@ -468 +510 @@
 }
 
-BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType)
+BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType, bool fIommu)
 {
     BusAssignmentManager *pInstance = new BusAssignmentManager();
-    pInstance->pState->init(chipsetType);
+    pInstance->pState->init(chipsetType, fIommu);
     Assert(pInstance);
     return pInstance;
@@ -537 +579 @@
         return rc;
 
-    rc = InsertConfigInteger(pCfg, "PCIBusNo",      GuestAddress.miBus);
-    if (FAILED(rc))
-        return rc;
-    rc = InsertConfigInteger(pCfg, "PCIDeviceNo",   GuestAddress.miDevice);
-    if (FAILED(rc))
-        return rc;
-    rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
-    if (FAILED(rc))
-        return rc;
+    if (pCfg)
+    {
+        rc = InsertConfigInteger(pCfg, "PCIBusNo",      GuestAddress.miBus);
+        if (FAILED(rc))
+            return rc;
+        rc = InsertConfigInteger(pCfg, "PCIDeviceNo",   GuestAddress.miDevice);
+        if (FAILED(rc))
+            return rc;
+        rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
+        if (FAILED(rc))
+            return rc;
+    }
 
     /* Check if the bus is still unknown, i.e. the bridge to it is missing */

trunk/src/VBox/Main/src-client/ConsoleImpl2.cpp

@@ -801 +801 @@
     }
 
-    BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(chipsetType);
+    /** @todo Get IOMMU from pMachine and pass info to createInstance() below. */
+    BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(chipsetType, false /* fIommu */);
 
     ULONG cCpus = 1;
@@ -1493 +1494 @@
             hrc = i_attachRawPCIDevices(pUVM, pBusMgr, pDevices);                           H();
 #endif
-        }
+
+#ifdef VBOX_WITH_IOMMU_AMD
+            /* AMD IOMMU. */
+            /** @todo Get IOMMU from pMachine. */
+            InsertConfigNode(pDevices, "iommu-amd", &pDev);
+            InsertConfigNode(pDev,     "0", &pInst);
+            InsertConfigInteger(pInst, "Trusted",   1); /* boolean */
+            InsertConfigNode(pInst,    "Config", &pCfg);
+            hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst);                             H();
+
+            /*
+             * Reserve the specific PCI address of the "SB I/O APIC" when using
+             * an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
+             */
+            PCIBusAddress PCIAddr = PCIBusAddress(VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC);
+            hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg */, PCIAddr, true /*fGuestAddressRequired*/);  H();
+#endif
+        }
+        /** @todo IOMMU: Disallow creating a VM without ICH9 chipset if an IOMMU is
+         *        configured. */
 
         /*