Changeset 8564 in vbox for trunk/src

Timestamp:

May 5, 2008 11:50:50 AM (17 years ago)

Author:

vboxsync

Message:

NoDmik -> NOT_DMIK.

Location:

trunk/src

Files:

• VBox/VMM/CFGM.cpp (modified) (1 diff)
• VBox/VMM/PDMDevice.cpp (modified) (1 diff)
• VBox/VMM/VM.cpp (modified) (1 diff)
• recompiler/target-i386/helper.c (modified) (129 diffs)

trunk/src/VBox/VMM/CFGM.cpp

@@ -143 +143 @@
     }
     else
-        NoDmik(AssertMsgFailed(("Constructor failed with rc=%Vrc pfnCFGMConstructor=%p\n", rc, pfnCFGMConstructor)));
+        NOT_DMIK(AssertMsgFailed(("Constructor failed with rc=%Vrc pfnCFGMConstructor=%p\n", rc, pfnCFGMConstructor)));
 
     return rc;

trunk/src/VBox/VMM/PDMDevice.cpp

@@ -942 +942 @@
         if (VBOX_FAILURE(rc))
         {
-            NoDmik(AssertMsgFailed(("Failed to construct '%s'/%d! %Vra\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)));
+            NOT_DMIK(AssertMsgFailed(("Failed to construct '%s'/%d! %Vra\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)));
             /* because we're damn lazy right now, we'll say that the destructor will be called even if the constructor fails. */
             return rc;

trunk/src/VBox/VMM/VM.cpp

@@ -241 +241 @@
                 default:
                     pszError = N_("Unknown error creating VM");
-                    NoDmik(AssertMsgFailed(("Add error message for rc=%d (%Vrc)\n", rc, rc)));
+                    NOT_DMIK(AssertMsgFailed(("Add error message for rc=%d (%Vrc)\n", rc, rc)));
                     break;
             }

trunk/src/recompiler/target-i386/helper.c

@@ -1 +1 @@
 /*
  *  i386 helpers
- * 
+ *
  *  Copyright (c) 2003 Fabrice Bellard
  *
@@ -71 +71 @@
 /* modulo 17 table */
 const uint8_t rclw_table[32] = {
-    0, 1, 2, 3, 4, 5, 6, 7, 
+    0, 1, 2, 3, 4, 5, 6, 7,
     8, 9,10,11,12,13,14,15,
    16, 0, 1, 2, 3, 4, 5, 6,
@@ -79 +79 @@
 /* modulo 9 table */
 const uint8_t rclb_table[32] = {
-    0, 1, 2, 3, 4, 5, 6, 7, 
+    0, 1, 2, 3, 4, 5, 6, 7,
     8, 0, 1, 2, 3, 4, 5, 6,
-    7, 8, 0, 1, 2, 3, 4, 5, 
+    7, 8, 0, 1, 2, 3, 4, 5,
     6, 7, 8, 0, 1, 2, 3, 4,
 };
@@ -95 +95 @@
     3.32192809488736234781L,  /*l2t*/
 };
-    
+
 /* thread support */
 
@@ -138 +138 @@
     return 0;
 }
-                                     
+
 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
 {
@@ -164 +164 @@
 {
     selector &= 0xffff;
-    cpu_x86_load_seg_cache(env, seg, selector, 
+    cpu_x86_load_seg_cache(env, seg, selector,
                            (selector << 4), 0xffff, 0);
 }
 
-static inline void get_ss_esp_from_tss(uint32_t *ss_ptr, 
+static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
                                        uint32_t *esp_ptr, int dpl)
 {
     int type, index, shift;
-    
+
 #if 0
     {
@@ -243 +243 @@
         if (!(e2 & DESC_P_MASK))
             raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
-        cpu_x86_load_seg_cache(env, seg_reg, selector, 
+        cpu_x86_load_seg_cache(env, seg_reg, selector,
                        get_seg_base(e1, e2),
                        get_seg_limit(e1, e2),
                        e2);
     } else {
-        if (seg_reg == R_SS || seg_reg == R_CS) 
+        if (seg_reg == R_SS || seg_reg == R_CS)
             raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
     }
@@ -258 +258 @@
 
 /* XXX: restore CPU state in registers (PowerPC case) */
-static void switch_tss(int tss_selector, 
+static void switch_tss(int tss_selector,
                        uint32_t e1, uint32_t e2, int source,
                        uint32_t next_eip)
@@ -306 +306 @@
     tss_limit = get_seg_limit(e1, e2);
     tss_base = get_seg_base(e1, e2);
-    if ((tss_selector & 4) != 0 || 
+    if ((tss_selector & 4) != 0 ||
         tss_limit < tss_limit_max)
         raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
@@ -341 +341 @@
         new_trap = 0;
     }
-    
+
     /* NOTE: we must avoid memory exceptions during the task switch,
        so we make dummy accesses before */
@@ -351 +351 @@
     stb_kernel(env->tr.base, v1);
     stb_kernel(env->tr.base + old_tss_limit_max, v2);
-    
+
     /* clear busy bit (it is restartable) */
     if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
@@ -364 +364 @@
     if (source == SWITCH_TSS_IRET)
         old_eflags &= ~NT_MASK;
-    
+
     /* save the current state in the old TSS */
     if (type & 8) {
@@ -399 +399 @@
             stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
     }
-    
+
     /* now if an exception occurs, it will occurs in the next task
        context */
@@ -426 +426 @@
     env->tr.limit = tss_limit;
     env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
-    
+
     if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
         cpu_x86_update_cr3(env, new_cr3);
     }
-    
+
     /* load all registers without an exception, then reload them with
        possible exception */
     env->eip = new_eip;
-    eflags_mask = TF_MASK | AC_MASK | ID_MASK | 
+    eflags_mask = TF_MASK | AC_MASK | ID_MASK |
         IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
     if (!(type & 8))
@@ -449 +449 @@
     EDI = new_regs[7];
     if (new_eflags & VM_MASK) {
-        for(i = 0; i < 6; i++) 
+        for(i = 0; i < 6; i++)
             load_seg_vm(i, new_segs[i]);
         /* in vm86, CPL is always 3 */
@@ -460 +460 @@
             cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
     }
-    
+
     env->ldt.selector = new_ldt & ~4;
     env->ldt.base = 0;
@@ -484 +484 @@
         load_seg_cache_raw_dt(&env->ldt, e1, e2);
     }
-    
+
     /* load the segments */
     if (!(new_eflags & VM_MASK)) {
@@ -494 +494 @@
         tss_load_seg(R_GS, new_segs[R_GS]);
     }
-    
+
     /* check that EIP is in the CS segment limits */
     if (new_eip > env->segs[R_CS].limit) {
@@ -506 +506 @@
 {
     int io_offset, val, mask;
-    
+
     /* TSS must be a valid 32 bit one */
     if (!(env->tr.flags & DESC_P_MASK) ||
@@ -792 +792 @@
         }
     }
-    
+
     if (new_stack) {
         if (env->eflags & VM_MASK) {
@@ -801 +801 @@
         }
         ss = (ss & ~3) | dpl;
-        cpu_x86_load_seg_cache(env, R_SS, ss, 
+        cpu_x86_load_seg_cache(env, R_SS, ss,
                                ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
     }
@@ -807 +807 @@
 
     selector = (selector & ~3) | dpl;
-    cpu_x86_load_seg_cache(env, R_CS, selector, 
+    cpu_x86_load_seg_cache(env, R_CS, selector,
                    get_seg_base(e1, e2),
                    get_seg_limit(e1, e2),
@@ -828 +828 @@
     int io_offset, intredir_offset;
     unsigned char val, mask;
-    
+
     /* TSS must be a valid 32 bit one */
     if (!(env->tr.flags & DESC_P_MASK) ||
@@ -837 +837 @@
     /* the virtual interrupt redirection bitmap is located below the io bitmap */
     intredir_offset = io_offset - 0x20;
-    
+
     intredir_offset += (intno >> 3);
     if ((intredir_offset) > env->tr.limit)
@@ -900 +900 @@
     PUSHW(ssp, esp, 0xffff, old_cs);
     PUSHW(ssp, esp, 0xffff, next_eip);
-    
+
     /* update processor state */
     ESP = (ESP & ~0xffff) | (esp & 0xffff);
@@ -932 +932 @@
 {
     int index;
-    
+
 #if 0
-    printf("TR: base=" TARGET_FMT_lx " limit=%x\n", 
+    printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
            env->tr.base, env->tr.limit);
 #endif
@@ -1052 +1052 @@
         PUSHQ(esp, error_code);
     }
-    
+
     if (new_stack) {
         ss = 0 | dpl;
@@ -1060 +1060 @@
 
     selector = (selector & ~3) | dpl;
-    cpu_x86_load_seg_cache(env, R_CS, selector, 
+    cpu_x86_load_seg_cache(env, R_CS, selector,
                    get_seg_base(e1, e2),
                    get_seg_limit(e1, e2),
@@ -1089 +1089 @@
         ECX = env->eip + next_eip_addend;
         env->regs[11] = compute_eflags();
-        
+
         code64 = env->hflags & HF_CS64_MASK;
 
         cpu_x86_set_cpl(env, 0);
-        cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, 
-                           0, 0xffffffff, 
+        cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
+                           0, 0xffffffff,
                                DESC_G_MASK | DESC_P_MASK |
                                DESC_S_MASK |
                                DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
-        cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, 
+        cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
                                0, 0xffffffff,
                                DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -1108 +1108 @@
         else
             env->eip = env->cstar;
-    } else 
+    } else
 #endif
     {
         ECX = (uint32_t)(env->eip + next_eip_addend);
-        
+
         cpu_x86_set_cpl(env, 0);
-        cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, 
-                           0, 0xffffffff, 
+        cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
+                           0, 0xffffffff,
                                DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
                                DESC_S_MASK |
                                DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
-        cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, 
+        cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
                                0, 0xffffffff,
                                DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -1144 +1144 @@
     if (env->hflags & HF_LMA_MASK) {
         if (dflag == 2) {
-            cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, 
-                                   0, 0xffffffff, 
+            cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
+                                   0, 0xffffffff,
                                    DESC_G_MASK | DESC_P_MASK |
                                    DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
-                                   DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | 
+                                   DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
                                    DESC_L_MASK);
             env->eip = ECX;
         } else {
-            cpu_x86_load_seg_cache(env, R_CS, selector | 3, 
-                                   0, 0xffffffff, 
+            cpu_x86_load_seg_cache(env, R_CS, selector | 3,
+                                   0, 0xffffffff,
                                    DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
                                    DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
@@ -1159 +1159 @@
             env->eip = (uint32_t)ECX;
         }
-        cpu_x86_load_seg_cache(env, R_SS, selector + 8, 
+        cpu_x86_load_seg_cache(env, R_SS, selector + 8,
                                0, 0xffffffff,
                                DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
                                DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
                                DESC_W_MASK | DESC_A_MASK);
-        load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK | 
+        load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
                     IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
         cpu_x86_set_cpl(env, 3);
-    } else 
+    } else
 #endif
     {
-        cpu_x86_load_seg_cache(env, R_CS, selector | 3, 
-                               0, 0xffffffff, 
+        cpu_x86_load_seg_cache(env, R_CS, selector | 3,
+                               0, 0xffffffff,
                                DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
                                DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
                                DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
         env->eip = (uint32_t)ECX;
-        cpu_x86_load_seg_cache(env, R_SS, selector + 8, 
+        cpu_x86_load_seg_cache(env, R_SS, selector + 8,
                                0, 0xffffffff,
                                DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -1196 +1196 @@
 #ifdef VBOX
 /**
- * Checks and processes external VMM events. 
+ * Checks and processes external VMM events.
  * Called by op_check_external_event() when any of the flags is set and can be serviced.
  */
@@ -1265 +1265 @@
     PUSHW(ssp, esp, 0xffff, old_cs);
     PUSHW(ssp, esp, 0xffff, old_eip);
-    
+
     /* update processor state */
     ESP = (ESP & ~0xffff) | (esp & 0xffff);
@@ -1275 +1275 @@
 
 /* fake user mode interrupt */
-void do_interrupt_user(int intno, int is_int, int error_code, 
+void do_interrupt_user(int intno, int is_int, int error_code,
                        target_ulong next_eip)
 {
@@ -1286 +1286 @@
     ptr = dt->base + (intno * 8);
     e2 = ldl_kernel(ptr + 4);
-    
+
     dpl = (e2 >> DESC_DPL_SHIFT) & 3;
     cpl = env->hflags & HF_CPL_MASK;
@@ -1303 +1303 @@
  * Begin execution of an interruption. is_int is TRUE if coming from
  * the int instruction. next_eip is the EIP value AFTER the interrupt
- * instruction. It is only relevant if is_int is TRUE.  
+ * instruction. It is only relevant if is_int is TRUE.
  */
-void do_interrupt(int intno, int is_int, int error_code, 
+void do_interrupt(int intno, int is_int, int error_code,
                   target_ulong next_eip, int is_hw)
 {
@@ -1348 +1348 @@
 #ifdef VBOX
             /* int xx *, v86 code and VME enabled? */
-            if (    (env->eflags & VM_MASK) 
+            if (    (env->eflags & VM_MASK)
                 &&  (env->cr[4] & CR4_VME_MASK)
                 &&  is_int
@@ -1368 +1368 @@
  * is_int is TRUE if coming from the int instruction. next_eip is the
  * EIP value AFTER the interrupt instruction. It is only relevant if
- * is_int is TRUE.  
+ * is_int is TRUE.
  */
-void raise_interrupt(int intno, int is_int, int error_code, 
+void raise_interrupt(int intno, int is_int, int error_code,
                      int next_eip_addend)
 {
 #if defined(VBOX) && defined(DEBUG)
-    NoDmik(Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend)));
+    NOT_DMIK(Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend)));
 #endif
     env->exception_index = intno;
@@ -1407 +1407 @@
 /* SMM support */
 
-#if defined(CONFIG_USER_ONLY) 
+#if defined(CONFIG_USER_ONLY)
 
 void do_smm_enter(void)
@@ -1427 +1427 @@
 void do_smm_enter(void)
 {
-#ifdef VBOX 
+#ifdef VBOX
     cpu_abort(env, "do_ssm_enter");
 #else /* !VBOX */
@@ -1443 +1443 @@
 
     sm_state = env->smbase + 0x8000;
-    
+
 #ifdef TARGET_X86_64
     for(i = 0; i < 6; i++) {
@@ -1461 +1461 @@
     stl_phys(sm_state + 0x7e74, env->ldt.limit);
     stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
-    
+
     stq_phys(sm_state + 0x7e88, env->idt.base);
     stl_phys(sm_state + 0x7e84, env->idt.limit);
@@ -1469 +1469 @@
     stl_phys(sm_state + 0x7e94, env->tr.limit);
     stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
-    
+
     stq_phys(sm_state + 0x7ed0, env->efer);
 
@@ -1480 +1480 @@
     stq_phys(sm_state + 0x7fc8, ESI);
     stq_phys(sm_state + 0x7fc0, EDI);
-    for(i = 8; i < 16; i++) 
+    for(i = 8; i < 16; i++)
         stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
     stq_phys(sm_state + 0x7f78, env->eip);
@@ -1508 +1508 @@
     stl_phys(sm_state + 0x7fcc, env->dr[6]);
     stl_phys(sm_state + 0x7fc8, env->dr[7]);
-    
+
     stl_phys(sm_state + 0x7fc4, env->tr.selector);
     stl_phys(sm_state + 0x7f64, env->tr.base);
     stl_phys(sm_state + 0x7f60, env->tr.limit);
     stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
-    
+
     stl_phys(sm_state + 0x7fc0, env->ldt.selector);
     stl_phys(sm_state + 0x7f80, env->ldt.base);
     stl_phys(sm_state + 0x7f7c, env->ldt.limit);
     stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
-    
+
     stl_phys(sm_state + 0x7f74, env->gdt.base);
     stl_phys(sm_state + 0x7f70, env->gdt.limit);
@@ -1556 +1556 @@
     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
-    
-    cpu_x86_update_cr0(env, 
+
+    cpu_x86_update_cr0(env,
                        env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK));
     cpu_x86_update_cr4(env, 0);
@@ -1584 +1584 @@
     for(i = 0; i < 6; i++) {
         offset = 0x7e00 + i * 16;
-        cpu_x86_load_seg_cache(env, i, 
+        cpu_x86_load_seg_cache(env, i,
                                lduw_phys(sm_state + offset),
                                ldq_phys(sm_state + offset + 8),
@@ -1598 +1598 @@
     env->ldt.limit = ldl_phys(sm_state + 0x7e74);
     env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
-    
+
     env->idt.base = ldq_phys(sm_state + 0x7e88);
     env->idt.limit = ldl_phys(sm_state + 0x7e84);
@@ -1606 +1606 @@
     env->tr.limit = ldl_phys(sm_state + 0x7e94);
     env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
-    
+
     EAX = ldq_phys(sm_state + 0x7ff8);
     ECX = ldq_phys(sm_state + 0x7ff0);
@@ -1615 +1615 @@
     ESI = ldq_phys(sm_state + 0x7fc8);
     EDI = ldq_phys(sm_state + 0x7fc0);
-    for(i = 8; i < 16; i++) 
+    for(i = 8; i < 16; i++)
         env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
     env->eip = ldq_phys(sm_state + 0x7f78);
-    load_eflags(ldl_phys(sm_state + 0x7f70), 
+    load_eflags(ldl_phys(sm_state + 0x7f70),
                 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
     env->dr[6] = ldl_phys(sm_state + 0x7f68);
@@ -1634 +1634 @@
     cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
     cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
-    load_eflags(ldl_phys(sm_state + 0x7ff4), 
+    load_eflags(ldl_phys(sm_state + 0x7ff4),
                 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
     env->eip = ldl_phys(sm_state + 0x7ff0);
@@ -1647 +1647 @@
     env->dr[6] = ldl_phys(sm_state + 0x7fcc);
     env->dr[7] = ldl_phys(sm_state + 0x7fc8);
-    
+
     env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
     env->tr.base = ldl_phys(sm_state + 0x7f64);
     env->tr.limit = ldl_phys(sm_state + 0x7f60);
     env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
-    
+
     env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
     env->ldt.base = ldl_phys(sm_state + 0x7f80);
     env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
     env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
-    
+
     env->gdt.base = ldl_phys(sm_state + 0x7f74);
     env->gdt.limit = ldl_phys(sm_state + 0x7f70);
@@ -1669 +1669 @@
         else
             offset = 0x7f2c + (i - 3) * 12;
-        cpu_x86_load_seg_cache(env, i, 
+        cpu_x86_load_seg_cache(env, i,
                                ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
                                ldl_phys(sm_state + offset + 8),
@@ -1716 +1716 @@
     unsigned int den, r;
     uint64_t num, q;
-    
+
     num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
     den = T0;
@@ -1738 +1738 @@
     int den, r;
     int64_t num, q;
-    
+
     num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
     den = T0;
@@ -1785 +1785 @@
     uint32_t index;
     index = (uint32_t)EAX;
-    
+
     /* test if maximum index reached */
     if (index & 0x80000000) {
-        if (index > env->cpuid_xlevel) 
+        if (index > env->cpuid_xlevel)
             index = env->cpuid_level;
     } else {
-        if (index > env->cpuid_level) 
+        if (index > env->cpuid_level)
             index = env->cpuid_level;
     }
-        
+
     switch(index) {
     case 0:
@@ -1940 +1940 @@
     target_ulong ptr;
 #ifdef VBOX
-    Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n", 
+    Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
          (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
-#endif 
-    
+#endif
+
     selector = T0 & 0xffff;
     if ((selector & 0xfffc) == 0) {
@@ -1958 +1958 @@
             entry_limit = 15;
         else
-#endif            
+#endif
             entry_limit = 7;
         if ((index + entry_limit) > dt->limit)
@@ -1983 +1983 @@
     env->ldt.selector = selector;
 #ifdef VBOX
-    Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n", 
+    Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
          (RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
-#endif 
+#endif
 }
 
@@ -1995 +1995 @@
     int index, type, entry_limit;
     target_ulong ptr;
-    
+
 #ifdef VBOX
-    Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n", 
-         (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit, 
+    Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
+         (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
          env->tr.flags, (RTSEL)(T0 & 0xffff)));
-#endif 
+#endif
 
     selector = T0 & 0xffff;
@@ -2017 +2017 @@
             entry_limit = 15;
         else
-#endif            
+#endif
             entry_limit = 7;
         if ((index + entry_limit) > dt->limit)
@@ -2025 +2025 @@
         e2 = ldl_kernel(ptr + 4);
         type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
-        if ((e2 & DESC_S_MASK) || 
+        if ((e2 & DESC_S_MASK) ||
             (type != 1 && type != 9))
             raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
@@ -2036 +2036 @@
             load_seg_cache_raw_dt(&env->tr, e1, e2);
             env->tr.base |= (target_ulong)e3 << 32;
-        } else 
+        } else
 #endif
         {
@@ -2046 +2046 @@
     env->tr.selector = selector;
 #ifdef VBOX
-    Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n", 
-         (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit, 
+    Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
+         (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
          env->tr.flags, (RTSEL)(T0 & 0xffff)));
-#endif 
+#endif
 }
 
@@ -2066 +2066 @@
 #ifdef VBOX
     /* Trying to load a selector with CPL=1? */
-    if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0)) 
+    if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0))
     {
         Log(("RPL 1 -> sel %04X -> %04X\n", selector, selector & 0xfffc));
@@ -2083 +2083 @@
         cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
     } else {
-        
+
         if (selector & 0x4)
             dt = &env->ldt;
@@ -2094 +2094 @@
         e1 = ldl_kernel(ptr);
         e2 = ldl_kernel(ptr + 4);
-        
+
         if (!(e2 & DESC_S_MASK))
             raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
@@ -2109 +2109 @@
             if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
                 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
-            
+
             if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
                 /* if not conforming code, test rights */
-                if (dpl < cpl || dpl < rpl) 
+                if (dpl < cpl || dpl < rpl)
                     raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
             }
@@ -2130 +2130 @@
         }
 
-        cpu_x86_load_seg_cache(env, seg_reg, selector, 
+        cpu_x86_load_seg_cache(env, seg_reg, selector,
                        get_seg_base(e1, e2),
                        get_seg_limit(e1, e2),
                        e2);
 #if 0
-        fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n", 
+        fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
                 selector, (unsigned long)sc->base, sc->limit, sc->flags);
 #endif
@@ -2147 +2147 @@
     uint32_t e1, e2, cpl, dpl, rpl, limit;
     target_ulong new_eip, next_eip;
-    
+
     new_cs = T0;
     new_eip = T1;
@@ -2174 +2174 @@
             raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
         limit = get_seg_limit(e1, e2);
-        if (new_eip > limit && 
+        if (new_eip > limit &&
             !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
             raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
@@ -2210 +2210 @@
             dpl = (e2 >> DESC_DPL_SHIFT) & 3;
             /* must be code segment */
-            if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) != 
+            if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
                  (DESC_S_MASK | DESC_CS_MASK)))
                 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
-            if (((e2 & DESC_C_MASK) && (dpl > cpl)) || 
+            if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
                 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
                 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
@@ -2321 +2321 @@
             ESP = rsp;
             cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
-                                   get_seg_base(e1, e2), 
+                                   get_seg_base(e1, e2),
                                    get_seg_limit(e1, e2), e2);
             EIP = new_eip;
-        } else 
+        } else
 #endif
         {
@@ -2337 +2337 @@
                 PUSHW(ssp, sp, sp_mask, next_eip);
             }
-            
+
             limit = get_seg_limit(e1, e2);
             if (new_eip > limit)
@@ -2396 +2396 @@
 #ifdef DEBUG_PCALL
             if (loglevel & CPU_LOG_PCALL)
-                fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n", 
+                fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
                         ss, sp, param_count, ESP);
 #endif
@@ -2418 +2418 @@
                 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
 #endif
-            
+
             //            push_size = ((param_count * 2) + 8) << shift;
 
             old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
             old_ssp = env->segs[R_SS].base;
-            
+
             sp_mask = get_sp_mask(ss_e2);
             ssp = get_seg_base(ss_e1, ss_e2);
@@ -2463 +2463 @@
         if (new_stack) {
             ss = (ss & ~3) | dpl;
-            cpu_x86_load_seg_cache(env, R_SS, ss, 
+            cpu_x86_load_seg_cache(env, R_SS, ss,
                                    ssp,
                                    get_seg_limit(ss_e1, ss_e2),
@@ -2470 +2470 @@
 
         selector = (selector & ~3) | dpl;
-        cpu_x86_load_seg_cache(env, R_CS, selector, 
+        cpu_x86_load_seg_cache(env, R_CS, selector,
                        get_seg_base(e1, e2),
                        get_seg_limit(e1, e2),
@@ -2521 +2521 @@
         /* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
         /* if TF will be set -> #GP */
-        if (    ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK)) 
-            ||  (new_eflags & TF_MASK)) 
+        if (    ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
+            ||  (new_eflags & TF_MASK))
             raise_exception(EXCP0D_GPF);
     }
@@ -2562 +2562 @@
        they may still contain a valid base. I would be interested to
        know how a real x86_64 CPU behaves */
-    if ((seg_reg == R_FS || seg_reg == R_GS) && 
+    if ((seg_reg == R_FS || seg_reg == R_GS) &&
         (env->segs[seg_reg].selector & 0xfffc) == 0)
         return;
@@ -2584 +2584 @@
     int cpl, dpl, rpl, eflags_mask, iopl;
     target_ulong ssp, sp, new_eip, new_esp, sp_mask;
-    
+
 #ifdef TARGET_X86_64
     if (shift == 2)
@@ -2622 +2622 @@
         }
 #ifdef VBOX
-        if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0)) 
+        if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
         {
 #ifdef DEBUG
@@ -2667 +2667 @@
     }
     cpl = env->hflags & HF_CPL_MASK;
-    rpl = new_cs & 3; 
+    rpl = new_cs & 3;
     if (rpl < cpl)
     {
@@ -2701 +2701 @@
     }
     sp += addend;
-    if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) || 
+    if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
                        ((env->hflags & HF_CS64_MASK) && !is_iret))) {
         /* return to same priledge level */
-        cpu_x86_load_seg_cache(env, R_CS, new_cs, 
+        cpu_x86_load_seg_cache(env, R_CS, new_cs,
                        get_seg_base(e1, e2),
                        get_seg_limit(e1, e2),
@@ -2738 +2738 @@
             /* XXX: test CS64 ? */
             if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
-                cpu_x86_load_seg_cache(env, R_SS, new_ss, 
+                cpu_x86_load_seg_cache(env, R_SS, new_ss,
                                        0, 0xffffffff,
                                        DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -2744 +2744 @@
                                        DESC_W_MASK | DESC_A_MASK);
                 ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
-            } else 
+            } else
 #endif
             {
@@ -2763 +2763 @@
             if (!(ss_e2 & DESC_P_MASK))
                 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
-            cpu_x86_load_seg_cache(env, R_SS, new_ss, 
+            cpu_x86_load_seg_cache(env, R_SS, new_ss,
                                    get_seg_base(ss_e1, ss_e2),
                                    get_seg_limit(ss_e1, ss_e2),
@@ -2769 +2769 @@
         }
 
-        cpu_x86_load_seg_cache(env, R_CS, new_cs, 
+        cpu_x86_load_seg_cache(env, R_CS, new_cs,
                        get_seg_base(e1, e2),
                        get_seg_limit(e1, e2),
@@ -2825 +2825 @@
     POPL(ssp, sp, sp_mask, new_fs);
     POPL(ssp, sp, sp_mask, new_gs);
-    
+
     /* modify processor state */
-    load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK | 
+    load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
                 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
     load_seg_vm(R_CS, new_cs & 0xffff);
@@ -2845 +2845 @@
     int tss_selector, type;
     uint32_t e1, e2;
-    
+
 #ifdef VBOX
     remR3TrapClear(env->pVM);
@@ -2896 +2896 @@
     env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
     cpu_x86_set_cpl(env, 0);
-    cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc, 
-                           0, 0xffffffff, 
+    cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
+                           0, 0xffffffff,
                            DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
                            DESC_S_MASK |
                            DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
-    cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, 
+    cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
                            0, 0xffffffff,
                            DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -2919 +2919 @@
     }
     cpu_x86_set_cpl(env, 3);
-    cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3, 
-                           0, 0xffffffff, 
+    cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
+                           0, 0xffffffff,
                            DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
                            DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
                            DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
-    cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3, 
+    cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
                            0, 0xffffffff,
                            DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
@@ -2941 +2941 @@
 void helper_movl_crN_T0(int reg)
 {
-#if !defined(CONFIG_USER_ONLY) 
+#if !defined(CONFIG_USER_ONLY)
     switch(reg) {
     case 0:
@@ -2985 +2985 @@
 }
 
-#if defined(CONFIG_USER_ONLY) 
+#if defined(CONFIG_USER_ONLY)
 void helper_wrmsr(void)
 {
@@ -3025 +3025 @@
             if (env->cpuid_ext2_features & CPUID_EXT2_NX)
                 update_mask |= MSR_EFER_NXE;
-            env->efer = (env->efer & ~update_mask) | 
+            env->efer = (env->efer & ~update_mask) |
             (val & update_mask);
         }
@@ -3057 +3057 @@
     default:
         /* XXX: exception ? */
-        break; 
+        break;
     }
 }
@@ -3109 +3109 @@
         /* XXX: exception ? */
         val = 0;
-        break; 
+        break;
     }
     EAX = (uint32_t)(val);
@@ -3296 +3296 @@
 CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
 {
-    if (b == 0.0) 
+    if (b == 0.0)
         fpu_set_exception(FPUS_ZE);
     return a / b;
@@ -3305 +3305 @@
     if (env->cr[0] & CR0_NE_MASK) {
         raise_exception(EXCP10_COPR);
-    } 
-#if !defined(CONFIG_USER_ONLY) 
+    }
+#if !defined(CONFIG_USER_ONLY)
     else {
         cpu_set_ferr(env);
@@ -3370 +3370 @@
 {
     CPU86_LDouble fptemp;
-    
+
     fptemp = ST0;
     if (fptemp>0.0){
@@ -3376 +3376 @@
         ST1 *= fptemp;
         fpop();
-    } else { 
+    } else {
         env->fpus &= (~0x4700);
         env->fpus |= 0x400;
@@ -3461 +3461 @@
     int expdif;
     int q;
-    
+
     fpsrcop = ST0;
     fptemp = ST1;
@@ -3497 +3497 @@
         ST1 *= fptemp;
         fpop();
-    } else { 
+    } else {
         env->fpus &= (~0x4700);
         env->fpus |= 0x400;
@@ -3508 +3508 @@
 
     fptemp = ST0;
-    if (fptemp<0.0) { 
+    if (fptemp<0.0) {
         env->fpus &= (~0x4700);  /* (C3,C2,C1,C0) <-- 0000 */
         env->fpus |= 0x400;
@@ -3538 +3538 @@
 void helper_fscale(void)
 {
-    ST0 = ldexp (ST0, (int)(ST1)); 
+    ST0 = ldexp (ST0, (int)(ST1));
 }
 
@@ -3737 +3737 @@
         addr += 16;
     }
-    
+
     if (env->cr[4] & CR4_OSFXSR_MASK) {
         /* XXX: finish it */
@@ -3797 +3797 @@
             u64 = ldq(addr + 4);
                         env->xmm_regs[i].XMM_Q(1) = u64;
-# endif                 
+# endif
 #endif
             addr += 16;
@@ -3890 +3890 @@
     b0 = b;
     b1 = b >> 32;
-    
+
     v = (uint64_t)a0 * (uint64_t)b0;
     *plow = v;
@@ -3897 +3897 @@
     v = (uint64_t)a0 * (uint64_t)b1;
     add128(plow, phigh, v << 32, v >> 32);
-    
+
     v = (uint64_t)a1 * (uint64_t)b0;
     add128(plow, phigh, v << 32, v >> 32);
-    
+
     v = (uint64_t)a1 * (uint64_t)b1;
     *phigh += v;
@@ -4133 +4133 @@
 }
 
-#if !defined(CONFIG_USER_ONLY) 
+#if !defined(CONFIG_USER_ONLY)
 
 #define MMUSUFFIX _mmu
@@ -4314 +4314 @@
                 uint32_t e1, e2;
                 load_segment(&e1, &e2, selector);
-                cpu_x86_load_seg_cache(env, R_CS, selector, 
+                cpu_x86_load_seg_cache(env, R_CS, selector,
                                get_seg_base(e1, e2),
                                get_seg_limit(e1, e2),
@@ -4326 +4326 @@
             env1->segs[seg_reg].newselector = 0;
         }
-        else 
+        else
         {
             env = savedenv;
@@ -4342 +4342 @@
 /**
  * Correctly loads a new ldtr selector.
- * 
+ *
  * @param   env1        CPU environment.
  * @param   selector    Selector to load.
@@ -4358 +4358 @@
         env = saved_env;
     }
-    else 
+    else
     {
         T0 = saved_T0;
@@ -4364 +4364 @@
 #ifdef VBOX_STRICT
         cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
-#endif 
+#endif
     }
 }
@@ -4370 +4370 @@
 /**
  * Correctly loads a new tr selector.
- * 
+ *
  * @param   env1        CPU environment.
  * @param   selector    Selector to load.
@@ -4399 +4399 @@
             entry_limit = 15;
         else
-#endif            
+#endif
             entry_limit = 7;
         if ((index + entry_limit) > dt->limit)
@@ -4407 +4407 @@
         e2 = ldl_kernel(ptr + 4);
         type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
-        if ((e2 & DESC_S_MASK) /*|| 
+        if ((e2 & DESC_S_MASK) /*||
             (type != 1 && type != 9)*/)
             goto l_failure;
@@ -4418 +4418 @@
             load_seg_cache_raw_dt(&env->tr, e1, e2);
             env->tr.base |= (target_ulong)e3 << 32;
-        } else 
+        } else
 #endif
         {
@@ -4438 +4438 @@
 {
 #if 1 /* single stepping is broken when using a static tb... feel free to figure out why. :-) */
-    /* This has to be static because it needs to be addressible 
+    /* This has to be static because it needs to be addressible
        using 32-bit immediate addresses on 64-bit machines. This
        is dictated by the gcc code model used when building this
-       module / op.o. Using a static here pushes the problem 
+       module / op.o. Using a static here pushes the problem
        onto the module loader. */
-    static TranslationBlock tb_temp; 
+    static TranslationBlock tb_temp;
 #endif
     TranslationBlock *tb;
@@ -4455 +4455 @@
     CPUX86State *savedenv = env;
     env = env1;
-    
+
     RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
 
@@ -4474 +4474 @@
 #else
     tb = tb_alloc(env->segs[R_CS].base + env->eip);
-    if (!tb) 
+    if (!tb)
     {
         tb_flush(env);
@@ -4504 +4504 @@
     env->current_tb = NULL;
 
-    /* 
+    /*
      * Translate only one instruction.
      */
@@ -4551 +4551 @@
     env->current_tb = tb;
 
-    // eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code 
+    // eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
     // perhaps not a very safe hack
     while(old_eip == env->eip)
@@ -4582 +4582 @@
     Assert(tb->jmp_next[1] == NULL);
     Assert(tb->jmp_first == NULL); */
-    
+
     RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
 
-    /*                                                              
+    /*
      * Execute the next instruction when we encounter instruction fusing.
      */
@@ -4599 +4599 @@
 }
 
-int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr, 
+int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr,
                              uint32_t *esp_ptr, int dpl)
 {
@@ -4678 +4678 @@
             addr += 16;
         }
-    
+
         if (env->cr[4] & CR4_OSFXSR_MASK) {
             /* XXX: finish it */
@@ -4694 +4694 @@
                 stl(addr + 8, env->xmm_regs[i].XMM_L(2));
                 stl(addr + 12, env->xmm_regs[i].XMM_L(3));
-#endif 
+#endif
                 addr += 16;
             }