VirtualBox

Ignore:
Timestamp:
Aug 12, 2020 4:09:12 PM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
139865
Message:

Devices/EFI: Merge edk-stable202005 and make it build, bugref:4643

Location:
trunk/src/VBox/Devices/EFI/FirmwareNew
Files:
1 added
9 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/EFI/FirmwareNew

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/AmdSev.c

    r80721 r85718  
    1010// The package level header files this module uses
    1111//
     12#include <IndustryStandard/Q35MchIch9.h>
    1213#include <Library/DebugLib.h>
    1314#include <Library/HobLib.h>
    … …  
    1718#include <Register/Amd/Cpuid.h>
    1819#include <Register/Cpuid.h>
     20#include <Register/Intel/SmramSaveStateMap.h>
    1921
    2022#include "Platform.h"
    … …  
    8486    ASSERT_RETURN_ERROR (LocateMapStatus);
    8587
    86     BuildMemoryAllocationHob (
    87       MapPagesBase,                      // BaseAddress
    88       EFI_PAGES_TO_SIZE (MapPagesCount), // Length
    89       EfiBootServicesData                // MemoryType
    90       );
     88    if (mQ35SmramAtDefaultSmbase) {
     89      //
     90      // The initial SMRAM Save State Map has been covered as part of a larger
     91      // reserved memory allocation in InitializeRamRegions().
     92      //
     93      ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);
     94      ASSERT (
     95        (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=
     96         SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)
     97        );
     98    } else {
     99      BuildMemoryAllocationHob (
     100        MapPagesBase,                      // BaseAddress
     101        EFI_PAGES_TO_SIZE (MapPagesCount), // Length
     102        EfiBootServicesData                // MemoryType
     103        );
     104    }
    91105  }
    92106}

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/FeatureControl.c

    r80721 r85718  
    6464  EFI_STATUS              Status;
    6565
    66   DEBUG ((EFI_D_VERBOSE, "%a: %a\n", gEfiCallerBaseName, __FUNCTION__));
     66  DEBUG ((DEBUG_VERBOSE, "%a: %a\n", gEfiCallerBaseName, __FUNCTION__));
    6767
    6868  //
    … …  
    7979                         );
    8080  if (EFI_ERROR (Status) && Status != EFI_NOT_STARTED) {
    81     DEBUG ((EFI_D_ERROR, "%a: StartupAllAps(): %r\n", __FUNCTION__, Status));
     81    DEBUG ((DEBUG_ERROR, "%a: StartupAllAps(): %r\n", __FUNCTION__, Status));
    8282    return Status;
    8383  }
    … …  
    123123  Status = PeiServicesNotifyPpi (&mMpServicesNotify);
    124124  if (EFI_ERROR (Status)) {
    125     DEBUG ((EFI_D_ERROR, "%a: failed to set up MP Services callback: %r\n",
     125    DEBUG ((DEBUG_ERROR, "%a: failed to set up MP Services callback: %r\n",
    126126      __FUNCTION__, Status));
    127127  }

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/Fv.c

    r82249 r85718  
    3434#endif
    3535
    36   DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n"));
     36  DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
    3737
    3838#ifdef VBOX

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/MemDetect.c

    r82249 r85718  
    1818#include <IndustryStandard/Q35MchIch9.h>
    1919#include <PiPei.h>
     20#include <Register/Intel/SmramSaveStateMap.h>
    2021
    2122//
    … …  
    3334#include <Library/MtrrLib.h>
    3435#include <Library/QemuFwCfgLib.h>
     36#include <Library/QemuFwCfgSimpleParserLib.h>
    3537
    3638#include "Platform.h"
    … …  
    4446STATIC UINT16 mQ35TsegMbytes;
    4547
     48BOOLEAN mQ35SmramAtDefaultSmbase;
     49
    4650UINT32 mQemuUc32Base;
    4751
    … …  
    5458  RETURN_STATUS PcdStatus;
    5559
    56   if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
    57     DEBUG ((
    58       DEBUG_ERROR,
    59       "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
    60       "only DID=0x%04x (Q35) is supported\n",
    61       __FUNCTION__,
    62       mHostBridgeDevId,
    63       INTEL_Q35_MCH_DEVICE_ID
    64       ));
    65     ASSERT (FALSE);
    66     CpuDeadLoop ();
    67   }
     60  ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
    6861
    6962  //
    … …  
    9992  ASSERT_RETURN_ERROR (PcdStatus);
    10093  mQ35TsegMbytes = ExtendedTsegMbytes;
     94}
     95
     96
     97VOID
     98Q35SmramAtDefaultSmbaseInitialization (
     99  VOID
     100  )
     101{
     102  RETURN_STATUS PcdStatus;
     103
     104  ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
     105
     106  mQ35SmramAtDefaultSmbase = FALSE;
     107  if (FeaturePcdGet (PcdCsmEnable)) {
     108    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE not checked due to CSM\n",
     109      __FUNCTION__));
     110  } else {
     111    UINTN CtlReg;
     112    UINT8 CtlRegVal;
     113
     114    CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);
     115    PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);
     116    CtlRegVal = PciRead8 (CtlReg);
     117    mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
     118                                         MCH_DEFAULT_SMBASE_IN_RAM);
     119    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__,
     120      mQ35SmramAtDefaultSmbase ? "found" : "not found"));
     121  }
     122
     123  PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,
     124                mQ35SmramAtDefaultSmbase);
     125  ASSERT_RETURN_ERROR (PcdStatus);
    101126}
    102127
    … …  
    318343  UINT64               FirstNonAddress;
    319344  UINT64               Pci64Base, Pci64Size;
    320   CHAR8                MbString[7 + 1];
     345  UINT32               FwCfgPciMmio64Mb;
    321346  EFI_STATUS           Status;
    322347  FIRMWARE_CONFIG_ITEM FwCfgItem;
    … …  
    361386  //
    362387  // See if the user specified the number of megabytes for the 64-bit PCI host
    363   // aperture. The number of non-NUL characters in MbString allows for
    364   // 9,999,999 MB, which is approximately 10 TB.
     388  // aperture. Accept an aperture size up to 16TB.
    365389  //
    366390  // As signaled by the "X-" prefix, this knob is experimental, and might go
    367391  // away at any time.
    368392  //
    369   Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,
    370              &FwCfgSize);
    371   if (!EFI_ERROR (Status)) {
    372     if (FwCfgSize >= sizeof MbString) {
    373       DEBUG ((EFI_D_WARN,
    374         "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
    375         __FUNCTION__));
    376     } else {
    377       QemuFwCfgSelectItem (FwCfgItem);
    378       QemuFwCfgReadBytes (FwCfgSize, MbString);
    379       MbString[FwCfgSize] = '\0';
    380       Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);
     393  Status = QemuFwCfgParseUint32 ("opt/ovmf/X-PciMmio64Mb", FALSE,
     394             &FwCfgPciMmio64Mb);
     395  switch (Status) {
     396  case EFI_UNSUPPORTED:
     397  case EFI_NOT_FOUND:
     398    break;
     399  case EFI_SUCCESS:
     400    if (FwCfgPciMmio64Mb <= 0x1000000) {
     401      Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
     402      break;
    381403    }
     404    //
     405    // fall through
     406    //
     407  default:
     408    DEBUG ((DEBUG_WARN,
     409      "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
     410      __FUNCTION__));
     411    break;
    382412  }
    383413
    384414  if (Pci64Size == 0) {
    385415    if (mBootMode != BOOT_ON_S3_RESUME) {
    386       DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",
     416      DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",
    387417        __FUNCTION__));
    388418      PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
    … …  
    442472    ASSERT_RETURN_ERROR (PcdStatus);
    443473
    444     DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
     474    DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
    445475      __FUNCTION__, Pci64Base, Pci64Size));
    446476  }
    … …  
    602632  } else {
    603633    PeiMemoryCap = GetPeiMemoryCap ();
    604     DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
     634    DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
    605635      __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
    606636
    … …  
    629659
    630660  //
     661  // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the
     662  // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
     663  // permanent PEI RAM is located even higher.
     664  //
     665  if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
     666    ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);
     667  }
     668
     669  //
    631670  // Publish this memory to the PEI Core
    632671  //
    … …  
    639678
    640679#ifndef VBOX
     680STATIC
     681VOID
     682QemuInitializeRamBelow1gb (
     683  VOID
     684  )
     685{
     686  if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
     687    AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);
     688    AddReservedMemoryBaseSizeHob (SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE,
     689      TRUE /* Cacheable */);
     690    STATIC_ASSERT (
     691      SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,
     692      "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
     693      );
     694    AddMemoryRangeHob (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,
     695      BASE_512KB + BASE_128KB);
     696  } else {
     697    AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
     698  }
     699}
     700
     701
    641702/**
    642703  Peform Memory Detection for QEMU / KVM
    … …  
    654715  EFI_STATUS                  Status;
    655716
    656   DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));
     717  DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));
    657718
    658719  //
    … …  
    683744    // looking for an area to borrow.
    684745    //
    685     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
     746    QemuInitializeRamBelow1gb ();
    686747  } else {
    687748    //
    688749    // Create memory HOBs
    689750    //
    690     AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
     751    QemuInitializeRamBelow1gb ();
    691752
    692753    if (FeaturePcdGet (PcdSmmSmramRequire)) {
    … …  
    923984        EfiReservedMemoryType
    924985        );
     986      //
     987      // Similarly, allocate away the (already reserved) SMRAM at the default
     988      // SMBASE, if it exists.
     989      //
     990      if (mQ35SmramAtDefaultSmbase) {
     991        BuildMemoryAllocationHob (
     992          SMM_DEFAULT_SMBASE,
     993          MCH_DEFAULT_SMBASE_SIZE,
     994          EfiReservedMemoryType
     995          );
     996      }
    925997    }
    926998  }

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/Platform.c

    r82104 r85718  
    2828#include <Library/QemuFwCfgLib.h>
    2929#include <Library/QemuFwCfgS3Lib.h>
     30#include <Library/QemuFwCfgSimpleParserLib.h>
    3031#include <Library/ResourcePublicationLib.h>
    31 #include <Guid/MemoryTypeInformation.h>
    3232#include <Ppi/MasterBootMode.h>
     33#include <IndustryStandard/I440FxPiix4.h>
    3334#include <IndustryStandard/Pci22.h>
     35#include <IndustryStandard/Q35MchIch9.h>
     36#include <IndustryStandard/QemuCpuHotplug.h>
    3437#include <OvmfPlatforms.h>
    3538
    … …  
    4245# include "iprt/asm.h"
    4346#endif
    44 
    45 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
    46   { EfiACPIMemoryNVS,       0x004 },
    47   { EfiACPIReclaimMemory,   0x008 },
    48   { EfiReservedMemoryType,  0x004 },
    49   { EfiRuntimeServicesData, 0x024 },
    50   { EfiRuntimeServicesCode, 0x030 },
    51   { EfiBootServicesCode,    0x180 },
    52   { EfiBootServicesData,    0xF00 },
    53   { EfiMaxMemoryType,       0x000 }
    54 };
    55 
    5647
    5748EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
    … …  
    236227
    237228  //
    238   // Create Memory Type Information HOB
    239   //
    240   BuildGuidDataHob (
    241     &gEfiMemoryTypeInformationGuid,
    242     mDefaultMemoryTypeInformation,
    243     sizeof(mDefaultMemoryTypeInformation)
    244     );
    245 
    246   //
    247229  // Video memory + Legacy BIOS region
    248230#ifdef VBOX
    … …  
    397379}
    398380
    399 EFI_STATUS
    400 GetNamedFwCfgBoolean (
    401   IN  CHAR8   *FwCfgFileName,
    402   OUT BOOLEAN *Setting
    403   )
    404 {
    405   EFI_STATUS           Status;
    406   FIRMWARE_CONFIG_ITEM FwCfgItem;
    407   UINTN                FwCfgSize;
    408   UINT8                Value[3];
    409 
    410   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
    411   if (EFI_ERROR (Status)) {
    412     return Status;
    413   }
    414   if (FwCfgSize > sizeof Value) {
    415     return EFI_BAD_BUFFER_SIZE;
    416   }
    417   QemuFwCfgSelectItem (FwCfgItem);
    418   QemuFwCfgReadBytes (FwCfgSize, Value);
    419 
    420   if ((FwCfgSize == 1) ||
    421       (FwCfgSize == 2 && Value[1] == '\n') ||
    422       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
    423     switch (Value[0]) {
    424       case '0':
    425       case 'n':
    426       case 'N':
    427         *Setting = FALSE;
    428         return EFI_SUCCESS;
    429 
    430       case '1':
    431       case 'y':
    432       case 'Y':
    433         *Setting = TRUE;
    434         return EFI_SUCCESS;
    435 
    436       default:
    437         break;
    438     }
    439   }
    440   return EFI_PROTOCOL_ERROR;
    441 }
    442 
    443381#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
    444382          do {                                                      \
    … …  
    446384            RETURN_STATUS PcdStatus;                                \
    447385                                                                    \
    448             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
     386            if (!RETURN_ERROR (QemuFwCfgParseBool (                 \
    449387                              "opt/ovmf/" #TokenName, &Setting))) { \
    450388              PcdStatus = PcdSetBoolS (TokenName, Setting);         \
    … …  
    458396  )
    459397{
    460   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
    461398  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
    462399}
    … …  
    555492      break;
    556493    default:
    557       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
     494      DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
    558495        __FUNCTION__, mHostBridgeDevId));
    559496      ASSERT (FALSE);
    … …  
    651588        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
    652589        );
    653   DEBUG ((EFI_D_INFO,
     590  DEBUG ((DEBUG_INFO,
    654591          "Reserved variable store memory: 0x%lX; size: %dkb\n",
    655592          VariableStore,
    … …  
    668605  UINT32 Loop;
    669606
    670   DEBUG ((EFI_D_INFO, "CMOS:\n"));
     607  DEBUG ((DEBUG_INFO, "CMOS:\n"));
    671608
    672609  for (Loop = 0; Loop < 0x80; Loop++) {
    673610    if ((Loop % 0x10) == 0) {
    674       DEBUG ((EFI_D_INFO, "%02x:", Loop));
     611      DEBUG ((DEBUG_INFO, "%02x:", Loop));
    675612    }
    676     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
     613    DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
    677614    if ((Loop % 0x10) == 0xf) {
    678       DEBUG ((EFI_D_INFO, "\n"));
     615      DEBUG ((DEBUG_INFO, "\n"));
    679616    }
    680617  }
    … …  
    689626#if defined (MDE_CPU_X64)
    690627  if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
    691     DEBUG ((EFI_D_ERROR,
     628    DEBUG ((DEBUG_ERROR,
    692629      "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
    693     DEBUG ((EFI_D_ERROR,
     630    DEBUG ((DEBUG_ERROR,
    694631      "%a: Please disable S3 on the QEMU command line (see the README),\n",
    695632      __FUNCTION__));
    696     DEBUG ((EFI_D_ERROR,
     633    DEBUG ((DEBUG_ERROR,
    697634      "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
    698635    ASSERT (FALSE);
    … …  
    703640
    704641
     642VOID
     643Q35BoardVerification (
     644  VOID
     645  )
     646{
     647  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
     648    return;
     649  }
     650
     651  DEBUG ((
     652    DEBUG_ERROR,
     653    "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
     654    "only DID=0x%04x (Q35) is supported\n",
     655    __FUNCTION__,
     656    mHostBridgeDevId,
     657    INTEL_Q35_MCH_DEVICE_ID
     658    ));
     659  ASSERT (FALSE);
     660  CpuDeadLoop ();
     661}
     662
     663
    705664/**
    706   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
    707   Set the mMaxCpuCount variable.
     665  Fetch the boot CPU count and the possible CPU count from QEMU, and expose
     666  them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
    708667**/
    709668VOID
    … …  
    712671  )
    713672{
    714   UINT16        ProcessorCount;
     673  UINT16        BootCpuCount;
    715674  RETURN_STATUS PcdStatus;
    716675
     676  //
     677  // Try to fetch the boot CPU count.
     678  //
    717679  QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
    718   ProcessorCount = QemuFwCfgRead16 ();
    719   //
    720   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
    721   // from the PCD default. No change to PCDs.
    722   //
    723   if (ProcessorCount == 0) {
     680  BootCpuCount = QemuFwCfgRead16 ();
     681  if (BootCpuCount == 0) {
     682    //
     683    // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
     684    // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
     685    // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
     686    // first).
     687    //
     688    DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
    724689    mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
    725     return;
    726   }
    727   //
    728   // Otherwise, set mMaxCpuCount to the value reported by QEMU.
    729   //
    730   mMaxCpuCount = ProcessorCount;
    731   //
    732   // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
    733   // to wait, in the initial AP bringup, exactly as long as it takes for all of
    734   // the APs to report in. For this, we set the longest representable timeout
    735   // (approx. 71 minutes).
    736   //
    737   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);
     690  } else {
     691    //
     692    // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
     693    // (BootCpuCount - 1) precisely, regardless of timeout.
     694    //
     695    // Now try to fetch the possible CPU count.
     696    //
     697    UINTN CpuHpBase;
     698    UINT32 CmdData2;
     699
     700    CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
     701                 ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
     702
     703    //
     704    // If only legacy mode is available in the CPU hotplug register block, or
     705    // the register block is completely missing, then the writes below are
     706    // no-ops.
     707    //
     708    // 1. Switch the hotplug register block to modern mode.
     709    //
     710    IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
     711    //
     712    // 2. Select a valid CPU for deterministic reading of
     713    //    QEMU_CPUHP_R_CMD_DATA2.
     714    //
     715    //    CPU#0 is always valid; it is the always present and non-removable
     716    //    BSP.
     717    //
     718    IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
     719    //
     720    // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
     721    //    read as zero, and which does not invalidate the selector. (The
     722    //    selector may change, but it must not become invalid.)
     723    //
     724    //    Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
     725    //
     726    IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
     727    //
     728    // 4. Read QEMU_CPUHP_R_CMD_DATA2.
     729    //
     730    //    If the register block is entirely missing, then this is an unassigned
     731    //    IO read, returning all-bits-one.
     732    //
     733    //    If only legacy mode is available, then bit#0 stands for CPU#0 in the
     734    //    "CPU present bitmap". CPU#0 is always present.
     735    //
     736    //    Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
     737    //    all-bits-zero), or it is specified to read as zero after the above
     738    //    steps. Both cases confirm modern mode.
     739    //
     740    CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
     741    DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
     742    if (CmdData2 != 0) {
     743      //
     744      // QEMU doesn't support the modern CPU hotplug interface. Assume that the
     745      // possible CPU count equals the boot CPU count (precluding hotplug).
     746      //
     747      DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",
     748        __FUNCTION__));
     749      mMaxCpuCount = BootCpuCount;
     750    } else {
     751      //
     752      // Grab the possible CPU count from the modern CPU hotplug interface.
     753      //
     754      UINT32 Present, Possible, Selected;
     755
     756      Present = 0;
     757      Possible = 0;
     758
     759      //
     760      // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
     761      // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
     762      // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
     763      // hotplug events; therefore, select CPU#0 forcibly.
     764      //
     765      IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
     766
     767      do {
     768        UINT8 CpuStatus;
     769
     770        //
     771        // Read the status of the currently selected CPU. This will help with a
     772        // sanity check against "BootCpuCount".
     773        //
     774        CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
     775        if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
     776          ++Present;
     777        }
     778        //
     779        // Attempt to select the next CPU.
     780        //
     781        ++Possible;
     782        IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
     783        //
     784        // If the selection is successful, then the following read will return
     785        // the selector (which we know is positive at this point). Otherwise,
     786        // the read will return 0.
     787        //
     788        Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
     789        ASSERT (Selected == Possible || Selected == 0);
     790      } while (Selected > 0);
     791
     792      //
     793      // Sanity check: fw_cfg and the modern CPU hotplug interface should
     794      // return the same boot CPU count.
     795      //
     796      if (BootCpuCount != Present) {
     797        DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
     798          "Present=%u\n", __FUNCTION__, BootCpuCount, Present));
     799        //
     800        // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
     801        // platform reset (including S3), was corrected in QEMU commit
     802        // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
     803        // CPUs", 2016-11-16), part of release v2.8.0.
     804        //
     805        BootCpuCount = (UINT16)Present;
     806      }
     807
     808      mMaxCpuCount = Possible;
     809    }
     810  }
     811
     812  DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,
     813    BootCpuCount, mMaxCpuCount));
     814  ASSERT (BootCpuCount <= mMaxCpuCount);
     815
     816  PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
    738817  ASSERT_RETURN_ERROR (PcdStatus);
    739   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);
     818  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);
    740819  ASSERT_RETURN_ERROR (PcdStatus);
    741   DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,
    742     ProcessorCount));
    743820}
    744821
    … …  
    772849
    773850  if (QemuFwCfgS3Enabled ()) {
    774     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
     851    DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
    775852    mS3Supported = TRUE;
    776853    Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
    … …  
    781858  BootModeInitialization ();
    782859  AddressWidthInitialization ();
    783   MaxCpuCountInitialization ();
    784860
    785861  //
    … …  
    794870#endif
    795871
     872  MaxCpuCountInitialization ();
     873
    796874  if (FeaturePcdGet (PcdSmmSmramRequire)) {
     875    Q35BoardVerification ();
    797876    Q35TsegMbytesInitialization ();
     877    Q35SmramAtDefaultSmbaseInitialization ();
    798878  }
    799879
    … …  
    805885
    806886  if (mXen) {
    807     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
     887    DEBUG ((DEBUG_INFO, "Xen was detected\n"));
    808888    InitializeXen ();
    809889  }
    … …  
    839919    }
    840920    PeiFvInitialization ();
     921    MemTypeInfoInitialization ();
    841922    MemMapInitialization ();
    842923    NoexecDxeInitialization ();

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/Platform.h

    r80721 r85718  
    5353  );
    5454
     55VOID
     56Q35SmramAtDefaultSmbaseInitialization (
     57  VOID
     58  );
     59
    5560EFI_STATUS
    5661PublishPeiMemory (
    … …  
    7580EFI_STATUS
    7681PeiFvInitialization (
     82  VOID
     83  );
     84
     85VOID
     86MemTypeInfoInitialization (
    7787  VOID
    7888  );
    … …  
    120130extern UINT16 mHostBridgeDevId;
    121131
     132extern BOOLEAN mQ35SmramAtDefaultSmbase;
     133
    122134extern UINT32 mQemuUc32Base;
    123135

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/PlatformPei.inf

    r80721 r85718  
    3131  Fv.c
    3232  MemDetect.c
     33  MemTypeInfo.c
    3334  Platform.c
    3435  Platform.h
    … …  
    3738
    3839[Packages]
     40  EmbeddedPkg/EmbeddedPkg.dec
    3941  MdePkg/MdePkg.dec
    4042  MdeModulePkg/MdeModulePkg.dec
    … …  
    6163  QemuFwCfgLib
    6264  QemuFwCfgS3Lib
     65  QemuFwCfgSimpleParserLib
    6366  MtrrLib
    6467  MemEncryptSevLib
    … …  
    8689  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd
    8790  gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
     91  gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase
    8892  gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
    8993  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
    … …  
    9599  gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
    96100  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack
    97   gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable
    98101  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable
    99102  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
    … …  
    101104  gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
    102105  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
    103   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds
     106  gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber
    104107  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize
    105108
    106109#[FixedPcd]
    107110#  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
     111  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
     112  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
     113  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
     114  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
     115  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
    108116
    109117[FeaturePcd]
     118  gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable
    110119  gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire
    111120
    … …  
    113122  gEfiPeiMasterBootModePpiGuid
    114123  gEfiPeiMpServicesPpiGuid
     124  gEfiPeiReadOnlyVariable2PpiGuid
    115125
    116126[Depex]

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/PlatformPei/Xen.c

    r80721 r85718  
    9494
    9595  AsmCpuid (XenLeaf + 1, &XenVersion, NULL, NULL, NULL);
    96   DEBUG ((EFI_D_ERROR, "Detected Xen version %d.%d\n",
     96  DEBUG ((DEBUG_ERROR, "Detected Xen version %d.%d\n",
    9797          XenVersion >> 16, XenVersion & 0xFFFF));
    9898  mXenInfo.VersionMajor = (UINT16)(XenVersion >> 16);
    … …  
    158158  }
    159159
    160   DEBUG ((EFI_D_INFO, "Using memory map provided by Xen\n"));
     160  DEBUG ((DEBUG_INFO, "Using memory map provided by Xen\n"));
    161161
    162162  //
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