Changeset 85912 in vbox for trunk/src/VBox/Devices/PC
- Timestamp:
- Aug 28, 2020 7:17:55 AM (4 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevACPI.cpp (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/PC/DevACPI.cpp
r85855 r85912 37 37 # include <iprt/uuid.h> 38 38 #endif /* IN_RING3 */ 39 #ifdef VBOX_WITH_IOMMU_AMD 40 # include <VBox/iommu-amd.h> 41 #endif 39 42 40 43 #include "VBoxDD.h" 44 #ifdef VBOX_WITH_IOMMU_AMD 45 # include "../Bus/DevIommuAmd.h" 46 #endif 41 47 42 48 #ifdef LOG_ENABLED … … 784 790 785 791 #ifdef VBOX_WITH_IOMMU_AMD 786 /** @name IVRS format revision field.787 * In accordance with the AMD spec.788 * @{ */789 /** Fixed: Supports only pre-assigned device IDs and type 10h and 11h IVHD790 * blocks. */791 #define ACPI_IVRS_FMT_REV_FIXED 0x1792 /** Mixed: Supports pre-assigned and ACPI HID device naming and all IVHD blocks. */793 #define ACPI_IVRS_FMT_REV_MIXED 0x2794 /** @} */795 796 /** @name IVHD special device entry variety field.797 * In accordance with the AMD spec.798 * @{ */799 /** I/O APIC. */800 #define ACPI_IVHD_VARIETY_IOAPIC 0x1801 /** HPET. */802 #define ACPI_IVHD_VARIETY_HPET 0x2803 /** @} */804 805 /** @name IVHD device entry type codes.806 * In accordance with the AMD spec.807 * @{ */808 /** Reserved. */809 #define ACPI_IVHD_DEVENTRY_TYPE_RSVD 0x0810 /** All: DTE setting applies to all Device IDs. */811 #define ACPI_IVHD_DEVENTRY_TYPE_ALL 0x1812 /** Select: DTE setting applies to the device specified in DevId field. */813 #define ACPI_IVHD_DEVENTRY_TYPE_SELECT 0x2814 /** Start of range: DTE setting applies to all devices from start of range specified815 * by the DevId field. */816 #define ACPI_IVHD_DEVENTRY_TYPE_START_RANGE 0x3817 /** End of range: DTE setting from previous type 3 entry applies to all devices818 * incl. DevId specified by this entry. */819 #define ACPI_IVHD_DEVENTRY_TYPE_END_RANGE 0x4820 /** @} */821 822 /** @name IVHD DTE (Device Table Entry) Settings.823 * In accordance with the AMD spec.824 * @{ */825 /** INITPass: Identifies a device able to assert INIT interrupts. */826 #define ACPI_IVHD_DTE_INIT_PASS_SHIFT 0827 #define ACPI_IVHD_DTE_INIT_PASS_MASK UINT8_C(0x01)828 /** EIntPass: Identifies a device able to assert ExtInt interrupts. */829 #define ACPI_IVHD_DTE_EXTINT_PASS_SHIFT 1830 #define ACPI_IVHD_DTE_EXTINT_PASS_MASK UINT8_C(0x02)831 /** NMIPass: Identifies a device able to assert NMI interrupts. */832 #define ACPI_IVHD_DTE_NMI_PASS_SHIFT 2833 #define ACPI_IVHD_DTE_NMI_PASS_MASK UINT8_C(0x04)834 /** Bit 3 reserved. */835 #define ACPI_IVHD_DTE_RSVD_3_SHIFT 3836 #define ACPI_IVHD_DTE_RSVD_3_MASK UINT8_C(0x08)837 /** SysMgt: Identifies a device able to assert system management messages. */838 #define ACPI_IVHD_DTE_SYS_MGT_SHIFT 4839 #define ACPI_IVHD_DTE_SYS_MGT_MASK UINT8_C(0x30)840 /** Lint0Pass: Identifies a device able to assert LINT0 interrupts. */841 #define ACPI_IVHD_DTE_LINT0_PASS_SHIFT 6842 #define ACPI_IVHD_DTE_LINT0_PASS_MASK UINT8_C(0x40)843 /** Lint0Pass: Identifies a device able to assert LINT1 interrupts. */844 #define ACPI_IVHD_DTE_LINT1_PASS_SHIFT 7845 #define ACPI_IVHD_DTE_LINT1_PASS_MASK UINT8_C(0x80)846 RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVHD_DTE_, UINT8_C(0), UINT8_MAX,847 (INIT_PASS, EXTINT_PASS, NMI_PASS, RSVD_3, SYS_MGT, LINT0_PASS, LINT1_PASS));848 /** @} */849 850 /** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry851 * (4-byte). In accordance with the AMD spec. */852 typedef struct ACPIIVHDDEVENTRY4853 {854 uint8_t u8DevEntryType; /**< Device entry type. */855 uint16_t u16DevId; /**< Device ID. */856 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */857 } ACPIIVHDDEVENTRY4;858 AssertCompileSize(ACPIIVHDDEVENTRY4, 4);859 860 /** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry861 * (8-byte). In accordance with the AMD spec. */862 typedef struct ACPIIVHDDEVENTRY8863 {864 uint8_t u8DevEntryType; /**< Device entry type. */865 union866 {867 /** Reserved: When u8DevEntryType is 0x40, 0x41, 0x44 or 0x45 (or 0x49-0x7F). */868 struct869 {870 uint8_t au8Rsvd0[7]; /**< Reserved (MBZ). */871 } rsvd;872 /** Alias Select: When u8DevEntryType is 0x42 or 0x43. */873 struct874 {875 uint16_t u16DevIdA; /**< Device ID A. */876 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */877 uint8_t u8Rsvd0; /**< Reserved (MBZ). */878 uint16_t u16DevIdB; /**< Device ID B. */879 uint8_t u8Rsvd1; /**< Reserved (MBZ). */880 } alias;881 /** Extended Select: When u8DevEntryType is 0x46 or 0x47. */882 struct883 {884 uint16_t u16DevId; /**< Device ID. */885 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */886 uint32_t u32ExtDteSetting; /**< Extended DTE setting. */887 } ext;888 /** Special Device: When u8DevEntryType is 0x48. */889 struct890 {891 uint16_t u16Rsvd0; /**< Reserved (MBZ). */892 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */893 uint8_t u8Handle; /**< Handle contains I/O APIC ID or HPET number. */894 uint16_t u16DevIdB; /**< Device ID B (I/O APIC or HPET). */895 uint8_t u8Variety; /**< Whether this is the HPET or I/O APIC. */896 } special;897 } u;898 } ACPIIVHDDEVENTRY8;899 AssertCompileSize(ACPIIVHDDEVENTRY8, 8);900 901 /** @name IVHD Type 10h Flags.902 * In accordance with the AMD spec.903 * @{ */904 /** Peripheral page request support. */905 #define ACPI_IVHD_10H_F_PPR_SUP RT_BIT(7)906 /** Prefetch IOMMU pages command support. */907 #define ACPI_IVHD_10H_F_PREF_SUP RT_BIT(6)908 /** Coherent control. */909 #define ACPI_IVHD_10H_F_COHERENT RT_BIT(5)910 /** Remote IOTLB support. */911 #define ACPI_IVHD_10H_F_IOTLB_SUP RT_BIT(4)912 /** Isochronous control. */913 #define ACPI_IVHD_10H_F_ISOC RT_BIT(3)914 /** Response Pass Posted Write. */915 #define ACPI_IVHD_10H_F_RES_PASS_PW RT_BIT(2)916 /** Pass Posted Write. */917 #define ACPI_IVHD_10H_F_PASS_PW RT_BIT(1)918 /** HyperTransport Tunnel. */919 #define ACPI_IVHD_10H_F_HT_TUNNEL RT_BIT(0)920 /** @} */921 922 /** @name IVRS IVinfo field.923 * In accordance with the AMD spec.924 * @{ */925 /** EFRSup: Extended Feature Support. */926 #define ACPI_IVINFO_BF_EFR_SUP_SHIFT 0927 #define ACPI_IVINFO_BF_EFR_SUP_MASK UINT32_C(0x00000001)928 /** DMA Remap Sup: DMA remapping support (pre-boot DMA protection with929 * mandatory remapping of device accessed memory). */930 #define ACPI_IVINFO_BF_DMA_REMAP_SUP_SHIFT 1931 #define ACPI_IVINFO_BF_DMA_REMAP_SUP_MASK UINT32_C(0x00000002)932 /** Bits 4:2 reserved. */933 #define ACPI_IVINFO_BF_RSVD_2_4_SHIFT 2934 #define ACPI_IVINFO_BF_RSVD_2_4_MASK UINT32_C(0x0000001c)935 /** GVASize: Guest virtual-address size. */936 #define ACPI_IVINFO_BF_GVA_SIZE_SHIFT 5937 #define ACPI_IVINFO_BF_GVA_SIZE_MASK UINT32_C(0x000000e0)938 /** PASize: System physical address size. */939 #define ACPI_IVINFO_BF_PA_SIZE_SHIFT 8940 #define ACPI_IVINFO_BF_PA_SIZE_MASK UINT32_C(0x00007f00)941 /** VASize: Virtual address size. */942 #define ACPI_IVINFO_BF_VA_SIZE_SHIFT 15943 #define ACPI_IVINFO_BF_VA_SIZE_MASK UINT32_C(0x003f8000)944 /** HTAtsResv: HyperTransport ATS-response address translation range reserved. */945 #define ACPI_IVINFO_BF_HT_ATS_RESV_SHIFT 22946 #define ACPI_IVINFO_BF_HT_ATS_RESV_MASK UINT32_C(0x00400000)947 /** Bits 31:23 reserved. */948 #define ACPI_IVINFO_BF_RSVD_23_31_SHIFT 23949 #define ACPI_IVINFO_BF_RSVD_23_31_MASK UINT32_C(0xff800000)950 RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVINFO_BF_, UINT32_C(0), UINT32_MAX,951 (EFR_SUP, DMA_REMAP_SUP, RSVD_2_4, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_31));952 /** @} */953 954 /** @name IVHD IOMMU info flags.955 * In accordance with the AMD spec.956 * @{ */957 /** MSI message number for the event log. */958 #define ACPI_IOMMU_INFO_BF_MSI_NUM_SHIFT 0959 #define ACPI_IOMMU_INFO_BF_MSI_NUM_MASK UINT16_C(0x001f)960 /** Bits 7:5 reserved. */961 #define ACPI_IOMMU_INFO_BF_RSVD_5_7_SHIFT 5962 #define ACPI_IOMMU_INFO_BF_RSVD_5_7_MASK UINT16_C(0x00e0)963 /** IOMMU HyperTransport Unit ID number. */964 #define ACPI_IOMMU_INFO_BF_UNIT_ID_SHIFT 8965 #define ACPI_IOMMU_INFO_BF_UNIT_ID_MASK UINT16_C(0x1f00)966 /** Bits 15:13 reserved. */967 #define ACPI_IOMMU_INFO_BF_RSVD_13_15_SHIFT 13968 #define ACPI_IOMMU_INFO_BF_RSVD_13_15_MASK UINT16_C(0xe000)969 RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_INFO_BF_, UINT16_C(0), UINT16_MAX,970 (MSI_NUM, RSVD_5_7, UNIT_ID, RSVD_13_15));971 /** @} */972 973 /** @name IVHD IOMMU feature reporting field.974 * In accordance with the AMD spec.975 * @{ */976 /** x2APIC supported for peripherals. */977 #define ACPI_IOMMU_FEAT_BF_XT_SUP_SHIFT 0978 #define ACPI_IOMMU_FEAT_BF_XT_SUP_MASK UINT32_C(0x00000001)979 /** NX supported for I/O. */980 #define ACPI_IOMMU_FEAT_BF_NX_SUP_SHIFT 1981 #define ACPI_IOMMU_FEAT_BF_NX_SUP_MASK UINT32_C(0x00000002)982 /** GT (Guest Translation) supported. */983 #define ACPI_IOMMU_FEAT_BF_GT_SUP_SHIFT 2984 #define ACPI_IOMMU_FEAT_BF_GT_SUP_MASK UINT32_C(0x00000004)985 /** GLX (Number of guest CR3 tables) supported. */986 #define ACPI_IOMMU_FEAT_BF_GLX_SUP_SHIFT 3987 #define ACPI_IOMMU_FEAT_BF_GLX_SUP_MASK UINT32_C(0x00000018)988 /** IA (INVALIDATE_IOMMU_ALL) command supported. */989 #define ACPI_IOMMU_FEAT_BF_IA_SUP_SHIFT 5990 #define ACPI_IOMMU_FEAT_BF_IA_SUP_MASK UINT32_C(0x00000020)991 /** GA (Guest virtual APIC) supported. */992 #define ACPI_IOMMU_FEAT_BF_GA_SUP_SHIFT 6993 #define ACPI_IOMMU_FEAT_BF_GA_SUP_MASK UINT32_C(0x00000040)994 /** HE (Hardware error) registers supported. */995 #define ACPI_IOMMU_FEAT_BF_HE_SUP_SHIFT 7996 #define ACPI_IOMMU_FEAT_BF_HE_SUP_MASK UINT32_C(0x00000080)997 /** PASMax (maximum PASID) supported. Ignored if PPRSup=0. */998 #define ACPI_IOMMU_FEAT_BF_PAS_MAX_SHIFT 8999 #define ACPI_IOMMU_FEAT_BF_PAS_MAX_MASK UINT32_C(0x00001f00)1000 /** PNCounters (Number of performance counters per counter bank) supported. */1001 #define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_SHIFT 131002 #define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)1003 /** PNBanks (Number of performance counter banks) supported. */1004 #define ACPI_IOMMU_FEAT_BF_PN_BANKS_SHIFT 171005 #define ACPI_IOMMU_FEAT_BF_PN_BANKS_MASK UINT32_C(0x007e0000)1006 /** MSINumPPR (MSI number for peripheral page requests). */1007 #define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_SHIFT 231008 #define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)1009 /** GATS (Guest address translation size). MBZ when GTSup=0. */1010 #define ACPI_IOMMU_FEAT_BF_GATS_SHIFT 281011 #define ACPI_IOMMU_FEAT_BF_GATS_MASK UINT32_C(0x30000000)1012 /** HATS (Host address translation size). */1013 #define ACPI_IOMMU_FEAT_BF_HATS_SHIFT 301014 #define ACPI_IOMMU_FEAT_BF_HATS_MASK UINT32_C(0xc0000000)1015 RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_FEAT_BF_, UINT32_C(0), UINT32_MAX,1016 (XT_SUP, NX_SUP, GT_SUP, GLX_SUP, IA_SUP, GA_SUP, HE_SUP, PAS_MAX, PN_COUNTERS, PN_BANKS,1017 MSI_NUM_PPR, GATS, HATS));1018 /** @} */1019 1020 /** @name IOMMU Extended Feature Register (PCI/MMIO/ACPI).1021 * In accordance with the AMD spec.1022 * @{ */1023 /** PreFSup: Prefetch support (RO). */1024 #define IOMMU_EXT_FEAT_BF_PREF_SUP_SHIFT 01025 #define IOMMU_EXT_FEAT_BF_PREF_SUP_MASK UINT64_C(0x0000000000000001)1026 /** PPRSup: Peripheral Page Request (PPR) support (RO). */1027 #define IOMMU_EXT_FEAT_BF_PPR_SUP_SHIFT 11028 #define IOMMU_EXT_FEAT_BF_PPR_SUP_MASK UINT64_C(0x0000000000000002)1029 /** XTSup: x2APIC support (RO). */1030 #define IOMMU_EXT_FEAT_BF_X2APIC_SUP_SHIFT 21031 #define IOMMU_EXT_FEAT_BF_X2APIC_SUP_MASK UINT64_C(0x0000000000000004)1032 /** NXSup: No Execute (PMR and PRIV) support (RO). */1033 #define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_SHIFT 31034 #define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_MASK UINT64_C(0x0000000000000008)1035 /** GTSup: Guest Translation support (RO). */1036 #define IOMMU_EXT_FEAT_BF_GT_SUP_SHIFT 41037 #define IOMMU_EXT_FEAT_BF_GT_SUP_MASK UINT64_C(0x0000000000000010)1038 /** Bit 5 reserved. */1039 #define IOMMU_EXT_FEAT_BF_RSVD_5_SHIFT 51040 #define IOMMU_EXT_FEAT_BF_RSVD_5_MASK UINT64_C(0x0000000000000020)1041 /** IASup: INVALIDATE_IOMMU_ALL command support (RO). */1042 #define IOMMU_EXT_FEAT_BF_IA_SUP_SHIFT 61043 #define IOMMU_EXT_FEAT_BF_IA_SUP_MASK UINT64_C(0x0000000000000040)1044 /** GASup: Guest virtual-APIC support (RO). */1045 #define IOMMU_EXT_FEAT_BF_GA_SUP_SHIFT 71046 #define IOMMU_EXT_FEAT_BF_GA_SUP_MASK UINT64_C(0x0000000000000080)1047 /** HESup: Hardware error registers support (RO). */1048 #define IOMMU_EXT_FEAT_BF_HE_SUP_SHIFT 81049 #define IOMMU_EXT_FEAT_BF_HE_SUP_MASK UINT64_C(0x0000000000000100)1050 /** PCSup: Performance counters support (RO). */1051 #define IOMMU_EXT_FEAT_BF_PC_SUP_SHIFT 91052 #define IOMMU_EXT_FEAT_BF_PC_SUP_MASK UINT64_C(0x0000000000000200)1053 /** HATS: Host Address Translation Size (RO). */1054 #define IOMMU_EXT_FEAT_BF_HATS_SHIFT 101055 #define IOMMU_EXT_FEAT_BF_HATS_MASK UINT64_C(0x0000000000000c00)1056 /** GATS: Guest Address Translation Size (RO). */1057 #define IOMMU_EXT_FEAT_BF_GATS_SHIFT 121058 #define IOMMU_EXT_FEAT_BF_GATS_MASK UINT64_C(0x0000000000003000)1059 /** GLXSup: Guest CR3 root table level support (RO). */1060 #define IOMMU_EXT_FEAT_BF_GLX_SUP_SHIFT 141061 #define IOMMU_EXT_FEAT_BF_GLX_SUP_MASK UINT64_C(0x000000000000c000)1062 /** SmiFSup: SMI filter register support (RO). */1063 #define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_SHIFT 161064 #define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_MASK UINT64_C(0x0000000000030000)1065 /** SmiFRC: SMI filter register count (RO). */1066 #define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_SHIFT 181067 #define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_MASK UINT64_C(0x00000000001c0000)1068 /** GAMSup: Guest virtual-APIC modes support (RO). */1069 #define IOMMU_EXT_FEAT_BF_GAM_SUP_SHIFT 211070 #define IOMMU_EXT_FEAT_BF_GAM_SUP_MASK UINT64_C(0x0000000000e00000)1071 /** DualPprLogSup: Dual PPR Log support (RO). */1072 #define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_SHIFT 241073 #define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_MASK UINT64_C(0x0000000003000000)1074 /** Bits 27:26 reserved. */1075 #define IOMMU_EXT_FEAT_BF_RSVD_26_27_SHIFT 261076 #define IOMMU_EXT_FEAT_BF_RSVD_26_27_MASK UINT64_C(0x000000000c000000)1077 /** DualEventLogSup: Dual Event Log support (RO). */1078 #define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_SHIFT 281079 #define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_MASK UINT64_C(0x0000000030000000)1080 /** Bits 31:30 reserved. */1081 #define IOMMU_EXT_FEAT_BF_RSVD_30_31_SHIFT 301082 #define IOMMU_EXT_FEAT_BF_RSVD_30_31_MASK UINT64_C(0x00000000c0000000)1083 /** PASMax: Maximum PASID support (RO). */1084 #define IOMMU_EXT_FEAT_BF_PASID_MAX_SHIFT 321085 #define IOMMU_EXT_FEAT_BF_PASID_MAX_MASK UINT64_C(0x0000001f00000000)1086 /** USSup: User/Supervisor support (RO). */1087 #define IOMMU_EXT_FEAT_BF_US_SUP_SHIFT 371088 #define IOMMU_EXT_FEAT_BF_US_SUP_MASK UINT64_C(0x0000002000000000)1089 /** DevTblSegSup: Segmented Device Table support (RO). */1090 #define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_SHIFT 381091 #define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_MASK UINT64_C(0x000000c000000000)1092 /** PprOverflwEarlySup: PPR Log Overflow Early warning support (RO). */1093 #define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_SHIFT 401094 #define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_MASK UINT64_C(0x0000010000000000)1095 /** PprAutoRspSup: PPR Automatic Response support (RO). */1096 #define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_SHIFT 411097 #define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_MASK UINT64_C(0x0000020000000000)1098 /** MarcSup: Memory Access and Routing (MARC) support (RO). */1099 #define IOMMU_EXT_FEAT_BF_MARC_SUP_SHIFT 421100 #define IOMMU_EXT_FEAT_BF_MARC_SUP_MASK UINT64_C(0x00000c0000000000)1101 /** BlkStopMrkSup: Block StopMark message support (RO). */1102 #define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_SHIFT 441103 #define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_MASK UINT64_C(0x0000100000000000)1104 /** PerfOptSup: IOMMU Performance Optimization support (RO). */1105 #define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_SHIFT 451106 #define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_MASK UINT64_C(0x0000200000000000)1107 /** MsiCapMmioSup: MSI-Capability Register MMIO access support (RO). */1108 #define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_SHIFT 461109 #define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_MASK UINT64_C(0x0000400000000000)1110 /** Bit 47 reserved. */1111 #define IOMMU_EXT_FEAT_BF_RSVD_47_SHIFT 471112 #define IOMMU_EXT_FEAT_BF_RSVD_47_MASK UINT64_C(0x0000800000000000)1113 /** GIoSup: Guest I/O Protection support (RO). */1114 #define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_SHIFT 481115 #define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_MASK UINT64_C(0x0001000000000000)1116 /** HASup: Host Access support (RO). */1117 #define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_SHIFT 491118 #define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_MASK UINT64_C(0x0002000000000000)1119 /** EPHSup: Enhandled PPR Handling support (RO). */1120 #define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_SHIFT 501121 #define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_MASK UINT64_C(0x0004000000000000)1122 /** AttrFWSup: Attribute Forward support (RO). */1123 #define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_SHIFT 511124 #define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_MASK UINT64_C(0x0008000000000000)1125 /** HDSup: Host Dirty Support (RO). */1126 #define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_SHIFT 521127 #define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_MASK UINT64_C(0x0010000000000000)1128 /** Bit 53 reserved. */1129 #define IOMMU_EXT_FEAT_BF_RSVD_53_SHIFT 531130 #define IOMMU_EXT_FEAT_BF_RSVD_53_MASK UINT64_C(0x0020000000000000)1131 /** InvIotlbTypeSup: Invalidate IOTLB type support (RO). */1132 #define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_SHIFT 541133 #define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_MASK UINT64_C(0x0040000000000000)1134 /** Bits 60:55 reserved. */1135 #define IOMMU_EXT_FEAT_BF_RSVD_55_60_SHIFT 551136 #define IOMMU_EXT_FEAT_BF_RSVD_55_60_MASK UINT64_C(0x1f80000000000000)1137 /** GAUpdateDisSup: Support disabling hardware update on guest page table access1138 * (RO). */1139 #define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_SHIFT 611140 #define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_MASK UINT64_C(0x2000000000000000)1141 /** ForcePhysDestSup: Force Physical Destination Mode for Remapped Interrupt1142 * support (RO). */1143 #define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_SHIFT 621144 #define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_MASK UINT64_C(0x4000000000000000)1145 /** Bit 63 reserved. */1146 #define IOMMU_EXT_FEAT_BF_RSVD_63_SHIFT 631147 #define IOMMU_EXT_FEAT_BF_RSVD_63_MASK UINT64_C(0x8000000000000000)1148 RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_EXT_FEAT_BF_, UINT64_C(0), UINT64_MAX,1149 (PREF_SUP, PPR_SUP, X2APIC_SUP, NO_EXEC_SUP, GT_SUP, RSVD_5, IA_SUP, GA_SUP, HE_SUP, PC_SUP,1150 HATS, GATS, GLX_SUP, SMI_FLT_SUP, SMI_FLT_REG_CNT, GAM_SUP, DUAL_PPR_LOG_SUP, RSVD_26_27,1151 DUAL_EVT_LOG_SUP, RSVD_30_31, PASID_MAX, US_SUP, DEV_TBL_SEG_SUP, PPR_OVERFLOW_EARLY,1152 PPR_AUTO_RES_SUP, MARC_SUP, BLKSTOP_MARK_SUP, PERF_OPT_SUP, MSI_CAP_MMIO_SUP, RSVD_47,1153 GST_IO_PROT_SUP, HST_ACCESS_SUP, ENHANCED_PPR_SUP, ATTR_FW_SUP, HST_DIRTY_SUP, RSVD_53,1154 INV_IOTLB_TYPE_SUP, RSVD_55_60, GA_UPDATE_DIS_SUP, FORCE_PHYS_DST_SUP, RSVD_63));1155 /** @} */1156 1157 /** IVHD (I/O Virtualization Hardware Definition) Type 10h.1158 * In accordance with the AMD spec. */1159 typedef struct ACPIIVHDTYPE101160 {1161 uint8_t u8Type; /**< Type: Must be 0x10. */1162 uint8_t u8Flags; /**< Flags (see ACPI_IVHD_10H_F_XXX). */1163 uint16_t u16Length; /**< Length of IVHD including IVHD device entries. */1164 uint16_t u16DeviceId; /**< Device ID of the IOMMU. */1165 uint16_t u16CapOffset; /**< Offset in Capability space for control fields of IOMMU. */1166 uint64_t u64BaseAddress; /**< Base address of IOMMU control registers in MMIO space. */1167 uint16_t u16PciSegmentGroup; /**< PCI segment group number. */1168 uint16_t u16IommuInfo; /**< Interrupt number and Unit ID. */1169 uint32_t u32Features; /**< IOMMU feature reporting. */1170 /* IVHD device entry block follows. */1171 } ACPIIVHDTYPE10;1172 AssertCompileSize(ACPIIVHDTYPE10, 24);1173 1174 /** @name IVHD Type 11h Flags.1175 * In accordance with the AMD spec.1176 * @{ */1177 /** Coherent control. */1178 #define ACPI_IVHD_11H_F_COHERENT RT_BIT(5)1179 /** Remote IOTLB support. */1180 #define ACPI_IVHD_11H_F_IOTLB_SUP RT_BIT(4)1181 /** Isochronous control. */1182 #define ACPI_IVHD_11H_F_ISOC RT_BIT(3)1183 /** Response Pass Posted Write. */1184 #define ACPI_IVHD_11H_F_RES_PASS_PW RT_BIT(2)1185 /** Pass Posted Write. */1186 #define ACPI_IVHD_11H_F_PASS_PW RT_BIT(1)1187 /** HyperTransport Tunnel. */1188 #define ACPI_IVHD_11H_F_HT_TUNNEL RT_BIT(0)1189 /** @} */1190 1191 /** @name IVHD IOMMU Type 11 Attributes field.1192 * In accordance with the AMD spec.1193 * @{ */1194 /** Bits 12:0 reserved. */1195 #define ACPI_IOMMU_ATTR_BF_RSVD_0_12_SHIFT 01196 #define ACPI_IOMMU_ATTR_BF_RSVD_0_12_MASK UINT32_C(0x00001fff)1197 /** PNCounters: Number of performance counters per counter bank. */1198 #define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_SHIFT 131199 #define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)1200 /** PNBanks: Number of performance counter banks. */1201 #define ACPI_IOMMU_ATTR_BF_PN_BANKS_SHIFT 171202 #define ACPI_IOMMU_ATTR_BF_PN_BANKS_MASK UINT32_C(0x007e0000)1203 /** MSINumPPR: MSI number for peripheral page requests (PPR). */1204 #define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_SHIFT 231205 #define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)1206 /** Bits 31:28 reserved. */1207 #define ACPI_IOMMU_ATTR_BF_RSVD_28_31_SHIFT 281208 #define ACPI_IOMMU_ATTR_BF_RSVD_28_31_MASK UINT32_C(0xf0000000)1209 RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_ATTR_BF_, UINT32_C(0), UINT32_MAX,1210 (RSVD_0_12, PN_COUNTERS, PN_BANKS, MSI_NUM_PPR, RSVD_28_31));1211 /** @} */1212 1213 /** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 11h.1214 * In accordance with the AMD spec. */1215 typedef struct ACPIIVHDTYPE111216 {1217 uint8_t u8Type; /**< Type: Must be 0x11. */1218 uint8_t u8Flags; /**< Flags. */1219 uint16_t u16Length; /**< Length: Size starting from Type fields incl. IVHD device entries. */1220 uint16_t u16DeviceId; /**< Device ID of the IOMMU. */1221 uint16_t u16CapOffset; /**< Offset in Capability space for control fields of IOMMU. */1222 uint64_t u64BaseAddress; /**< Base address of IOMMU control registers in MMIO space. */1223 uint16_t u16PciSegmentGroup; /**< PCI segment group number. */1224 uint16_t u16IommuInfo; /**< Interrupt number and unit ID. */1225 uint32_t u32IommuAttr; /**< IOMMU info. not reported in EFR. */1226 uint64_t u64EfrRegister; /**< Extended Feature Register (must be identical to its MMIO shadow). */1227 uint64_t u64Rsvd0; /**< Reserved for future. */1228 /* IVHD device entry block follows. */1229 } ACPIIVHDTYPE11;1230 AssertCompileSize(ACPIIVHDTYPE11, 40);1231 1232 /** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 40h.1233 * In accordance with the AMD spec. */1234 typedef struct ACPIIVHDTYPE11 ACPIIVHDTYPE40;1235 1236 792 /** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure). 1237 793 * In accordance with the AMD spec. */ … … 3641 3197 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn)); 3642 3198 Ivrs.IvhdType10.u16CapOffset = 0; /* 0=No multiple IOMMU functionality. */ 3643 Ivrs.IvhdType10.u64BaseAddress = 0xfeb80000; /* MMIO base address: Taken from real hardware ACPI dumps. */3199 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR; 3644 3200 Ivrs.IvhdType10.u16PciSegmentGroup = 0; 3645 3201 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */ … … 3660 3216 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0) 3661 3217 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0) 3662 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, 6 & 3); /* IOMMU_MAX_HOST_PT_LEVEL & 3*/3218 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3); 3663 3219 /* Start range from BDF (00:01:00). */ 3664 3220 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE; … … 3718 3274 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1) 3719 3275 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0) 3720 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, 6 /* IOMMU_MAX_HOST_PT_LEVEL */& 3)3276 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3) 3721 3277 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0) 3722 3278 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0) … … 3728 3284 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0) 3729 3285 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0) 3730 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, 3 /* IOMMU_MAX_DEV_TAB_SEGMENTS */)3286 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS) 3731 3287 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0) 3732 3288 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
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