Changeset 86009 in vbox for trunk/src/VBox
- Timestamp:
- Sep 2, 2020 11:01:09 PM (5 years ago)
- svn:sync-xref-src-repo-rev:
- 140205
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Config.kmk
r82968 r86009 26 26 ifndef VBOX_VMM_CONFIG_KMK_INCLUDED 27 27 include $(PATH_ROOT)/src/VBox/VMM/Config.kmk 28 endif 29 30 # We need the Additions/3D/Config.kmk for the VBOX_PATH_VMSVGA_INC variable. 31 ifndef VBOX_MESA3D_CONFIG_KMK_INCLUDED 32 include $(PATH_ROOT)/src/VBox/Additions/3D/Config.kmk 28 33 endif 29 34 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r85476 r86009 162 162 163 163 #include "DevVGA-SVGA.h" 164 #include "vmsvga/svga_escape.h"165 #include "vmsvga/svga_overlay.h"166 #include "vmsvga/svga3d_caps.h"167 164 #ifdef VBOX_WITH_VMSVGA3D 168 165 # include "DevVGA-SVGA3d.h" … … 2571 2568 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); 2572 2569 break; 2573 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM:2574 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM= %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));2575 break; 2576 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM:2577 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM= %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));2570 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1: 2571 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); 2572 break; 2573 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2: 2574 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); 2578 2575 break; 2579 2576 case SVGA_FIFO_3D_CAPS_LAST: … … 3917 3914 * Process the command. 3918 3915 */ 3919 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)]; 3916 /* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler 3917 * warning. Because we support some obsolete and deprecated commands, which are not included in 3918 * the SVGAFifoCmdId enum in the VMSVGA headers anymore. 3919 */ 3920 uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)]; 3920 3921 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); 3921 3922 LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n", … … 4497 4498 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb); 4498 4499 4499 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format. s.bitsPerPixel, pCmd->format.s.colorDepth));4500 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth)); 4500 4501 pSVGAState->GMRFB.ptr = pCmd->ptr; 4501 4502 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine; … … 4520 4521 4521 4522 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */ 4522 AssertBreak(pSVGAState->GMRFB.format. s.bitsPerPixel == pScreen->cBpp);4523 AssertBreak(pSVGAState->GMRFB.format.bitsPerPixel == pScreen->cBpp); 4523 4524 4524 4525 /* Clip destRect to the screen dimensions. */ … … 4562 4563 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */ 4563 4564 SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr; 4564 uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format. s.bitsPerPixel, 8)) / 84565 uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.bitsPerPixel, 8)) / 8 4565 4566 + pSVGAState->GMRFB.bytesPerLine * srcy; 4566 4567 int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine; … … 4591 4592 AssertPtrBreak(pScreen); 4592 4593 4593 /** @todo Support GMRFB.format. s.bitsPerPixel != pThis->svga.uBpp? */4594 AssertBreak(pSVGAState->GMRFB.format. s.bitsPerPixel == pScreen->cBpp);4594 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp? */ 4595 AssertBreak(pSVGAState->GMRFB.format.bitsPerPixel == pScreen->cBpp); 4595 4596 4596 4597 /* Clip destRect to the screen dimensions. */ … … 4634 4635 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */ 4635 4636 SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr; 4636 uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format. s.bitsPerPixel, 8)) / 84637 uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.bitsPerPixel, 8)) / 8 4637 4638 + pSVGAState->GMRFB.bytesPerLine * dsty; 4638 4639 int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine; … … 4652 4653 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill); 4653 4654 4654 Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color. s.r, pCmd->color.s.g, pCmd->color.s.b));4655 Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b)); 4655 4656 pSVGAState->colorAnnotation = pCmd->color; 4656 4657 break; … … 4675 4676 RT_UNTRUSTED_VALIDATED_FENCE(); 4676 4677 4677 /* All 3d commands start with a common header, which defines the size of the command. */ 4678 SVGA3dCmdHeader *pHdr; 4679 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr)); 4680 AssertBreak(pHdr->size < pThis->svga.cbFIFO); 4681 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size; 4682 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd); 4678 /* All 3d commands start with a common header, which defines the identifier and the size 4679 * of the command. The identifier has been already read from FIFO. Fetch the size. 4680 */ 4681 uint32_t *pcbCmd; 4682 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd)); 4683 uint32_t const cbCmd = *pcbCmd; 4684 AssertBreak(cbCmd < pThis->svga.cbFIFO); 4685 uint32_t *pu32Cmd; 4686 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd); 4687 pu32Cmd++; /* Skip the command size. */ 4683 4688 4684 4689 if (RT_LIKELY(pThis->svga.f3DEnabled)) … … 4696 4701 # define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \ 4697 4702 if (1) { \ 4698 AssertMsgBreak( pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \4703 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \ 4699 4704 RT_UNTRUSTED_VALIDATED_FENCE(); \ 4700 4705 } else do {} while (0) … … 4704 4709 { 4705 4710 uint32_t cMipLevels; 4706 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *) (pHdr + 1);4711 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pu32Cmd; 4707 4712 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4708 4713 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine); 4709 4714 4710 cMipLevels = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dSize);4715 cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize); 4711 4716 rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0, 4712 4717 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1)); … … 4720 4725 { 4721 4726 uint32_t cMipLevels; 4722 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *) (pHdr + 1);4727 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pu32Cmd; 4723 4728 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4724 4729 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2); 4725 4730 4726 cMipLevels = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dSize);4731 cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize); 4727 4732 rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face, 4728 4733 pCmd->multisampleCount, pCmd->autogenFilter, … … 4733 4738 case SVGA_3D_CMD_SURFACE_DESTROY: 4734 4739 { 4735 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *) (pHdr + 1);4740 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pu32Cmd; 4736 4741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4737 4742 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy); … … 4743 4748 { 4744 4749 uint32_t cCopyBoxes; 4745 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *) (pHdr + 1);4750 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pu32Cmd; 4746 4751 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4747 4752 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy); 4748 4753 4749 cCopyBoxes = ( pHdr->size- sizeof(pCmd)) / sizeof(SVGA3dCopyBox);4754 cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox); 4750 4755 rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1)); 4751 4756 break; … … 4754 4759 case SVGA_3D_CMD_SURFACE_STRETCHBLT: 4755 4760 { 4756 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *) (pHdr + 1);4761 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pu32Cmd; 4757 4762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4758 4763 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt); … … 4766 4771 { 4767 4772 uint32_t cCopyBoxes; 4768 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *) (pHdr + 1);4773 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pu32Cmd; 4769 4774 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4770 4775 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma); … … 4773 4778 if (LogRelIs3Enabled()) 4774 4779 u64NanoTS = RTTimeNanoTS(); 4775 cCopyBoxes = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);4780 cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox); 4776 4781 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a); 4777 4782 rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer, … … 4795 4800 { 4796 4801 uint32_t cRects; 4797 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *) (pHdr + 1);4802 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pu32Cmd; 4798 4803 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4799 4804 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen); … … 4805 4810 if (LogRelIs3Enabled()) 4806 4811 u64NanoTS = RTTimeNanoTS(); 4807 cRects = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGASignedRect);4812 cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect); 4808 4813 STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a); 4809 4814 rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, … … 4836 4841 case SVGA_3D_CMD_CONTEXT_DEFINE: 4837 4842 { 4838 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *) (pHdr + 1);4843 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pu32Cmd; 4839 4844 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4840 4845 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine); … … 4846 4851 case SVGA_3D_CMD_CONTEXT_DESTROY: 4847 4852 { 4848 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *) (pHdr + 1);4853 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pu32Cmd; 4849 4854 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4850 4855 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy); … … 4856 4861 case SVGA_3D_CMD_SETTRANSFORM: 4857 4862 { 4858 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *) (pHdr + 1);4863 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pu32Cmd; 4859 4864 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4860 4865 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform); … … 4866 4871 case SVGA_3D_CMD_SETZRANGE: 4867 4872 { 4868 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *) (pHdr + 1);4873 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pu32Cmd; 4869 4874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4870 4875 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange); … … 4877 4882 { 4878 4883 uint32_t cRenderStates; 4879 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *) (pHdr + 1);4884 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pu32Cmd; 4880 4885 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4881 4886 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState); 4882 4887 4883 cRenderStates = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dRenderState);4888 cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState); 4884 4889 rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1)); 4885 4890 break; … … 4888 4893 case SVGA_3D_CMD_SETRENDERTARGET: 4889 4894 { 4890 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *) (pHdr + 1);4895 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pu32Cmd; 4891 4896 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4892 4897 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget); … … 4899 4904 { 4900 4905 uint32_t cTextureStates; 4901 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *) (pHdr + 1);4906 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pu32Cmd; 4902 4907 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4903 4908 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState); 4904 4909 4905 cTextureStates = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dTextureState);4910 cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState); 4906 4911 rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1)); 4907 4912 break; … … 4910 4915 case SVGA_3D_CMD_SETMATERIAL: 4911 4916 { 4912 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *) (pHdr + 1);4917 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pu32Cmd; 4913 4918 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4914 4919 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial); … … 4920 4925 case SVGA_3D_CMD_SETLIGHTDATA: 4921 4926 { 4922 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *) (pHdr + 1);4927 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pu32Cmd; 4923 4928 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4924 4929 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData); … … 4930 4935 case SVGA_3D_CMD_SETLIGHTENABLED: 4931 4936 { 4932 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *) (pHdr + 1);4937 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pu32Cmd; 4933 4938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4934 4939 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable); … … 4940 4945 case SVGA_3D_CMD_SETVIEWPORT: 4941 4946 { 4942 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *) (pHdr + 1);4947 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pu32Cmd; 4943 4948 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4944 4949 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort); … … 4950 4955 case SVGA_3D_CMD_SETCLIPPLANE: 4951 4956 { 4952 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *) (pHdr + 1);4957 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pu32Cmd; 4953 4958 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4954 4959 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane); … … 4960 4965 case SVGA_3D_CMD_CLEAR: 4961 4966 { 4962 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *) (pHdr + 1);4967 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pu32Cmd; 4963 4968 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4964 4969 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear); 4965 4970 4966 uint32_t cRects = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dRect);4971 uint32_t cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect); 4967 4972 rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1)); 4968 4973 break; … … 4972 4977 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */ 4973 4978 { 4974 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *) (pHdr + 1);4979 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pu32Cmd; 4975 4980 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4976 4981 if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT) … … 4979 4984 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack); 4980 4985 4981 uint32_t cRects = ( pHdr->size- sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);4986 uint32_t cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect); 4982 4987 4983 4988 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a); … … 4989 4994 case SVGA_3D_CMD_SHADER_DEFINE: 4990 4995 { 4991 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *) (pHdr + 1);4996 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pu32Cmd; 4992 4997 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4993 4998 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine); 4994 4999 4995 uint32_t cbData = ( pHdr->size- sizeof(*pCmd));5000 uint32_t cbData = (cbCmd - sizeof(*pCmd)); 4996 5001 rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1)); 4997 5002 break; … … 5000 5005 case SVGA_3D_CMD_SHADER_DESTROY: 5001 5006 { 5002 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *) (pHdr + 1);5007 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pu32Cmd; 5003 5008 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5004 5009 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy); … … 5010 5015 case SVGA_3D_CMD_SET_SHADER: 5011 5016 { 5012 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *) (pHdr + 1);5017 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pu32Cmd; 5013 5018 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5014 5019 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader); … … 5020 5025 case SVGA_3D_CMD_SET_SHADER_CONST: 5021 5026 { 5022 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *) (pHdr + 1);5027 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pu32Cmd; 5023 5028 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5024 5029 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst); 5025 5030 5026 uint32_t cRegisters = ( pHdr->size- sizeof(*pCmd)) / sizeof(pCmd->values) + 1;5031 uint32_t cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1; 5027 5032 rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values); 5028 5033 break; … … 5031 5036 case SVGA_3D_CMD_DRAW_PRIMITIVES: 5032 5037 { 5033 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *) (pHdr + 1);5038 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pu32Cmd; 5034 5039 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5035 5040 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives); … … 5039 5044 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl) 5040 5045 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange); 5041 ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size- sizeof(*pCmd));5042 5043 uint32_t cVertexDivisor = ( pHdr->size- sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);5046 ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd)); 5047 5048 uint32_t cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t); 5044 5049 AssertBreak(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls); 5045 5050 … … 5059 5064 case SVGA_3D_CMD_SETSCISSORRECT: 5060 5065 { 5061 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *) (pHdr + 1);5066 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pu32Cmd; 5062 5067 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5063 5068 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect); … … 5069 5074 case SVGA_3D_CMD_BEGIN_QUERY: 5070 5075 { 5071 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *) (pHdr + 1);5076 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pu32Cmd; 5072 5077 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5073 5078 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery); … … 5079 5084 case SVGA_3D_CMD_END_QUERY: 5080 5085 { 5081 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *) (pHdr + 1);5086 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pu32Cmd; 5082 5087 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5083 5088 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery); … … 5089 5094 case SVGA_3D_CMD_WAIT_FOR_QUERY: 5090 5095 { 5091 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *) (pHdr + 1);5096 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pu32Cmd; 5092 5097 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5093 5098 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery); … … 5099 5104 case SVGA_3D_CMD_GENERATE_MIPMAPS: 5100 5105 { 5101 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *) (pHdr + 1);5106 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pu32Cmd; 5102 5107 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5103 5108 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps); … … 6419 6424 "xSURFACEFMT_Z_DF24", 6420 6425 "xSURFACEFMT_Z_D24S8_INT", 6421 "xSURFACEFMT_ BC4_UNORM",6422 "xSURFACEFMT_ BC5_UNORM", /* 83 */6426 "xSURFACEFMT_ATI1", 6427 "xSURFACEFMT_ATI2", /* 83 */ 6423 6428 }; 6424 6429 … … 6447 6452 6448 6453 /* Fill out all 3d capabilities. */ 6449 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++) 6454 /** @todo The current implementation stores the capabilities in the FIFO. 6455 * Newer VMSVGA uses SVGA_REG_DEV_CAP register to query 3d caps. 6456 * Prerequisite for the new interface is support for SVGA_CAP_GBOBJECTS. 6457 */ 6458 AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1); 6459 for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; i++) 6450 6460 { 6451 6461 uint32_t val = 0; -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h
r85368 r86009 25 25 #endif 26 26 27 #include <VBox/pci.h> 28 #include <VBox/vmm/pdmifs.h> 27 29 #include <VBox/vmm/pdmthread.h> 28 29 #include "vmsvga/svga3d_reg.h" 30 #include <VBox/vmm/stam.h> 31 32 /* 33 * PCI device IDs. 34 */ 35 #ifndef PCI_VENDOR_ID_VMWARE 36 # define PCI_VENDOR_ID_VMWARE 0x15AD 37 #endif 38 #ifndef PCI_DEVICE_ID_VMWARE_SVGA2 39 # define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 40 #endif 41 42 /* For "svga_overlay.h" */ 43 #ifndef TRUE 44 # define TRUE 1 45 #endif 46 #ifndef FALSE 47 # define FALSE 0 48 #endif 49 50 #include <svga3d_caps.h> 51 #include <svga3d_reg.h> 52 #include <svga3d_shaderdefs.h> 53 #include <svga_escape.h> 54 #include <svga_overlay.h> 55 56 /* Deprecated. */ 57 #define SVGA_CMD_RECT_FILL 2 58 #define SVGA_CMD_DISPLAY_CURSOR 20 59 #define SVGA_CMD_MOVE_CURSOR 21 60 61 /* 62 * SVGA_CMD_RECT_FILL -- 63 * 64 * Fill a rectangular area in the the GFB, and copy the result 65 * to any screens which intersect it. 66 * 67 * Deprecated? 68 * 69 * Availability: 70 * SVGA_CAP_RECT_FILL 71 */ 72 73 typedef 74 struct { 75 uint32_t pixel; 76 uint32_t destX; 77 uint32_t destY; 78 uint32_t width; 79 uint32_t height; 80 } SVGAFifoCmdRectFill; 81 82 /* 83 * SVGA_CMD_DISPLAY_CURSOR -- 84 * 85 * Turn the cursor on or off. 86 * 87 * Deprecated. 88 * 89 * Availability: 90 * SVGA_CAP_CURSOR? 91 */ 92 93 typedef 94 struct { 95 uint32_t id; // Reserved, must be zero. 96 uint32_t state; // 0=off 97 } SVGAFifoCmdDisplayCursor; 98 99 /* 100 * SVGA_CMD_MOVE_CURSOR -- 101 * 102 * Set the cursor position. 103 * 104 * Deprecated. 105 * 106 * Availability: 107 * SVGA_CAP_CURSOR? 108 */ 109 110 typedef 111 struct { 112 SVGASignedPoint pos; 113 } SVGAFifoCmdMoveCursor; 114 30 115 31 116 /** Default FIFO size. */ -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-hlp.cpp
r83579 r86009 24 24 #include <iprt/types.h> 25 25 26 #include "vmsvga/svga3d_reg.h" 27 #include "vmsvga/svga3d_shaderdefs.h" 26 #include "DevVGA-SVGA.h" 28 27 29 28 typedef struct VMSVGA3DSHADERPARSECONTEXT … … 98 97 src.value = *pToken; 99 98 100 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src. s.type_upper << 3 | src.s.type_lower);99 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower); 101 100 Log3(("Src: type %d, r0 %d, srcMod %d, swizzle 0x%x, r1 %d, relAddr %d, num %d\n", 102 regType, src. s.reserved0, src.s.srcMod, src.s.swizzle, src.s.reserved1, src.s.relAddr, src.s.num));103 104 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src. s.num);101 regType, src.reserved0, src.srcMod, src.swizzle, src.reserved1, src.relAddr, src.num)); 102 103 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src.num); 105 104 } 106 105 #endif … … 113 112 dest.value = *pToken; 114 113 115 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest. s.type_upper << 3 | dest.s.type_lower);114 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest.type_upper << 3 | dest.type_lower); 116 115 Log3(("Dest: type %d, r0 %d, shfScale %d, dstMod %d, mask 0x%x, r1 %d, relAddr %d, num %d\n", 117 regType, dest. s.reserved0, dest.s.shfScale, dest.s.dstMod, dest.s.mask, dest.s.reserved1, dest.s.relAddr, dest.s.num));118 119 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest. s.num);116 regType, dest.reserved0, dest.shfScale, dest.dstMod, dest.mask, dest.reserved1, dest.relAddr, dest.num)); 117 118 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest.num); 120 119 } 121 120 … … 126 125 a.values[1] = pToken[1]; // dst 127 126 128 return vmsvga3dShaderParseDestToken(pCtx, (uint32_t *)&a. s2.dst);127 return vmsvga3dShaderParseDestToken(pCtx, (uint32_t *)&a.dst); 129 128 } 130 129 … … 160 159 /* "The first token must be a version token." */ 161 160 SVGA3dShaderVersion const *pVersion = (SVGA3dShaderVersion const *)paTokensStart; 162 ASSERT_GUEST_RETURN( pVersion-> s.type == SVGA3D_VS_TYPE163 || pVersion-> s.type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR);161 ASSERT_GUEST_RETURN( pVersion->type == SVGA3D_VS_TYPE 162 || pVersion->type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR); 164 163 165 164 VMSVGA3DSHADERPARSECONTEXT ctx; 166 ctx.type = pVersion-> s.type;165 ctx.type = pVersion->type; 167 166 168 167 /* Scan the tokens. Immediately return an error code on any unexpected data. */ … … 175 174 /* Figure out the instruction length, which is how many tokens follow the instruction token. */ 176 175 uint32_t cInstLen; 177 if (token. s1.op == SVGA3DOP_COMMENT)178 cInstLen = token. s.comment_size;176 if (token.op == SVGA3DOP_COMMENT) 177 cInstLen = token.comment_size; 179 178 else 180 cInstLen = token.s 1.size;181 182 Log3(("op %d, cInstLen %d\n", token. s1.op, cInstLen));179 cInstLen = token.size; 180 181 Log3(("op %d, cInstLen %d\n", token.op, cInstLen)); 183 182 184 183 ASSERT_GUEST_RETURN(cInstLen < paTokensEnd - pToken, VERR_PARSE_ERROR); 185 184 186 if (token. s1.op == SVGA3DOP_END)185 if (token.op == SVGA3DOP_END) 187 186 { 188 187 ASSERT_GUEST_RETURN(token.value == 0x0000FFFF, VERR_PARSE_ERROR); … … 191 190 192 191 int rc; 193 switch (token. s1.op)192 switch (token.op) 194 193 { 195 194 case SVGA3DOP_DCL: -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-info.cpp
r85864 r86009 73 73 { SVGA3D_BUMPL6V5U5 , "BUMPL6V5U5" }, 74 74 { SVGA3D_BUMPX8L8V8U8 , "BUMPX8L8V8U8" }, 75 { SVGA3D_ BUMPL8V8U8 , "BUMPL8V8U8" },75 { SVGA3D_FORMAT_DEAD1 , "FORMAT_DEAD1" }, 76 76 { SVGA3D_ARGB_S10E5 , "ARGB_S10E5" }, 77 77 { SVGA3D_ARGB_S23E8 , "ARGB_S23E8" }, … … 96 96 { SVGA3D_NV12 , "NV12" }, 97 97 { SVGA3D_AYUV , "AYUV" }, 98 { SVGA3D_ BC4_UNORM , "BC4_UNORM" },99 { SVGA3D_ BC5_UNORM , "BC5_UNORM" },98 { SVGA3D_ATI1 , "ATI1" }, 99 { SVGA3D_ATI2 , "ATI2" }, 100 100 { SVGA3D_Z_DF16 , "Z_DF16" }, 101 101 { SVGA3D_Z_DF24 , "Z_DF24" }, … … 682 682 *pEnumMap->pfAsserted = true; 683 683 for (uint32_t i = 1; i < pEnumMap->cValues; i++) 684 Assert(paValues[i - 1].iValue <= paValues[i].iValue); 684 AssertMsg(paValues[i - 1].iValue <= paValues[i].iValue, 685 ("i = %d: %d followed by %d", i, paValues[i - 1].iValue, paValues[i].iValue)); 685 686 } 686 687 #endif … … 1010 1011 case SVGA3D_BUMPL6V5U5: 1011 1012 case SVGA3D_BUMPX8L8V8U8: 1012 case SVGA3D_ BUMPL8V8U8:1013 case SVGA3D_FORMAT_DEAD1: 1013 1014 case SVGA3D_ARGB_S10E5: 1014 1015 case SVGA3D_ARGB_S23E8: … … 1028 1029 case SVGA3D_NV12: 1029 1030 case SVGA3D_AYUV: 1030 case SVGA3D_ BC4_UNORM:1031 case SVGA3D_ BC5_UNORM:1031 case SVGA3D_ATI1: 1032 case SVGA3D_ATI2: 1032 1033 case SVGA3D_Z_DF16: 1033 1034 case SVGA3D_Z_DF24: … … 1226 1227 "e" "BLENDEQUATIONALPHA", /* SVGA3dBlendEquation */ 1227 1228 "*" "TRANSPARENCYANTIALIAS", /* SVGA3dTransparencyAntialiasType */ 1228 "f" "LINEAA", /* SVGA3dBool */1229 1229 "r" "LINEWIDTH", /* float */ 1230 1230 }; … … 1265 1265 case 'c': //SVGA3dColor, SVGA3dColorMask 1266 1266 RTStrPrintf(pszBuffer, cbBuffer, "%s = RGBA(%d,%d,%d,%d) (%#x)", pszName, 1267 uValue.Color. s.red, uValue.Color.s.green, uValue.Color.s.blue, uValue.Color.s.alpha, uValue.u);1267 uValue.Color.red, uValue.Color.green, uValue.Color.blue, uValue.Color.alpha, uValue.u); 1268 1268 break; 1269 1269 case 'w': //SVGA3dWrapFlags … … 1392 1392 case 'c': //SVGA3dColor, SVGA3dColorMask 1393 1393 RTStrPrintf(pszBuffer, cbBuffer, "%s = RGBA(%d,%d,%d,%d) (%#x)", pszName, 1394 uValue.Color. s.red, uValue.Color.s.green, uValue.Color.s.blue, uValue.Color.s.alpha, uValue.u);1394 uValue.Color.red, uValue.Color.green, uValue.Color.blue, uValue.Color.alpha, uValue.u); 1395 1395 break; 1396 1396 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-internal.h
r85368 r86009 87 87 #endif 88 88 89 #include "vmsvga/svga3d_shaderdefs.h"90 89 #ifdef VMSVGA3D_OPENGL 91 90 # include "vmsvga_glext/glext.h" … … 863 862 VMSVGATRANSFORMSTATE aTransformState[SVGA3D_TRANSFORM_MAX]; 864 863 VMSVGAMATERIALSTATE aMaterial[SVGA3D_FACE_MAX]; 865 VMSVGACLIPPLANESTATE aClipPlane[SVGA3D_CLIPPLANE_MAX]; 864 /* The aClipPlane array has a wrong (greater) size. Keep it for now because the array is a part of the saved state. */ 865 /** @todo Replace SVGA3D_CLIPPLANE_5 with SVGA3D_NUM_CLIPPLANES and increase the saved state version. */ 866 VMSVGACLIPPLANESTATE aClipPlane[SVGA3D_CLIPPLANE_5]; 866 867 VMSVGALIGHTSTATE aLightData[SVGA3D_MAX_LIGHTS]; 867 868 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-ogl.cpp
r85370 r86009 1097 1097 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80, 1098 1098 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81, 1099 SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM= 82,1100 SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM= 83,1099 SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82, 1100 SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83, 1101 1101 #endif 1102 1102 … … 1624 1624 1625 1625 /* Linux: Not referenced in current sources. */ 1626 case SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM:1627 case SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM:1626 case SVGA3D_DEVCAP_SURFACEFMT_ATI1: 1627 case SVGA3D_DEVCAP_SURFACEFMT_ATI2: 1628 1628 Log(("CAPS: Unknown CAP %s\n", vmsvga3dGetCapString(idx3dCaps))); 1629 1629 rc = VERR_INVALID_PARAMETER; … … 1812 1812 case SVGA3D_BUMPX8L8V8U8: 1813 1813 return D3DFMT_X8L8V8U8; 1814 case SVGA3D_ BUMPL8V8U8:1814 case SVGA3D_FORMAT_DEAD1: 1815 1815 /* No corresponding D3D9 equivalent. */ 1816 1816 AssertFailedReturn(D3DFMT_UNKNOWN); … … 1963 1963 return (D3DFORMAT)MAKEFOURCC('A', 'Y', 'U', 'V'); 1964 1964 1965 case SVGA3D_ BC4_UNORM:1966 case SVGA3D_ BC5_UNORM:1965 case SVGA3D_ATI1: 1966 case SVGA3D_ATI2: 1967 1967 /* Unknown; only in DX10 & 11 */ 1968 1968 break; … … 4479 4479 case SVGA3D_RS_CLIPPLANEENABLE: /* SVGA3dClipPlanes */ 4480 4480 { 4481 AssertCompile(SVGA3D_CLIPPLANE_MAX == (1 << 5)); 4482 for (uint32_t j = 0; j <= 5; j++) 4481 for (uint32_t j = 0; j < SVGA3D_NUM_CLIPPLANES; j++) 4483 4482 { 4484 4483 if (pRenderState[i].uintValue & RT_BIT(j)) … … 4528 4527 4529 4528 enableCap = GL_FOG_MODE; 4530 switch (mode. s.function)4529 switch (mode.function) 4531 4530 { 4532 4531 case SVGA3D_FOGFUNC_EXP: … … 4540 4539 break; 4541 4540 default: 4542 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode. s.function), VERR_INTERNAL_ERROR);4541 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode.function), VERR_INTERNAL_ERROR); 4543 4542 break; 4544 4543 } 4545 4544 4546 4545 /** @todo how to switch between vertex and pixel fog modes??? */ 4547 Assert(mode. s.type == SVGA3D_FOGTYPE_PIXEL);4546 Assert(mode.type == SVGA3D_FOGTYPE_PIXEL); 4548 4547 #if 0 4549 4548 /* The fog type determines the render state. */ 4550 switch (mode. s.type)4549 switch (mode.type) 4551 4550 { 4552 4551 case SVGA3D_FOGTYPE_VERTEX: … … 4557 4556 break; 4558 4557 default: 4559 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode. s.type), VERR_INTERNAL_ERROR);4558 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode.type), VERR_INTERNAL_ERROR); 4560 4559 break; 4561 4560 } … … 4563 4562 4564 4563 /* Set the fog base to depth or range. */ 4565 switch (mode. s.base)4564 switch (mode.base) 4566 4565 { 4567 4566 case SVGA3D_FOGBASE_DEPTHBASED: … … 4575 4574 default: 4576 4575 /* ignore */ 4577 AssertMsgFailed(("Unexpected fog base %d\n", mode. s.base));4576 AssertMsgFailed(("Unexpected fog base %d\n", mode.base)); 4578 4577 break; 4579 4578 } … … 4587 4586 mode.uintValue = pRenderState[i].uintValue; 4588 4587 4589 switch (mode. s.mode)4588 switch (mode.mode) 4590 4589 { 4591 4590 case SVGA3D_FILLMODE_POINT: … … 4599 4598 break; 4600 4599 default: 4601 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode. s.mode), VERR_INTERNAL_ERROR);4600 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode.mode), VERR_INTERNAL_ERROR); 4602 4601 break; 4603 4602 } 4604 4603 /* Only front and back faces. Also recent Mesa guest drivers initialize the 'face' to zero. */ 4605 ASSERT_GUEST(mode. s.face == SVGA3D_FACE_FRONT_BACK || mode.s.face == SVGA3D_FACE_INVALID);4604 ASSERT_GUEST(mode.face == SVGA3D_FACE_FRONT_BACK || mode.face == SVGA3D_FACE_INVALID); 4606 4605 glPolygonMode(GL_FRONT_AND_BACK, val); 4607 4606 VMSVGA3D_CHECK_LAST_ERROR(pState, pContext); … … 4639 4638 break; 4640 4639 4641 case SVGA3D_RS_ LINEAA:/* SVGA3dBool */4640 case SVGA3D_RS_ANTIALIASEDLINEENABLE: /* SVGA3dBool */ 4642 4641 enableCap = GL_LINE_SMOOTH; 4643 4642 val = pRenderState[i].uintValue; … … 5042 5041 mask.uintValue = pRenderState[i].uintValue; 5043 5042 5044 red = mask. s.red;5045 green = mask. s.green;5046 blue = mask. s.blue;5047 alpha = mask. s.alpha;5043 red = mask.red; 5044 green = mask.green; 5045 blue = mask.blue; 5046 alpha = mask.alpha; 5048 5047 5049 5048 glColorMask(red, green, blue, alpha); … … 5115 5114 5116 5115 case SVGA3D_RS_MULTISAMPLEMASK: /* uint32_t */ 5117 case SVGA3D_RS_ANTIALIASEDLINEENABLE: /* SVGA3dBool */5118 5116 Log(("vmsvga3dSetRenderState: WARNING not applicable??!!\n")); 5119 5117 break; … … 6204 6202 6205 6203 Log(("vmsvga3dSetClipPlane cid=%u %d (%d,%d)(%d,%d)\n", cid, index, (unsigned)(plane[0] * 100.0), (unsigned)(plane[1] * 100.0), (unsigned)(plane[2] * 100.0), (unsigned)(plane[3] * 100.0))); 6206 AssertReturn(index < SVGA3D_ CLIPPLANE_MAX, VERR_INVALID_PARAMETER);6204 AssertReturn(index < SVGA3D_NUM_CLIPPLANES, VERR_INVALID_PARAMETER); 6207 6205 6208 6206 PVMSVGA3DCONTEXT pContext; … … 6806 6804 VMSVGA3D_CHECK_LAST_ERROR(pState, pContext); 6807 6805 6808 GLuint divisor = paVertexDivisors && paVertexDivisors[index]. s.instanceData ? 1 : 0;6806 GLuint divisor = paVertexDivisors && paVertexDivisors[index].instanceData ? 1 : 0; 6809 6807 pState->ext.glVertexAttribDivisor(index, divisor); 6810 6808 VMSVGA3D_CHECK_LAST_ERROR(pState, pContext); … … 7070 7068 for (uint32_t iVertexDivisor = 0; iVertexDivisor < cVertexDivisor; ++iVertexDivisor) 7071 7069 { 7072 if (pVertexDivisor[iVertexDivisor]. s.indexedData)7070 if (pVertexDivisor[iVertexDivisor].indexedData) 7073 7071 { 7074 7072 if (cInstances == 0) 7075 cInstances = pVertexDivisor[iVertexDivisor]. s.count;7073 cInstances = pVertexDivisor[iVertexDivisor].count; 7076 7074 else 7077 Assert(cInstances == pVertexDivisor[iVertexDivisor]. s.count);7078 } 7079 else if (pVertexDivisor[iVertexDivisor]. s.instanceData)7080 { 7081 Assert(pVertexDivisor[iVertexDivisor]. s.count == 1);7075 Assert(cInstances == pVertexDivisor[iVertexDivisor].count); 7076 } 7077 else if (pVertexDivisor[iVertexDivisor].instanceData) 7078 { 7079 Assert(pVertexDivisor[iVertexDivisor].count == 1); 7082 7080 } 7083 7081 } … … 7583 7581 Log(("ConstantB %d: value=%d, %d, %d, %d\n", reg + i, pValues[i*4 + 0], pValues[i*4 + 1], pValues[i*4 + 2], pValues[i*4 + 3])); 7584 7582 break; 7583 7584 default: 7585 AssertFailedReturn(VERR_INVALID_PARAMETER); 7585 7586 } 7586 7587 #endif -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-shared.cpp
r84853 r86009 626 626 case SVGA3D_DEVCAP_SURFACEFMT_AYUV: 627 627 return "SVGA3D_DEVCAP_SURFACEFMT_AYUV"; 628 case SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM:629 return "SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM";630 case SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM:631 return "SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM";628 case SVGA3D_DEVCAP_SURFACEFMT_ATI1: 629 return "SVGA3D_DEVCAP_SURFACEFMT_ATI1"; 630 case SVGA3D_DEVCAP_SURFACEFMT_ATI2: 631 return "SVGA3D_DEVCAP_SURFACEFMT_ATI2"; 632 632 default: 633 633 return "UNEXPECTED"; … … 888 888 case SVGA3D_RS_TRANSPARENCYANTIALIAS: /* SVGA3dTransparencyAntialiasType */ 889 889 return "SVGA3D_RS_TRANSPARENCYANTIALIAS"; 890 case SVGA3D_RS_LINEAA: /* SVGA3dBool */891 return "SVGA3D_RS_LINEAA";892 890 case SVGA3D_RS_LINEWIDTH: /* float */ 893 891 return "SVGA3D_RS_LINEWIDTH"; -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win.cpp
r85938 r86009 799 799 break; 800 800 801 case SVGA3D_DEVCAP_SURFACEFMT_ BC4_UNORM:802 case SVGA3D_DEVCAP_SURFACEFMT_ BC5_UNORM:801 case SVGA3D_DEVCAP_SURFACEFMT_ATI1: 802 case SVGA3D_DEVCAP_SURFACEFMT_ATI2: 803 803 /* Unknown; only in DX10 & 11 */ 804 804 Log(("CAPS: Unknown CAP %s\n", vmsvga3dGetCapString(idx3dCaps))); … … 992 992 case SVGA3D_BUMPX8L8V8U8: 993 993 return D3DFMT_X8L8V8U8; 994 case SVGA3D_ BUMPL8V8U8:994 case SVGA3D_FORMAT_DEAD1: 995 995 /* No corresponding D3D9 equivalent. */ 996 996 AssertFailedReturn(D3DFMT_UNKNOWN); … … 1064 1064 return D3DFMT_G16R16; 1065 1065 1066 case SVGA3D_ BC4_UNORM:1067 case SVGA3D_ BC5_UNORM:1066 case SVGA3D_ATI1: 1067 case SVGA3D_ATI2: 1068 1068 /* Unknown; only in DX10 & 11 */ 1069 1069 break; … … 1071 1071 case SVGA3D_FORMAT_MAX: /* shut up MSC */ 1072 1072 case SVGA3D_FORMAT_INVALID: 1073 break; 1074 default: /** @todo Other formats. Avoid MSC warning for now. */ 1073 1075 break; 1074 1076 } … … 3408 3410 mode.uintValue = pRenderState[i].uintValue; 3409 3411 3410 switch (mode. s.function)3412 switch (mode.function) 3411 3413 { 3412 3414 case SVGA3D_FOGFUNC_INVALID: … … 3426 3428 break; 3427 3429 default: 3428 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode. s.function), VERR_INTERNAL_ERROR);3430 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode.function), VERR_INTERNAL_ERROR); 3429 3431 break; 3430 3432 } 3431 3433 3432 3434 /* The fog type determines the render state. */ 3433 switch (mode. s.type)3435 switch (mode.type) 3434 3436 { 3435 3437 case SVGA3D_FOGTYPE_VERTEX: … … 3440 3442 break; 3441 3443 default: 3442 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode. s.type), VERR_INTERNAL_ERROR);3444 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode.type), VERR_INTERNAL_ERROR); 3443 3445 break; 3444 3446 } 3445 3447 3446 3448 /* Set the fog base to depth or range. */ 3447 switch (mode. s.base)3449 switch (mode.base) 3448 3450 { 3449 3451 case SVGA3D_FOGBASE_DEPTHBASED: … … 3457 3459 default: 3458 3460 /* ignore */ 3459 AssertMsgFailed(("Unexpected fog base %d\n", mode. s.base));3461 AssertMsgFailed(("Unexpected fog base %d\n", mode.base)); 3460 3462 break; 3461 3463 } … … 3469 3471 mode.uintValue = pRenderState[i].uintValue; 3470 3472 3471 switch (mode. s.mode)3473 switch (mode.mode) 3472 3474 { 3473 3475 case SVGA3D_FILLMODE_POINT: … … 3481 3483 break; 3482 3484 default: 3483 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode. s.mode), VERR_INTERNAL_ERROR);3485 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode.mode), VERR_INTERNAL_ERROR); 3484 3486 break; 3485 3487 } … … 3896 3898 val = pRenderState[i].uintValue; 3897 3899 */ 3898 break;3899 3900 case SVGA3D_RS_LINEAA: /* SVGA3dBool */3901 renderState = D3DRS_ANTIALIASEDLINEENABLE;3902 val = pRenderState[i].uintValue;3903 3900 break; 3904 3901 … … 4602 4599 case SVGA3D_TS_BIND_TEXTURE: 4603 4600 AssertFailedBreak(); 4601 default: /** @todo Remaining TSs. Avoid MSC warning for now. */ 4602 break; 4604 4603 } 4605 4604 … … 4829 4828 4830 4829 Log(("vmsvga3dSetClipPlane %x %d (%d,%d)(%d,%d)\n", cid, index, (unsigned)(plane[0] * 100.0), (unsigned)(plane[1] * 100.0), (unsigned)(plane[2] * 100.0), (unsigned)(plane[3] * 100.0))); 4831 AssertReturn(index < SVGA3D_ CLIPPLANE_MAX, VERR_INVALID_PARAMETER);4830 AssertReturn(index < SVGA3D_NUM_CLIPPLANES, VERR_INVALID_PARAMETER); 4832 4831 4833 4832 int rc = vmsvga3dContextFromCid(pState, cid, &pContext); … … 5761 5760 Log(("ConstantB %d: value=%d, %d, %d, %d\n", reg + i, pValues[i*4 + 0], pValues[i*4 + 1], pValues[i*4 + 2], pValues[i*4 + 3])); 5762 5761 break; 5762 5763 default: 5764 AssertFailedReturn(VERR_INVALID_PARAMETER); 5763 5765 } 5764 5766 #endif -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.cpp
r85368 r86009 158 158 case SVGA3D_BUMPL6V5U5: 159 159 case SVGA3D_BUMPX8L8V8U8: 160 case SVGA3D_BUMPL8V8U8:161 160 case SVGA3D_V8U8: 162 161 case SVGA3D_Q8W8V8U8: … … 193 192 case SVGA3D_NV12: 194 193 case SVGA3D_AYUV: 195 case SVGA3D_ BC4_UNORM:196 case SVGA3D_ BC5_UNORM:194 case SVGA3D_ATI1: 195 case SVGA3D_ATI2: 197 196 break; 198 197 … … 482 481 * @param paBoxes . 483 482 */ 484 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA 3dGuestImage guest, SVGA3dSurfaceImageId host,483 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAGuestImage guest, SVGA3dSurfaceImageId host, 485 484 SVGA3dTransferType transfer, uint32_t cCopyBoxes, SVGA3dCopyBox *paBoxes) 486 485 { … … 852 851 853 852 SVGA3dCopyBox box; 854 SVGA 3dGuestImage dest;853 SVGAGuestImage dest; 855 854 856 855 box.srcz = 0; -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.h
r85368 r86009 22 22 #endif 23 23 24 #include "vmsvga/svga3d_reg.h" 25 #include "vmsvga/svga_escape.h" 26 #include "vmsvga/svga_overlay.h" 24 #include "DevVGA-SVGA.h" 27 25 28 26 … … 74 72 SVGA3dSurfaceImageId const *pDstSfcImg, SVGA3dBox const *pDstBox, 75 73 SVGA3dSurfaceImageId const *pSrcSfcImg, SVGA3dBox const *pSrcBox, SVGA3dStretchBltMode enmMode); 76 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA 3dGuestImage guest, SVGA3dSurfaceImageId host, SVGA3dTransferType transfer, uint32_t cCopyBoxes, SVGA3dCopyBox *pBoxes);74 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAGuestImage guest, SVGA3dSurfaceImageId host, SVGA3dTransferType transfer, uint32_t cCopyBoxes, SVGA3dCopyBox *pBoxes); 77 75 int vmsvga3dSurfaceBlitToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t dest, SVGASignedRect destRect, SVGA3dSurfaceImageId srcImage, SVGASignedRect srcRect, uint32_t cRects, SVGASignedRect *pRect); 78 76 -
trunk/src/VBox/Devices/Makefile.kmk
r85789 r86009 287 287 ifdef VBOX_WITH_VMSVGA 288 288 VBoxDD_DEFS += VBOX_WITH_VMSVGA 289 VBoxDD_INCS += $(VBOX_PATH_VMSVGA_INC) 289 290 VBoxDD_SOURCES += Graphics/DevVGA-SVGA.cpp 290 291 endif … … 1112 1113 VBoxDDR0_DEFS.win += VBOX_WITH_WIN_PARPORT_SUP 1113 1114 VBoxDDR0_INCS = build $(VBOX_GRAPHICS_INCS) 1115 VBoxDDR0_INCS += $(VBOX_PATH_VMSVGA_INC) 1114 1116 VBoxDDR0_SDKS.win = ReorderCompilerIncs $(VBOX_WINPSDK) $(VBOX_WINDDK) 1115 1117 VBoxDDR0_SOURCES = \ -
trunk/src/VBox/Devices/testcase/Makefile.kmk
r82968 r86009 92 92 $(VBOX_PATH_DEVICES_SRC)/Bus \ 93 93 $(VBOX_DEVICES_TEST_OUT_DIR) \ 94 $(VBOX_GRAPHICS_INCS) 94 $(VBOX_GRAPHICS_INCS) \ 95 $(VBOX_PATH_VMSVGA_INC) 95 96 tstDeviceStructSize_SOURCES = tstDeviceStructSize.cpp 96 97 tstDeviceStructSize_CLEAN = \
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