- Timestamp:
- Sep 2, 2020 11:13:07 PM (4 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Config.kmk
r86009 r86011 26 26 ifndef VBOX_VMM_CONFIG_KMK_INCLUDED 27 27 include $(PATH_ROOT)/src/VBox/VMM/Config.kmk 28 endif29 30 # We need the Additions/3D/Config.kmk for the VBOX_PATH_VMSVGA_INC variable.31 ifndef VBOX_MESA3D_CONFIG_KMK_INCLUDED32 include $(PATH_ROOT)/src/VBox/Additions/3D/Config.kmk33 28 endif 34 29 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r86009 r86011 162 162 163 163 #include "DevVGA-SVGA.h" 164 #include "vmsvga/svga_escape.h" 165 #include "vmsvga/svga_overlay.h" 166 #include "vmsvga/svga3d_caps.h" 164 167 #ifdef VBOX_WITH_VMSVGA3D 165 168 # include "DevVGA-SVGA3d.h" … … 2568 2571 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); 2569 2572 break; 2570 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ ATI1:2571 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ ATI1= %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));2572 break; 2573 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ ATI2:2574 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ ATI2= %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));2573 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM: 2574 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); 2575 break; 2576 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM: 2577 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); 2575 2578 break; 2576 2579 case SVGA_FIFO_3D_CAPS_LAST: … … 3914 3917 * Process the command. 3915 3918 */ 3916 /* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler 3917 * warning. Because we support some obsolete and deprecated commands, which are not included in 3918 * the SVGAFifoCmdId enum in the VMSVGA headers anymore. 3919 */ 3920 uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)]; 3919 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)]; 3921 3920 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); 3922 3921 LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n", … … 4498 4497 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb); 4499 4498 4500 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format. bitsPerPixel, pCmd->format.colorDepth));4499 Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth)); 4501 4500 pSVGAState->GMRFB.ptr = pCmd->ptr; 4502 4501 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine; … … 4521 4520 4522 4521 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */ 4523 AssertBreak(pSVGAState->GMRFB.format. bitsPerPixel == pScreen->cBpp);4522 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp); 4524 4523 4525 4524 /* Clip destRect to the screen dimensions. */ … … 4563 4562 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */ 4564 4563 SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr; 4565 uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format. bitsPerPixel, 8)) / 84564 uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8 4566 4565 + pSVGAState->GMRFB.bytesPerLine * srcy; 4567 4566 int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine; … … 4592 4591 AssertPtrBreak(pScreen); 4593 4592 4594 /** @todo Support GMRFB.format. bitsPerPixel != pThis->svga.uBpp? */4595 AssertBreak(pSVGAState->GMRFB.format. bitsPerPixel == pScreen->cBpp);4593 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */ 4594 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp); 4596 4595 4597 4596 /* Clip destRect to the screen dimensions. */ … … 4635 4634 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */ 4636 4635 SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr; 4637 uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format. bitsPerPixel, 8)) / 84636 uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8 4638 4637 + pSVGAState->GMRFB.bytesPerLine * dsty; 4639 4638 int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine; … … 4653 4652 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill); 4654 4653 4655 Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color. r, pCmd->color.g, pCmd->color.b));4654 Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b)); 4656 4655 pSVGAState->colorAnnotation = pCmd->color; 4657 4656 break; … … 4676 4675 RT_UNTRUSTED_VALIDATED_FENCE(); 4677 4676 4678 /* All 3d commands start with a common header, which defines the identifier and the size 4679 * of the command. The identifier has been already read from FIFO. Fetch the size. 4680 */ 4681 uint32_t *pcbCmd; 4682 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd)); 4683 uint32_t const cbCmd = *pcbCmd; 4684 AssertBreak(cbCmd < pThis->svga.cbFIFO); 4685 uint32_t *pu32Cmd; 4686 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd); 4687 pu32Cmd++; /* Skip the command size. */ 4677 /* All 3d commands start with a common header, which defines the size of the command. */ 4678 SVGA3dCmdHeader *pHdr; 4679 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr)); 4680 AssertBreak(pHdr->size < pThis->svga.cbFIFO); 4681 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size; 4682 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd); 4688 4683 4689 4684 if (RT_LIKELY(pThis->svga.f3DEnabled)) … … 4701 4696 # define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \ 4702 4697 if (1) { \ 4703 AssertMsgBreak( cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \4698 AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \ 4704 4699 RT_UNTRUSTED_VALIDATED_FENCE(); \ 4705 4700 } else do {} while (0) … … 4709 4704 { 4710 4705 uint32_t cMipLevels; 4711 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *) pu32Cmd;4706 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1); 4712 4707 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4713 4708 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine); 4714 4709 4715 cMipLevels = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dSize);4710 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize); 4716 4711 rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0, 4717 4712 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1)); … … 4725 4720 { 4726 4721 uint32_t cMipLevels; 4727 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *) pu32Cmd;4722 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1); 4728 4723 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4729 4724 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2); 4730 4725 4731 cMipLevels = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dSize);4726 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize); 4732 4727 rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face, 4733 4728 pCmd->multisampleCount, pCmd->autogenFilter, … … 4738 4733 case SVGA_3D_CMD_SURFACE_DESTROY: 4739 4734 { 4740 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *) pu32Cmd;4735 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1); 4741 4736 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4742 4737 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy); … … 4748 4743 { 4749 4744 uint32_t cCopyBoxes; 4750 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *) pu32Cmd;4745 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1); 4751 4746 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4752 4747 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy); 4753 4748 4754 cCopyBoxes = ( cbCmd- sizeof(pCmd)) / sizeof(SVGA3dCopyBox);4749 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox); 4755 4750 rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1)); 4756 4751 break; … … 4759 4754 case SVGA_3D_CMD_SURFACE_STRETCHBLT: 4760 4755 { 4761 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *) pu32Cmd;4756 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1); 4762 4757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4763 4758 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt); … … 4771 4766 { 4772 4767 uint32_t cCopyBoxes; 4773 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *) pu32Cmd;4768 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1); 4774 4769 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4775 4770 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma); … … 4778 4773 if (LogRelIs3Enabled()) 4779 4774 u64NanoTS = RTTimeNanoTS(); 4780 cCopyBoxes = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);4775 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox); 4781 4776 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a); 4782 4777 rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer, … … 4800 4795 { 4801 4796 uint32_t cRects; 4802 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *) pu32Cmd;4797 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1); 4803 4798 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4804 4799 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen); … … 4810 4805 if (LogRelIs3Enabled()) 4811 4806 u64NanoTS = RTTimeNanoTS(); 4812 cRects = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGASignedRect);4807 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect); 4813 4808 STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a); 4814 4809 rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, … … 4841 4836 case SVGA_3D_CMD_CONTEXT_DEFINE: 4842 4837 { 4843 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *) pu32Cmd;4838 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1); 4844 4839 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4845 4840 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine); … … 4851 4846 case SVGA_3D_CMD_CONTEXT_DESTROY: 4852 4847 { 4853 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *) pu32Cmd;4848 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1); 4854 4849 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4855 4850 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy); … … 4861 4856 case SVGA_3D_CMD_SETTRANSFORM: 4862 4857 { 4863 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *) pu32Cmd;4858 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1); 4864 4859 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4865 4860 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform); … … 4871 4866 case SVGA_3D_CMD_SETZRANGE: 4872 4867 { 4873 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *) pu32Cmd;4868 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1); 4874 4869 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4875 4870 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange); … … 4882 4877 { 4883 4878 uint32_t cRenderStates; 4884 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *) pu32Cmd;4879 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1); 4885 4880 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4886 4881 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState); 4887 4882 4888 cRenderStates = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dRenderState);4883 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState); 4889 4884 rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1)); 4890 4885 break; … … 4893 4888 case SVGA_3D_CMD_SETRENDERTARGET: 4894 4889 { 4895 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *) pu32Cmd;4890 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1); 4896 4891 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4897 4892 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget); … … 4904 4899 { 4905 4900 uint32_t cTextureStates; 4906 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *) pu32Cmd;4901 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1); 4907 4902 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4908 4903 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState); 4909 4904 4910 cTextureStates = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dTextureState);4905 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState); 4911 4906 rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1)); 4912 4907 break; … … 4915 4910 case SVGA_3D_CMD_SETMATERIAL: 4916 4911 { 4917 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *) pu32Cmd;4912 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1); 4918 4913 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4919 4914 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial); … … 4925 4920 case SVGA_3D_CMD_SETLIGHTDATA: 4926 4921 { 4927 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *) pu32Cmd;4922 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1); 4928 4923 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4929 4924 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData); … … 4935 4930 case SVGA_3D_CMD_SETLIGHTENABLED: 4936 4931 { 4937 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *) pu32Cmd;4932 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1); 4938 4933 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4939 4934 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable); … … 4945 4940 case SVGA_3D_CMD_SETVIEWPORT: 4946 4941 { 4947 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *) pu32Cmd;4942 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1); 4948 4943 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4949 4944 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort); … … 4955 4950 case SVGA_3D_CMD_SETCLIPPLANE: 4956 4951 { 4957 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *) pu32Cmd;4952 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1); 4958 4953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4959 4954 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane); … … 4965 4960 case SVGA_3D_CMD_CLEAR: 4966 4961 { 4967 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *) pu32Cmd;4962 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1); 4968 4963 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4969 4964 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear); 4970 4965 4971 uint32_t cRects = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dRect);4966 uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect); 4972 4967 rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1)); 4973 4968 break; … … 4977 4972 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */ 4978 4973 { 4979 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *) pu32Cmd;4974 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1); 4980 4975 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4981 4976 if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT) … … 4984 4979 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack); 4985 4980 4986 uint32_t cRects = ( cbCmd- sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);4981 uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect); 4987 4982 4988 4983 STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a); … … 4994 4989 case SVGA_3D_CMD_SHADER_DEFINE: 4995 4990 { 4996 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *) pu32Cmd;4991 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1); 4997 4992 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 4998 4993 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine); 4999 4994 5000 uint32_t cbData = ( cbCmd- sizeof(*pCmd));4995 uint32_t cbData = (pHdr->size - sizeof(*pCmd)); 5001 4996 rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1)); 5002 4997 break; … … 5005 5000 case SVGA_3D_CMD_SHADER_DESTROY: 5006 5001 { 5007 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *) pu32Cmd;5002 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1); 5008 5003 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5009 5004 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy); … … 5015 5010 case SVGA_3D_CMD_SET_SHADER: 5016 5011 { 5017 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *) pu32Cmd;5012 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1); 5018 5013 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5019 5014 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader); … … 5025 5020 case SVGA_3D_CMD_SET_SHADER_CONST: 5026 5021 { 5027 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *) pu32Cmd;5022 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1); 5028 5023 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5029 5024 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst); 5030 5025 5031 uint32_t cRegisters = ( cbCmd- sizeof(*pCmd)) / sizeof(pCmd->values) + 1;5026 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1; 5032 5027 rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values); 5033 5028 break; … … 5036 5031 case SVGA_3D_CMD_DRAW_PRIMITIVES: 5037 5032 { 5038 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *) pu32Cmd;5033 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1); 5039 5034 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5040 5035 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives); … … 5044 5039 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl) 5045 5040 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange); 5046 ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= cbCmd- sizeof(*pCmd));5047 5048 uint32_t cVertexDivisor = ( cbCmd- sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);5041 ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd)); 5042 5043 uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t); 5049 5044 AssertBreak(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls); 5050 5045 … … 5064 5059 case SVGA_3D_CMD_SETSCISSORRECT: 5065 5060 { 5066 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *) pu32Cmd;5061 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1); 5067 5062 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5068 5063 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect); … … 5074 5069 case SVGA_3D_CMD_BEGIN_QUERY: 5075 5070 { 5076 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *) pu32Cmd;5071 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1); 5077 5072 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5078 5073 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery); … … 5084 5079 case SVGA_3D_CMD_END_QUERY: 5085 5080 { 5086 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *) pu32Cmd;5081 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1); 5087 5082 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5088 5083 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery); … … 5094 5089 case SVGA_3D_CMD_WAIT_FOR_QUERY: 5095 5090 { 5096 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *) pu32Cmd;5091 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1); 5097 5092 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5098 5093 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery); … … 5104 5099 case SVGA_3D_CMD_GENERATE_MIPMAPS: 5105 5100 { 5106 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *) pu32Cmd;5101 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1); 5107 5102 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); 5108 5103 STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps); … … 6424 6419 "xSURFACEFMT_Z_DF24", 6425 6420 "xSURFACEFMT_Z_D24S8_INT", 6426 "xSURFACEFMT_ ATI1",6427 "xSURFACEFMT_ ATI2", /* 83 */6421 "xSURFACEFMT_BC4_UNORM", 6422 "xSURFACEFMT_BC5_UNORM", /* 83 */ 6428 6423 }; 6429 6424 … … 6452 6447 6453 6448 /* Fill out all 3d capabilities. */ 6454 /** @todo The current implementation stores the capabilities in the FIFO. 6455 * Newer VMSVGA uses SVGA_REG_DEV_CAP register to query 3d caps. 6456 * Prerequisite for the new interface is support for SVGA_CAP_GBOBJECTS. 6457 */ 6458 AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1); 6459 for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; i++) 6449 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++) 6460 6450 { 6461 6451 uint32_t val = 0; -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h
r86009 r86011 25 25 #endif 26 26 27 #include <VBox/pci.h>28 #include <VBox/vmm/pdmifs.h>29 27 #include <VBox/vmm/pdmthread.h> 30 #include <VBox/vmm/stam.h> 31 32 /* 33 * PCI device IDs. 34 */ 35 #ifndef PCI_VENDOR_ID_VMWARE 36 # define PCI_VENDOR_ID_VMWARE 0x15AD 37 #endif 38 #ifndef PCI_DEVICE_ID_VMWARE_SVGA2 39 # define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 40 #endif 41 42 /* For "svga_overlay.h" */ 43 #ifndef TRUE 44 # define TRUE 1 45 #endif 46 #ifndef FALSE 47 # define FALSE 0 48 #endif 49 50 #include <svga3d_caps.h> 51 #include <svga3d_reg.h> 52 #include <svga3d_shaderdefs.h> 53 #include <svga_escape.h> 54 #include <svga_overlay.h> 55 56 /* Deprecated. */ 57 #define SVGA_CMD_RECT_FILL 2 58 #define SVGA_CMD_DISPLAY_CURSOR 20 59 #define SVGA_CMD_MOVE_CURSOR 21 60 61 /* 62 * SVGA_CMD_RECT_FILL -- 63 * 64 * Fill a rectangular area in the the GFB, and copy the result 65 * to any screens which intersect it. 66 * 67 * Deprecated? 68 * 69 * Availability: 70 * SVGA_CAP_RECT_FILL 71 */ 72 73 typedef 74 struct { 75 uint32_t pixel; 76 uint32_t destX; 77 uint32_t destY; 78 uint32_t width; 79 uint32_t height; 80 } SVGAFifoCmdRectFill; 81 82 /* 83 * SVGA_CMD_DISPLAY_CURSOR -- 84 * 85 * Turn the cursor on or off. 86 * 87 * Deprecated. 88 * 89 * Availability: 90 * SVGA_CAP_CURSOR? 91 */ 92 93 typedef 94 struct { 95 uint32_t id; // Reserved, must be zero. 96 uint32_t state; // 0=off 97 } SVGAFifoCmdDisplayCursor; 98 99 /* 100 * SVGA_CMD_MOVE_CURSOR -- 101 * 102 * Set the cursor position. 103 * 104 * Deprecated. 105 * 106 * Availability: 107 * SVGA_CAP_CURSOR? 108 */ 109 110 typedef 111 struct { 112 SVGASignedPoint pos; 113 } SVGAFifoCmdMoveCursor; 114 28 29 #include "vmsvga/svga3d_reg.h" 115 30 116 31 /** Default FIFO size. */ -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-hlp.cpp
r86009 r86011 24 24 #include <iprt/types.h> 25 25 26 #include "DevVGA-SVGA.h" 26 #include "vmsvga/svga3d_reg.h" 27 #include "vmsvga/svga3d_shaderdefs.h" 27 28 28 29 typedef struct VMSVGA3DSHADERPARSECONTEXT … … 97 98 src.value = *pToken; 98 99 99 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src. type_upper << 3 | src.type_lower);100 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src.s.type_upper << 3 | src.s.type_lower); 100 101 Log3(("Src: type %d, r0 %d, srcMod %d, swizzle 0x%x, r1 %d, relAddr %d, num %d\n", 101 regType, src. reserved0, src.srcMod, src.swizzle, src.reserved1, src.relAddr, src.num));102 103 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src. num);102 regType, src.s.reserved0, src.s.srcMod, src.s.swizzle, src.s.reserved1, src.s.relAddr, src.s.num)); 103 104 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src.s.num); 104 105 } 105 106 #endif … … 112 113 dest.value = *pToken; 113 114 114 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest. type_upper << 3 | dest.type_lower);115 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest.s.type_upper << 3 | dest.s.type_lower); 115 116 Log3(("Dest: type %d, r0 %d, shfScale %d, dstMod %d, mask 0x%x, r1 %d, relAddr %d, num %d\n", 116 regType, dest. reserved0, dest.shfScale, dest.dstMod, dest.mask, dest.reserved1, dest.relAddr, dest.num));117 118 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest. num);117 regType, dest.s.reserved0, dest.s.shfScale, dest.s.dstMod, dest.s.mask, dest.s.reserved1, dest.s.relAddr, dest.s.num)); 118 119 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest.s.num); 119 120 } 120 121 … … 125 126 a.values[1] = pToken[1]; // dst 126 127 127 return vmsvga3dShaderParseDestToken(pCtx, (uint32_t *)&a. dst);128 return vmsvga3dShaderParseDestToken(pCtx, (uint32_t *)&a.s2.dst); 128 129 } 129 130 … … 159 160 /* "The first token must be a version token." */ 160 161 SVGA3dShaderVersion const *pVersion = (SVGA3dShaderVersion const *)paTokensStart; 161 ASSERT_GUEST_RETURN( pVersion-> type == SVGA3D_VS_TYPE162 || pVersion-> type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR);162 ASSERT_GUEST_RETURN( pVersion->s.type == SVGA3D_VS_TYPE 163 || pVersion->s.type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR); 163 164 164 165 VMSVGA3DSHADERPARSECONTEXT ctx; 165 ctx.type = pVersion-> type;166 ctx.type = pVersion->s.type; 166 167 167 168 /* Scan the tokens. Immediately return an error code on any unexpected data. */ … … 174 175 /* Figure out the instruction length, which is how many tokens follow the instruction token. */ 175 176 uint32_t cInstLen; 176 if (token. op == SVGA3DOP_COMMENT)177 cInstLen = token. comment_size;177 if (token.s1.op == SVGA3DOP_COMMENT) 178 cInstLen = token.s.comment_size; 178 179 else 179 cInstLen = token.s ize;180 181 Log3(("op %d, cInstLen %d\n", token. op, cInstLen));180 cInstLen = token.s1.size; 181 182 Log3(("op %d, cInstLen %d\n", token.s1.op, cInstLen)); 182 183 183 184 ASSERT_GUEST_RETURN(cInstLen < paTokensEnd - pToken, VERR_PARSE_ERROR); 184 185 185 if (token. op == SVGA3DOP_END)186 if (token.s1.op == SVGA3DOP_END) 186 187 { 187 188 ASSERT_GUEST_RETURN(token.value == 0x0000FFFF, VERR_PARSE_ERROR); … … 190 191 191 192 int rc; 192 switch (token. op)193 switch (token.s1.op) 193 194 { 194 195 case SVGA3DOP_DCL: -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-info.cpp
r86009 r86011 73 73 { SVGA3D_BUMPL6V5U5 , "BUMPL6V5U5" }, 74 74 { SVGA3D_BUMPX8L8V8U8 , "BUMPX8L8V8U8" }, 75 { SVGA3D_ FORMAT_DEAD1 , "FORMAT_DEAD1" },75 { SVGA3D_BUMPL8V8U8 , "BUMPL8V8U8" }, 76 76 { SVGA3D_ARGB_S10E5 , "ARGB_S10E5" }, 77 77 { SVGA3D_ARGB_S23E8 , "ARGB_S23E8" }, … … 96 96 { SVGA3D_NV12 , "NV12" }, 97 97 { SVGA3D_AYUV , "AYUV" }, 98 { SVGA3D_ ATI1 , "ATI1" },99 { SVGA3D_ ATI2 , "ATI2" },98 { SVGA3D_BC4_UNORM , "BC4_UNORM" }, 99 { SVGA3D_BC5_UNORM , "BC5_UNORM" }, 100 100 { SVGA3D_Z_DF16 , "Z_DF16" }, 101 101 { SVGA3D_Z_DF24 , "Z_DF24" }, … … 682 682 *pEnumMap->pfAsserted = true; 683 683 for (uint32_t i = 1; i < pEnumMap->cValues; i++) 684 AssertMsg(paValues[i - 1].iValue <= paValues[i].iValue, 685 ("i = %d: %d followed by %d", i, paValues[i - 1].iValue, paValues[i].iValue)); 684 Assert(paValues[i - 1].iValue <= paValues[i].iValue); 686 685 } 687 686 #endif … … 1011 1010 case SVGA3D_BUMPL6V5U5: 1012 1011 case SVGA3D_BUMPX8L8V8U8: 1013 case SVGA3D_ FORMAT_DEAD1:1012 case SVGA3D_BUMPL8V8U8: 1014 1013 case SVGA3D_ARGB_S10E5: 1015 1014 case SVGA3D_ARGB_S23E8: … … 1029 1028 case SVGA3D_NV12: 1030 1029 case SVGA3D_AYUV: 1031 case SVGA3D_ ATI1:1032 case SVGA3D_ ATI2:1030 case SVGA3D_BC4_UNORM: 1031 case SVGA3D_BC5_UNORM: 1033 1032 case SVGA3D_Z_DF16: 1034 1033 case SVGA3D_Z_DF24: … … 1227 1226 "e" "BLENDEQUATIONALPHA", /* SVGA3dBlendEquation */ 1228 1227 "*" "TRANSPARENCYANTIALIAS", /* SVGA3dTransparencyAntialiasType */ 1228 "f" "LINEAA", /* SVGA3dBool */ 1229 1229 "r" "LINEWIDTH", /* float */ 1230 1230 }; … … 1265 1265 case 'c': //SVGA3dColor, SVGA3dColorMask 1266 1266 RTStrPrintf(pszBuffer, cbBuffer, "%s = RGBA(%d,%d,%d,%d) (%#x)", pszName, 1267 uValue.Color. red, uValue.Color.green, uValue.Color.blue, uValue.Color.alpha, uValue.u);1267 uValue.Color.s.red, uValue.Color.s.green, uValue.Color.s.blue, uValue.Color.s.alpha, uValue.u); 1268 1268 break; 1269 1269 case 'w': //SVGA3dWrapFlags … … 1392 1392 case 'c': //SVGA3dColor, SVGA3dColorMask 1393 1393 RTStrPrintf(pszBuffer, cbBuffer, "%s = RGBA(%d,%d,%d,%d) (%#x)", pszName, 1394 uValue.Color. red, uValue.Color.green, uValue.Color.blue, uValue.Color.alpha, uValue.u);1394 uValue.Color.s.red, uValue.Color.s.green, uValue.Color.s.blue, uValue.Color.s.alpha, uValue.u); 1395 1395 break; 1396 1396 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-internal.h
r86009 r86011 87 87 #endif 88 88 89 #include "vmsvga/svga3d_shaderdefs.h" 89 90 #ifdef VMSVGA3D_OPENGL 90 91 # include "vmsvga_glext/glext.h" … … 862 863 VMSVGATRANSFORMSTATE aTransformState[SVGA3D_TRANSFORM_MAX]; 863 864 VMSVGAMATERIALSTATE aMaterial[SVGA3D_FACE_MAX]; 864 /* The aClipPlane array has a wrong (greater) size. Keep it for now because the array is a part of the saved state. */ 865 /** @todo Replace SVGA3D_CLIPPLANE_5 with SVGA3D_NUM_CLIPPLANES and increase the saved state version. */ 866 VMSVGACLIPPLANESTATE aClipPlane[SVGA3D_CLIPPLANE_5]; 865 VMSVGACLIPPLANESTATE aClipPlane[SVGA3D_CLIPPLANE_MAX]; 867 866 VMSVGALIGHTSTATE aLightData[SVGA3D_MAX_LIGHTS]; 868 867 -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-ogl.cpp
r86009 r86011 1097 1097 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80, 1098 1098 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81, 1099 SVGA3D_DEVCAP_SURFACEFMT_ ATI1= 82,1100 SVGA3D_DEVCAP_SURFACEFMT_ ATI2= 83,1099 SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82, 1100 SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83, 1101 1101 #endif 1102 1102 … … 1624 1624 1625 1625 /* Linux: Not referenced in current sources. */ 1626 case SVGA3D_DEVCAP_SURFACEFMT_ ATI1:1627 case SVGA3D_DEVCAP_SURFACEFMT_ ATI2:1626 case SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM: 1627 case SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM: 1628 1628 Log(("CAPS: Unknown CAP %s\n", vmsvga3dGetCapString(idx3dCaps))); 1629 1629 rc = VERR_INVALID_PARAMETER; … … 1812 1812 case SVGA3D_BUMPX8L8V8U8: 1813 1813 return D3DFMT_X8L8V8U8; 1814 case SVGA3D_ FORMAT_DEAD1:1814 case SVGA3D_BUMPL8V8U8: 1815 1815 /* No corresponding D3D9 equivalent. */ 1816 1816 AssertFailedReturn(D3DFMT_UNKNOWN); … … 1963 1963 return (D3DFORMAT)MAKEFOURCC('A', 'Y', 'U', 'V'); 1964 1964 1965 case SVGA3D_ ATI1:1966 case SVGA3D_ ATI2:1965 case SVGA3D_BC4_UNORM: 1966 case SVGA3D_BC5_UNORM: 1967 1967 /* Unknown; only in DX10 & 11 */ 1968 1968 break; … … 4479 4479 case SVGA3D_RS_CLIPPLANEENABLE: /* SVGA3dClipPlanes */ 4480 4480 { 4481 for (uint32_t j = 0; j < SVGA3D_NUM_CLIPPLANES; j++) 4481 AssertCompile(SVGA3D_CLIPPLANE_MAX == (1 << 5)); 4482 for (uint32_t j = 0; j <= 5; j++) 4482 4483 { 4483 4484 if (pRenderState[i].uintValue & RT_BIT(j)) … … 4527 4528 4528 4529 enableCap = GL_FOG_MODE; 4529 switch (mode. function)4530 switch (mode.s.function) 4530 4531 { 4531 4532 case SVGA3D_FOGFUNC_EXP: … … 4539 4540 break; 4540 4541 default: 4541 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode. function), VERR_INTERNAL_ERROR);4542 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode.s.function), VERR_INTERNAL_ERROR); 4542 4543 break; 4543 4544 } 4544 4545 4545 4546 /** @todo how to switch between vertex and pixel fog modes??? */ 4546 Assert(mode. type == SVGA3D_FOGTYPE_PIXEL);4547 Assert(mode.s.type == SVGA3D_FOGTYPE_PIXEL); 4547 4548 #if 0 4548 4549 /* The fog type determines the render state. */ 4549 switch (mode. type)4550 switch (mode.s.type) 4550 4551 { 4551 4552 case SVGA3D_FOGTYPE_VERTEX: … … 4556 4557 break; 4557 4558 default: 4558 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode. type), VERR_INTERNAL_ERROR);4559 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode.s.type), VERR_INTERNAL_ERROR); 4559 4560 break; 4560 4561 } … … 4562 4563 4563 4564 /* Set the fog base to depth or range. */ 4564 switch (mode. base)4565 switch (mode.s.base) 4565 4566 { 4566 4567 case SVGA3D_FOGBASE_DEPTHBASED: … … 4574 4575 default: 4575 4576 /* ignore */ 4576 AssertMsgFailed(("Unexpected fog base %d\n", mode. base));4577 AssertMsgFailed(("Unexpected fog base %d\n", mode.s.base)); 4577 4578 break; 4578 4579 } … … 4586 4587 mode.uintValue = pRenderState[i].uintValue; 4587 4588 4588 switch (mode. mode)4589 switch (mode.s.mode) 4589 4590 { 4590 4591 case SVGA3D_FILLMODE_POINT: … … 4598 4599 break; 4599 4600 default: 4600 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode. mode), VERR_INTERNAL_ERROR);4601 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode.s.mode), VERR_INTERNAL_ERROR); 4601 4602 break; 4602 4603 } 4603 4604 /* Only front and back faces. Also recent Mesa guest drivers initialize the 'face' to zero. */ 4604 ASSERT_GUEST(mode. face == SVGA3D_FACE_FRONT_BACK || mode.face == SVGA3D_FACE_INVALID);4605 ASSERT_GUEST(mode.s.face == SVGA3D_FACE_FRONT_BACK || mode.s.face == SVGA3D_FACE_INVALID); 4605 4606 glPolygonMode(GL_FRONT_AND_BACK, val); 4606 4607 VMSVGA3D_CHECK_LAST_ERROR(pState, pContext); … … 4638 4639 break; 4639 4640 4640 case SVGA3D_RS_ ANTIALIASEDLINEENABLE:/* SVGA3dBool */4641 case SVGA3D_RS_LINEAA: /* SVGA3dBool */ 4641 4642 enableCap = GL_LINE_SMOOTH; 4642 4643 val = pRenderState[i].uintValue; … … 5041 5042 mask.uintValue = pRenderState[i].uintValue; 5042 5043 5043 red = mask. red;5044 green = mask. green;5045 blue = mask. blue;5046 alpha = mask. alpha;5044 red = mask.s.red; 5045 green = mask.s.green; 5046 blue = mask.s.blue; 5047 alpha = mask.s.alpha; 5047 5048 5048 5049 glColorMask(red, green, blue, alpha); … … 5114 5115 5115 5116 case SVGA3D_RS_MULTISAMPLEMASK: /* uint32_t */ 5117 case SVGA3D_RS_ANTIALIASEDLINEENABLE: /* SVGA3dBool */ 5116 5118 Log(("vmsvga3dSetRenderState: WARNING not applicable??!!\n")); 5117 5119 break; … … 6202 6204 6203 6205 Log(("vmsvga3dSetClipPlane cid=%u %d (%d,%d)(%d,%d)\n", cid, index, (unsigned)(plane[0] * 100.0), (unsigned)(plane[1] * 100.0), (unsigned)(plane[2] * 100.0), (unsigned)(plane[3] * 100.0))); 6204 AssertReturn(index < SVGA3D_ NUM_CLIPPLANES, VERR_INVALID_PARAMETER);6206 AssertReturn(index < SVGA3D_CLIPPLANE_MAX, VERR_INVALID_PARAMETER); 6205 6207 6206 6208 PVMSVGA3DCONTEXT pContext; … … 6804 6806 VMSVGA3D_CHECK_LAST_ERROR(pState, pContext); 6805 6807 6806 GLuint divisor = paVertexDivisors && paVertexDivisors[index]. instanceData ? 1 : 0;6808 GLuint divisor = paVertexDivisors && paVertexDivisors[index].s.instanceData ? 1 : 0; 6807 6809 pState->ext.glVertexAttribDivisor(index, divisor); 6808 6810 VMSVGA3D_CHECK_LAST_ERROR(pState, pContext); … … 7068 7070 for (uint32_t iVertexDivisor = 0; iVertexDivisor < cVertexDivisor; ++iVertexDivisor) 7069 7071 { 7070 if (pVertexDivisor[iVertexDivisor]. indexedData)7072 if (pVertexDivisor[iVertexDivisor].s.indexedData) 7071 7073 { 7072 7074 if (cInstances == 0) 7073 cInstances = pVertexDivisor[iVertexDivisor]. count;7075 cInstances = pVertexDivisor[iVertexDivisor].s.count; 7074 7076 else 7075 Assert(cInstances == pVertexDivisor[iVertexDivisor]. count);7076 } 7077 else if (pVertexDivisor[iVertexDivisor]. instanceData)7078 { 7079 Assert(pVertexDivisor[iVertexDivisor]. count == 1);7077 Assert(cInstances == pVertexDivisor[iVertexDivisor].s.count); 7078 } 7079 else if (pVertexDivisor[iVertexDivisor].s.instanceData) 7080 { 7081 Assert(pVertexDivisor[iVertexDivisor].s.count == 1); 7080 7082 } 7081 7083 } … … 7581 7583 Log(("ConstantB %d: value=%d, %d, %d, %d\n", reg + i, pValues[i*4 + 0], pValues[i*4 + 1], pValues[i*4 + 2], pValues[i*4 + 3])); 7582 7584 break; 7583 7584 default:7585 AssertFailedReturn(VERR_INVALID_PARAMETER);7586 7585 } 7587 7586 #endif -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-shared.cpp
r86009 r86011 626 626 case SVGA3D_DEVCAP_SURFACEFMT_AYUV: 627 627 return "SVGA3D_DEVCAP_SURFACEFMT_AYUV"; 628 case SVGA3D_DEVCAP_SURFACEFMT_ ATI1:629 return "SVGA3D_DEVCAP_SURFACEFMT_ ATI1";630 case SVGA3D_DEVCAP_SURFACEFMT_ ATI2:631 return "SVGA3D_DEVCAP_SURFACEFMT_ ATI2";628 case SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM: 629 return "SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM"; 630 case SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM: 631 return "SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM"; 632 632 default: 633 633 return "UNEXPECTED"; … … 888 888 case SVGA3D_RS_TRANSPARENCYANTIALIAS: /* SVGA3dTransparencyAntialiasType */ 889 889 return "SVGA3D_RS_TRANSPARENCYANTIALIAS"; 890 case SVGA3D_RS_LINEAA: /* SVGA3dBool */ 891 return "SVGA3D_RS_LINEAA"; 890 892 case SVGA3D_RS_LINEWIDTH: /* float */ 891 893 return "SVGA3D_RS_LINEWIDTH"; -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win.cpp
r86009 r86011 799 799 break; 800 800 801 case SVGA3D_DEVCAP_SURFACEFMT_ ATI1:802 case SVGA3D_DEVCAP_SURFACEFMT_ ATI2:801 case SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM: 802 case SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM: 803 803 /* Unknown; only in DX10 & 11 */ 804 804 Log(("CAPS: Unknown CAP %s\n", vmsvga3dGetCapString(idx3dCaps))); … … 992 992 case SVGA3D_BUMPX8L8V8U8: 993 993 return D3DFMT_X8L8V8U8; 994 case SVGA3D_ FORMAT_DEAD1:994 case SVGA3D_BUMPL8V8U8: 995 995 /* No corresponding D3D9 equivalent. */ 996 996 AssertFailedReturn(D3DFMT_UNKNOWN); … … 1064 1064 return D3DFMT_G16R16; 1065 1065 1066 case SVGA3D_ ATI1:1067 case SVGA3D_ ATI2:1066 case SVGA3D_BC4_UNORM: 1067 case SVGA3D_BC5_UNORM: 1068 1068 /* Unknown; only in DX10 & 11 */ 1069 1069 break; … … 1071 1071 case SVGA3D_FORMAT_MAX: /* shut up MSC */ 1072 1072 case SVGA3D_FORMAT_INVALID: 1073 break;1074 default: /** @todo Other formats. Avoid MSC warning for now. */1075 1073 break; 1076 1074 } … … 3410 3408 mode.uintValue = pRenderState[i].uintValue; 3411 3409 3412 switch (mode. function)3410 switch (mode.s.function) 3413 3411 { 3414 3412 case SVGA3D_FOGFUNC_INVALID: … … 3428 3426 break; 3429 3427 default: 3430 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode. function), VERR_INTERNAL_ERROR);3428 AssertMsgFailedReturn(("Unexpected fog function %d\n", mode.s.function), VERR_INTERNAL_ERROR); 3431 3429 break; 3432 3430 } 3433 3431 3434 3432 /* The fog type determines the render state. */ 3435 switch (mode. type)3433 switch (mode.s.type) 3436 3434 { 3437 3435 case SVGA3D_FOGTYPE_VERTEX: … … 3442 3440 break; 3443 3441 default: 3444 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode. type), VERR_INTERNAL_ERROR);3442 AssertMsgFailedReturn(("Unexpected fog type %d\n", mode.s.type), VERR_INTERNAL_ERROR); 3445 3443 break; 3446 3444 } 3447 3445 3448 3446 /* Set the fog base to depth or range. */ 3449 switch (mode. base)3447 switch (mode.s.base) 3450 3448 { 3451 3449 case SVGA3D_FOGBASE_DEPTHBASED: … … 3459 3457 default: 3460 3458 /* ignore */ 3461 AssertMsgFailed(("Unexpected fog base %d\n", mode. base));3459 AssertMsgFailed(("Unexpected fog base %d\n", mode.s.base)); 3462 3460 break; 3463 3461 } … … 3471 3469 mode.uintValue = pRenderState[i].uintValue; 3472 3470 3473 switch (mode. mode)3471 switch (mode.s.mode) 3474 3472 { 3475 3473 case SVGA3D_FILLMODE_POINT: … … 3483 3481 break; 3484 3482 default: 3485 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode. mode), VERR_INTERNAL_ERROR);3483 AssertMsgFailedReturn(("Unexpected fill mode %d\n", mode.s.mode), VERR_INTERNAL_ERROR); 3486 3484 break; 3487 3485 } … … 3898 3896 val = pRenderState[i].uintValue; 3899 3897 */ 3898 break; 3899 3900 case SVGA3D_RS_LINEAA: /* SVGA3dBool */ 3901 renderState = D3DRS_ANTIALIASEDLINEENABLE; 3902 val = pRenderState[i].uintValue; 3900 3903 break; 3901 3904 … … 4599 4602 case SVGA3D_TS_BIND_TEXTURE: 4600 4603 AssertFailedBreak(); 4601 default: /** @todo Remaining TSs. Avoid MSC warning for now. */4602 break;4603 4604 } 4604 4605 … … 4828 4829 4829 4830 Log(("vmsvga3dSetClipPlane %x %d (%d,%d)(%d,%d)\n", cid, index, (unsigned)(plane[0] * 100.0), (unsigned)(plane[1] * 100.0), (unsigned)(plane[2] * 100.0), (unsigned)(plane[3] * 100.0))); 4830 AssertReturn(index < SVGA3D_ NUM_CLIPPLANES, VERR_INVALID_PARAMETER);4831 AssertReturn(index < SVGA3D_CLIPPLANE_MAX, VERR_INVALID_PARAMETER); 4831 4832 4832 4833 int rc = vmsvga3dContextFromCid(pState, cid, &pContext); … … 5760 5761 Log(("ConstantB %d: value=%d, %d, %d, %d\n", reg + i, pValues[i*4 + 0], pValues[i*4 + 1], pValues[i*4 + 2], pValues[i*4 + 3])); 5761 5762 break; 5762 5763 default:5764 AssertFailedReturn(VERR_INVALID_PARAMETER);5765 5763 } 5766 5764 #endif -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.cpp
r86009 r86011 158 158 case SVGA3D_BUMPL6V5U5: 159 159 case SVGA3D_BUMPX8L8V8U8: 160 case SVGA3D_BUMPL8V8U8: 160 161 case SVGA3D_V8U8: 161 162 case SVGA3D_Q8W8V8U8: … … 192 193 case SVGA3D_NV12: 193 194 case SVGA3D_AYUV: 194 case SVGA3D_ ATI1:195 case SVGA3D_ ATI2:195 case SVGA3D_BC4_UNORM: 196 case SVGA3D_BC5_UNORM: 196 197 break; 197 198 … … 481 482 * @param paBoxes . 482 483 */ 483 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA GuestImage guest, SVGA3dSurfaceImageId host,484 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dGuestImage guest, SVGA3dSurfaceImageId host, 484 485 SVGA3dTransferType transfer, uint32_t cCopyBoxes, SVGA3dCopyBox *paBoxes) 485 486 { … … 851 852 852 853 SVGA3dCopyBox box; 853 SVGA GuestImage dest;854 SVGA3dGuestImage dest; 854 855 855 856 box.srcz = 0; -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.h
r86009 r86011 22 22 #endif 23 23 24 #include "DevVGA-SVGA.h" 24 #include "vmsvga/svga3d_reg.h" 25 #include "vmsvga/svga_escape.h" 26 #include "vmsvga/svga_overlay.h" 25 27 26 28 … … 72 74 SVGA3dSurfaceImageId const *pDstSfcImg, SVGA3dBox const *pDstBox, 73 75 SVGA3dSurfaceImageId const *pSrcSfcImg, SVGA3dBox const *pSrcBox, SVGA3dStretchBltMode enmMode); 74 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA GuestImage guest, SVGA3dSurfaceImageId host, SVGA3dTransferType transfer, uint32_t cCopyBoxes, SVGA3dCopyBox *pBoxes);76 int vmsvga3dSurfaceDMA(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dGuestImage guest, SVGA3dSurfaceImageId host, SVGA3dTransferType transfer, uint32_t cCopyBoxes, SVGA3dCopyBox *pBoxes); 75 77 int vmsvga3dSurfaceBlitToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t dest, SVGASignedRect destRect, SVGA3dSurfaceImageId srcImage, SVGASignedRect srcRect, uint32_t cRects, SVGASignedRect *pRect); 76 78 -
trunk/src/VBox/Devices/Makefile.kmk
r86009 r86011 287 287 ifdef VBOX_WITH_VMSVGA 288 288 VBoxDD_DEFS += VBOX_WITH_VMSVGA 289 VBoxDD_INCS += $(VBOX_PATH_VMSVGA_INC)290 289 VBoxDD_SOURCES += Graphics/DevVGA-SVGA.cpp 291 290 endif … … 1113 1112 VBoxDDR0_DEFS.win += VBOX_WITH_WIN_PARPORT_SUP 1114 1113 VBoxDDR0_INCS = build $(VBOX_GRAPHICS_INCS) 1115 VBoxDDR0_INCS += $(VBOX_PATH_VMSVGA_INC)1116 1114 VBoxDDR0_SDKS.win = ReorderCompilerIncs $(VBOX_WINPSDK) $(VBOX_WINDDK) 1117 1115 VBoxDDR0_SOURCES = \ -
trunk/src/VBox/Devices/testcase/Makefile.kmk
r86009 r86011 92 92 $(VBOX_PATH_DEVICES_SRC)/Bus \ 93 93 $(VBOX_DEVICES_TEST_OUT_DIR) \ 94 $(VBOX_GRAPHICS_INCS) \ 95 $(VBOX_PATH_VMSVGA_INC) 94 $(VBOX_GRAPHICS_INCS) 96 95 tstDeviceStructSize_SOURCES = tstDeviceStructSize.cpp 97 96 tstDeviceStructSize_CLEAN = \
Note:
See TracChangeset
for help on using the changeset viewer.